diff --git a/lib/IR/Instructions.cpp b/lib/IR/Instructions.cpp
index 7ddf25b99a6..957db32d608 100644
--- a/lib/IR/Instructions.cpp
+++ b/lib/IR/Instructions.cpp
@@ -1246,12 +1246,12 @@ static Value *getAISize(LLVMContext &Context, Value *Amt) {
   return Amt;
 }
 
-Align computeAllocaDefaultAlign(Type *Ty, BasicBlock *BB) {
+static Align computeAllocaDefaultAlign(Type *Ty, BasicBlock *BB) {
   const DataLayout &DL = BB->getModule()->getDataLayout();
   return DL.getPrefTypeAlign(Ty);
 }
 
-Align computeAllocaDefaultAlign(Type *Ty, Instruction *I) {
+static Align computeAllocaDefaultAlign(Type *Ty, Instruction *I) {
   return computeAllocaDefaultAlign(Ty, I->getParent());
 }
 
@@ -1333,12 +1333,12 @@ void LoadInst::AssertOK() {
          "Alignment required for atomic load");
 }
 
-Align computeLoadStoreDefaultAlign(Type *Ty, BasicBlock *BB) {
+static Align computeLoadStoreDefaultAlign(Type *Ty, BasicBlock *BB) {
   const DataLayout &DL = BB->getModule()->getDataLayout();
   return DL.getABITypeAlign(Ty);
 }
 
-Align computeLoadStoreDefaultAlign(Type *Ty, Instruction *I) {
+static Align computeLoadStoreDefaultAlign(Type *Ty, Instruction *I) {
   return computeLoadStoreDefaultAlign(Ty, I->getParent());
 }
 
diff --git a/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/lib/Target/ARM/ARMExpandPseudoInsts.cpp
index f908f883fb2..49056d78302 100644
--- a/lib/Target/ARM/ARMExpandPseudoInsts.cpp
+++ b/lib/Target/ARM/ARMExpandPseudoInsts.cpp
@@ -960,9 +960,9 @@ void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
 // S0-S31 + FPSCR + 8 more bytes (VPR + pad, or just pad)
 static const int CMSE_FP_SAVE_SIZE = 136;
 
-void determineGPRegsToClear(const MachineInstr &MI,
-                            const std::initializer_list<unsigned> &Regs,
-                            SmallVectorImpl<unsigned> &ClearRegs) {
+static void determineGPRegsToClear(const MachineInstr &MI,
+                                   const std::initializer_list<unsigned> &Regs,
+                                   SmallVectorImpl<unsigned> &ClearRegs) {
   SmallVector<unsigned, 4> OpRegs;
   for (const MachineOperand &Op : MI.operands()) {
     if (!Op.isReg() || !Op.isUse())
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 655147076a4..08f455b8bf2 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -3330,6 +3330,7 @@ static bool isSortedByValueNo(ArrayRef<CCValAssign> ArgLocs) {
 }
 #endif
 
+namespace {
 /// This is a helper class for lowering variable arguments parameters.
 class VarArgsLoweringHelper {
 public:
@@ -3367,6 +3368,7 @@ private:
   CallingConv::ID CallConv;
   CCState &CCInfo;
 };
+} // namespace
 
 void VarArgsLoweringHelper::createVarArgAreaAndStoreRegisters(
     SDValue &Chain, unsigned StackSize) {
diff --git a/lib/Transforms/Utils/AssumeBundleBuilder.cpp b/lib/Transforms/Utils/AssumeBundleBuilder.cpp
index ee5e142ccf4..77d0edea759 100644
--- a/lib/Transforms/Utils/AssumeBundleBuilder.cpp
+++ b/lib/Transforms/Utils/AssumeBundleBuilder.cpp
@@ -447,6 +447,7 @@ PreservedAnalyses AssumeSimplifyPass::run(Function &F,
   return PreservedAnalyses::all();
 }
 
+namespace {
 class AssumeSimplifyPassLegacyPass : public FunctionPass {
 public:
   static char ID;
@@ -469,6 +470,7 @@ public:
     AU.setPreservesAll();
   }
 };
+} // namespace
 
 char AssumeSimplifyPassLegacyPass::ID = 0;