mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-22 18:54:02 +01:00
[NFC][ARM] Add tests
This commit is contained in:
Sam Parker
parent
68730495b8
commit
48cb6ea724
@ -0,0 +1,456 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s
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--- |
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define dso_local arm_aapcs_vfpcc void @multi_cond_iter_count(i32* nocapture %0, i32* nocapture readonly %1, i32 %2, i32 %3) local_unnamed_addr #0 {
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%5 = icmp eq i32 %3, 2
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%6 = select i1 %5, i32 2, i32 4
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%7 = icmp eq i32 %3, 4
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%8 = select i1 %7, i32 1, i32 %6
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%9 = shl i32 %2, %8
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%10 = icmp eq i32 %9, 0
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br i1 %10, label %64, label %11
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11: ; preds = %4
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%12 = getelementptr i32, i32* %0, i32 %9
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%13 = getelementptr i32, i32* %1, i32 %9
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%14 = icmp ugt i32* %13, %0
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%15 = icmp ugt i32* %12, %1
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%16 = and i1 %14, %15
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%17 = add i32 %9, 3
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%18 = lshr i32 %17, 2
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%19 = shl nuw i32 %18, 2
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%20 = add i32 %19, -4
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%21 = lshr i32 %20, 2
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%22 = add nuw nsw i32 %21, 1
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br i1 %16, label %23, label %32
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23: ; preds = %11
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%24 = add i32 %9, -1
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%25 = and i32 %9, 2
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%26 = icmp ult i32 %24, 3
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%27 = add i32 %9, -4
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%28 = sub i32 %27, %25
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%29 = lshr i32 %28, 2
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%30 = add nuw nsw i32 %29, 1
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br i1 %26, label %49, label %31
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31: ; preds = %23
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call void @llvm.set.loop.iterations.i32(i32 %30)
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br label %65
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32: ; preds = %11
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call void @llvm.set.loop.iterations.i32(i32 %22)
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br label %33
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33: ; preds = %33, %32
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%34 = phi i32* [ %46, %33 ], [ %0, %32 ]
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%35 = phi i32* [ %45, %33 ], [ %1, %32 ]
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%36 = phi i32 [ %22, %32 ], [ %47, %33 ]
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%37 = phi i32 [ %9, %32 ], [ %41, %33 ]
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%38 = bitcast i32* %34 to <4 x i32>*
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%39 = bitcast i32* %35 to <4 x i32>*
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%40 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %37)
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%41 = sub i32 %37, 4
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%42 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %39, i32 4, <4 x i1> %40, <4 x i32> undef)
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%43 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %38, i32 4, <4 x i1> %40, <4 x i32> undef)
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%44 = mul nsw <4 x i32> %43, %42
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call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %44, <4 x i32>* %38, i32 4, <4 x i1> %40)
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%45 = getelementptr i32, i32* %35, i32 4
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%46 = getelementptr i32, i32* %34, i32 4
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%47 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %36, i32 1)
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%48 = icmp ne i32 %47, 0
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br i1 %48, label %33, label %64
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49: ; preds = %65, %23
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%50 = phi i32 [ 0, %23 ], [ %107, %65 ]
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%51 = icmp eq i32 %25, 0
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br i1 %51, label %64, label %52
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52: ; preds = %49
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%53 = getelementptr inbounds i32, i32* %1, i32 %50
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%54 = load i32, i32* %53, align 4
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%55 = getelementptr inbounds i32, i32* %0, i32 %50
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%56 = load i32, i32* %55, align 4
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%57 = mul nsw i32 %56, %54
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store i32 %57, i32* %55, align 4
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%58 = add nuw i32 %50, 1
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%59 = getelementptr inbounds i32, i32* %1, i32 %58
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%60 = load i32, i32* %59, align 4
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%61 = getelementptr inbounds i32, i32* %0, i32 %58
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%62 = load i32, i32* %61, align 4
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%63 = mul nsw i32 %62, %60
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store i32 %63, i32* %61, align 4
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br label %64
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64: ; preds = %33, %52, %49, %4
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ret void
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65: ; preds = %65, %31
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%66 = phi i32 [ %108, %65 ], [ 0, %31 ]
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%67 = phi i32 [ 0, %31 ], [ %107, %65 ]
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%68 = phi i32 [ %30, %31 ], [ %109, %65 ]
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%69 = bitcast i32* %0 to i8*
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%70 = bitcast i32* %1 to i8*
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%71 = getelementptr i8, i8* %70, i32 %66
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%72 = bitcast i8* %71 to i32*
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%73 = bitcast i32* %72 to i32*
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%74 = load i32, i32* %73, align 4
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%75 = getelementptr i8, i8* %69, i32 %66
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%76 = bitcast i8* %75 to i32*
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%77 = bitcast i32* %76 to i32*
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%78 = load i32, i32* %77, align 4
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%79 = mul nsw i32 %78, %74
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store i32 %79, i32* %77, align 4
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%80 = getelementptr i8, i8* %70, i32 %66
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%81 = bitcast i8* %80 to i32*
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%82 = getelementptr i32, i32* %81, i32 1
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%83 = load i32, i32* %82, align 4
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%84 = getelementptr i8, i8* %69, i32 %66
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%85 = bitcast i8* %84 to i32*
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%86 = getelementptr i32, i32* %85, i32 1
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%87 = load i32, i32* %86, align 4
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%88 = mul nsw i32 %87, %83
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store i32 %88, i32* %86, align 4
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%89 = getelementptr i8, i8* %70, i32 %66
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%90 = bitcast i8* %89 to i32*
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%91 = getelementptr i32, i32* %90, i32 2
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%92 = load i32, i32* %91, align 4
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%93 = getelementptr i8, i8* %69, i32 %66
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%94 = bitcast i8* %93 to i32*
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%95 = getelementptr i32, i32* %94, i32 2
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%96 = load i32, i32* %95, align 4
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%97 = mul nsw i32 %96, %92
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store i32 %97, i32* %95, align 4
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%98 = getelementptr i8, i8* %70, i32 %66
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%99 = bitcast i8* %98 to i32*
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%100 = getelementptr i32, i32* %99, i32 3
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%101 = load i32, i32* %100, align 4
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%102 = getelementptr i8, i8* %69, i32 %66
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%103 = bitcast i8* %102 to i32*
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%104 = getelementptr i32, i32* %103, i32 3
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%105 = load i32, i32* %104, align 4
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%106 = mul nsw i32 %105, %101
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store i32 %106, i32* %104, align 4
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%107 = add nuw i32 %67, 4
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%108 = add i32 %66, 16
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%109 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %68, i32 1)
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%110 = icmp ne i32 %109, 0
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br i1 %110, label %65, label %49
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}
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declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>) #1
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declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>) #2
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declare void @llvm.set.loop.iterations.i32(i32) #3
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declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #3
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declare <4 x i1> @llvm.arm.mve.vctp32(i32) #4
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...
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---
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name: multi_cond_iter_count
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alignment: 2
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tracksRegLiveness: true
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registers: []
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liveins:
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- { reg: '$r0', virtual-reg: '' }
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- { reg: '$r1', virtual-reg: '' }
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- { reg: '$r2', virtual-reg: '' }
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- { reg: '$r3', virtual-reg: '' }
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frameInfo:
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stackSize: 32
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offsetAdjustment: -24
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maxAlignment: 4
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fixedStack: []
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stack:
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- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r6', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 4, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 5, name: '', type: spill-slot, offset: -24, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r10', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 6, name: '', type: spill-slot, offset: -28, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r9', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 7, name: '', type: spill-slot, offset: -32, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r8', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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callSites: []
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constants: []
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machineFunctionInfo: {}
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body: |
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; CHECK-LABEL: name: multi_cond_iter_count
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; CHECK: bb.0 (%ir-block.4):
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; CHECK: successors: %bb.4(0x30000000), %bb.1(0x50000000)
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; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8, $r9, $r10
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; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp
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; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20
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; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
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; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
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; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12
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; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -16
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; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -20
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; CHECK: dead $r7 = frame-setup tADDrSPi $sp, 3, 14 /* CC::al */, $noreg
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; CHECK: frame-setup CFI_INSTRUCTION def_cfa $r7, 8
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; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r8, killed $r9, killed $r10
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; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -24
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; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -28
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; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -32
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; CHECK: tCMPi8 renamable $r3, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: $r12 = tMOVr $r3, 14 /* CC::al */, $noreg
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; CHECK: t2IT 1, 8, implicit-def $itstate
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; CHECK: $r12 = t2MOVi 4, 1 /* CC::ne */, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate
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; CHECK: tCMPi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: t2IT 0, 8, implicit-def $itstate
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; CHECK: $r12 = t2MOVi 1, 0 /* CC::eq */, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate
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; CHECK: renamable $r3 = t2LSLrr killed renamable $r2, killed renamable $r12, 14 /* CC::al */, $noreg, def $cpsr
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; CHECK: tBcc %bb.4, 0 /* CC::eq */, killed $cpsr
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; CHECK: bb.1 (%ir-block.11):
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; CHECK: successors: %bb.2(0x55555555), %bb.5(0x2aaaaaab)
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; CHECK: liveins: $r0, $r1, $r3
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; CHECK: renamable $r2 = t2ADDrs renamable $r1, renamable $r3, 18, 14 /* CC::al */, $noreg, $noreg
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; CHECK: tCMPr killed renamable $r2, renamable $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: t2IT 8, 4, implicit-def $itstate
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; CHECK: renamable $r2 = t2ADDrs renamable $r0, renamable $r3, 18, 8 /* CC::hi */, $cpsr, $noreg, implicit $itstate
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; CHECK: tCMPr killed renamable $r2, renamable $r1, 8 /* CC::hi */, killed $cpsr, implicit-def $cpsr, implicit killed $itstate
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; CHECK: tBcc %bb.5, 8 /* CC::hi */, killed $cpsr
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; CHECK: bb.2 (%ir-block.32):
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; CHECK: successors: %bb.3(0x80000000)
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; CHECK: liveins: $r0, $r1, $r3
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; CHECK: $r2 = tMOVr $r0, 14 /* CC::al */, $noreg
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; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3
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; CHECK: bb.3 (%ir-block.33):
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; CHECK: successors: %bb.3(0x7c000000), %bb.4(0x04000000)
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; CHECK: liveins: $lr, $r0, $r1, $r2
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; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg
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; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg
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; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
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; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg
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; CHECK: $r0 = tMOVr $r2, 14 /* CC::al */, $noreg
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; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.3
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; CHECK: bb.4 (%ir-block.64):
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; CHECK: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r8, def $r9, def $r10
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; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc
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; CHECK: bb.5 (%ir-block.23):
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; CHECK: successors: %bb.6(0x40000000), %bb.7(0x40000000)
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; CHECK: liveins: $r0, $r1, $r3
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; CHECK: renamable $r2, dead $cpsr = tSUBi3 renamable $r3, 1, 14 /* CC::al */, $noreg
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; CHECK: renamable $r12 = t2ANDri renamable $r3, 2, 14 /* CC::al */, $noreg, $noreg
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; CHECK: tCMPi8 killed renamable $r2, 3, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: tBcc %bb.7, 2 /* CC::hs */, killed $cpsr
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; CHECK: bb.6:
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; CHECK: successors: %bb.9(0x80000000)
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; CHECK: liveins: $r0, $r1, $r12
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; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
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; CHECK: tB %bb.9, 14 /* CC::al */, $noreg
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; CHECK: bb.7 (%ir-block.31):
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; CHECK: successors: %bb.8(0x80000000)
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; CHECK: liveins: $r0, $r1, $r3, $r12
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; CHECK: renamable $r2 = t2BICri killed renamable $r3, 2, 14 /* CC::al */, $noreg, $noreg
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; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
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; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
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; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg
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; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
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; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
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; CHECK: $lr = t2DLS killed renamable $lr
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; CHECK: bb.8 (%ir-block.65):
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; CHECK: successors: %bb.8(0x7c000000), %bb.9(0x04000000)
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; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r12
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; CHECK: renamable $r4 = tLDRr renamable $r1, $r2, 14 /* CC::al */, $noreg
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; CHECK: renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
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; CHECK: renamable $r5 = tLDRr renamable $r0, $r2, 14 /* CC::al */, $noreg
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; CHECK: renamable $r4, dead $cpsr = nsw tMUL killed renamable $r5, killed renamable $r4, 14 /* CC::al */, $noreg
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; CHECK: renamable $r5, dead $cpsr = tADDrr renamable $r0, renamable $r2, 14 /* CC::al */, $noreg
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; CHECK: $r10, $r8 = t2LDRDi8 $r5, 4, 14 /* CC::al */, $noreg
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; CHECK: renamable $r9 = t2LDRi12 renamable $r5, 12, 14 /* CC::al */, $noreg
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; CHECK: tSTRr killed renamable $r4, renamable $r0, $r2, 14 /* CC::al */, $noreg
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; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r2, 14 /* CC::al */, $noreg
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; CHECK: renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg
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; CHECK: renamable $r6 = tLDRi renamable $r4, 1, 14 /* CC::al */, $noreg
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; CHECK: renamable $r6 = nsw t2MUL killed renamable $r10, killed renamable $r6, 14 /* CC::al */, $noreg
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; CHECK: tSTRi killed renamable $r6, renamable $r5, 1, 14 /* CC::al */, $noreg
|
||||
; CHECK: renamable $r6 = tLDRi renamable $r4, 2, 14 /* CC::al */, $noreg
|
||||
; CHECK: renamable $r6 = nsw t2MUL killed renamable $r8, killed renamable $r6, 14 /* CC::al */, $noreg
|
||||
; CHECK: tSTRi killed renamable $r6, renamable $r5, 2, 14 /* CC::al */, $noreg
|
||||
; CHECK: renamable $r4 = tLDRi killed renamable $r4, 3, 14 /* CC::al */, $noreg
|
||||
; CHECK: renamable $r4 = nsw t2MUL killed renamable $r9, killed renamable $r4, 14 /* CC::al */, $noreg
|
||||
; CHECK: tSTRi killed renamable $r4, killed renamable $r5, 3, 14 /* CC::al */, $noreg
|
||||
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.8
|
||||
; CHECK: bb.9 (%ir-block.49):
|
||||
; CHECK: successors: %bb.4(0x40000000), %bb.10(0x40000000)
|
||||
; CHECK: liveins: $r0, $r1, $r3, $r12
|
||||
; CHECK: t2CMPri killed renamable $r12, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
|
||||
; CHECK: tBcc %bb.4, 0 /* CC::eq */, killed $cpsr
|
||||
; CHECK: bb.10 (%ir-block.52):
|
||||
; CHECK: liveins: $r0, $r1, $r3
|
||||
; CHECK: renamable $r12 = t2LDRs renamable $r1, renamable $r3, 2, 14 /* CC::al */, $noreg
|
||||
; CHECK: renamable $r2 = t2LDRs renamable $r0, renamable $r3, 2, 14 /* CC::al */, $noreg
|
||||
; CHECK: renamable $r12 = nsw t2MUL killed renamable $r2, killed renamable $r12, 14 /* CC::al */, $noreg
|
||||
; CHECK: renamable $r2, dead $cpsr = tADDi3 renamable $r3, 1, 14 /* CC::al */, $noreg
|
||||
; CHECK: renamable $lr = t2LDRs renamable $r0, renamable $r2, 2, 14 /* CC::al */, $noreg
|
||||
; CHECK: t2STRs killed renamable $r12, renamable $r0, killed renamable $r3, 2, 14 /* CC::al */, $noreg
|
||||
; CHECK: renamable $r1 = t2LDRs killed renamable $r1, renamable $r2, 2, 14 /* CC::al */, $noreg
|
||||
; CHECK: renamable $r1 = nsw t2MUL killed renamable $lr, killed renamable $r1, 14 /* CC::al */, $noreg
|
||||
; CHECK: t2STRs killed renamable $r1, killed renamable $r0, killed renamable $r2, 2, 14 /* CC::al */, $noreg
|
||||
; CHECK: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r8, def $r9, def $r10
|
||||
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc
|
||||
bb.0 (%ir-block.4):
|
||||
successors: %bb.4(0x30000000), %bb.1(0x50000000)
|
||||
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8, $r9, $r10
|
||||
|
||||
frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp
|
||||
frame-setup CFI_INSTRUCTION def_cfa_offset 20
|
||||
frame-setup CFI_INSTRUCTION offset $lr, -4
|
||||
frame-setup CFI_INSTRUCTION offset $r7, -8
|
||||
frame-setup CFI_INSTRUCTION offset $r6, -12
|
||||
frame-setup CFI_INSTRUCTION offset $r5, -16
|
||||
frame-setup CFI_INSTRUCTION offset $r4, -20
|
||||
$r7 = frame-setup tADDrSPi $sp, 3, 14, $noreg
|
||||
frame-setup CFI_INSTRUCTION def_cfa $r7, 8
|
||||
$sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r8, killed $r9, killed $r10
|
||||
frame-setup CFI_INSTRUCTION offset $r10, -24
|
||||
frame-setup CFI_INSTRUCTION offset $r9, -28
|
||||
frame-setup CFI_INSTRUCTION offset $r8, -32
|
||||
tCMPi8 renamable $r3, 2, 14, $noreg, implicit-def $cpsr
|
||||
$r12 = tMOVr $r3, 14, $noreg
|
||||
t2IT 1, 8, implicit-def $itstate
|
||||
$r12 = t2MOVi 4, 1, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate
|
||||
tCMPi8 killed renamable $r3, 4, 14, $noreg, implicit-def $cpsr
|
||||
t2IT 0, 8, implicit-def $itstate
|
||||
$r12 = t2MOVi 1, 0, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate
|
||||
renamable $r3 = t2LSLrr killed renamable $r2, killed renamable $r12, 14, $noreg, def $cpsr
|
||||
tBcc %bb.4, 0, killed $cpsr
|
||||
|
||||
bb.1 (%ir-block.11):
|
||||
successors: %bb.2(0x80000000), %bb.5(0x40000000)
|
||||
liveins: $r0, $r1, $r3
|
||||
|
||||
renamable $r2 = t2ADDrs renamable $r1, renamable $r3, 18, 14, $noreg, $noreg
|
||||
tCMPr killed renamable $r2, renamable $r0, 14, $noreg, implicit-def $cpsr
|
||||
t2IT 8, 4, implicit-def $itstate
|
||||
renamable $r2 = t2ADDrs renamable $r0, renamable $r3, 18, 8, $cpsr, $noreg, implicit $itstate
|
||||
tCMPr killed renamable $r2, renamable $r1, 8, killed $cpsr, implicit-def $cpsr, implicit killed $itstate
|
||||
tBcc %bb.5, 8, killed $cpsr
|
||||
|
||||
bb.2 (%ir-block.32):
|
||||
successors: %bb.3(0x80000000)
|
||||
liveins: $r0, $r1, $r3
|
||||
|
||||
renamable $r2, dead $cpsr = tADDi3 renamable $r3, 3, 14, $noreg
|
||||
renamable $r2 = t2BICri killed renamable $r2, 3, 14, $noreg, $noreg
|
||||
renamable $r12 = t2SUBri killed renamable $r2, 4, 14, $noreg, $noreg
|
||||
renamable $r2, dead $cpsr = tMOVi8 1, 14, $noreg
|
||||
renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 19, 14, $noreg, $noreg
|
||||
$r2 = tMOVr $r0, 14, $noreg
|
||||
t2DoLoopStart renamable $lr
|
||||
|
||||
bb.3 (%ir-block.33):
|
||||
successors: %bb.3(0x7c000000), %bb.4(0x04000000)
|
||||
liveins: $lr, $r0, $r1, $r2, $r3
|
||||
|
||||
renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg
|
||||
MVE_VPST 4, implicit $vpr
|
||||
renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr
|
||||
renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr
|
||||
renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg
|
||||
renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
|
||||
MVE_VPST 8, implicit $vpr
|
||||
MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr
|
||||
renamable $lr = t2LoopDec killed renamable $lr, 1
|
||||
$r0 = tMOVr $r2, 14, $noreg
|
||||
t2LoopEnd renamable $lr, %bb.3, implicit-def dead $cpsr
|
||||
tB %bb.4, 14, $noreg
|
||||
|
||||
bb.4 (%ir-block.64):
|
||||
$sp = t2LDMIA_UPD $sp, 14, $noreg, def $r8, def $r9, def $r10
|
||||
tPOP_RET 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc
|
||||
|
||||
bb.5 (%ir-block.23):
|
||||
successors: %bb.6(0x40000000), %bb.7(0x40000000)
|
||||
liveins: $r0, $r1, $r3
|
||||
|
||||
renamable $r2, dead $cpsr = tSUBi3 renamable $r3, 1, 14, $noreg
|
||||
renamable $r12 = t2ANDri renamable $r3, 2, 14, $noreg, $noreg
|
||||
tCMPi8 killed renamable $r2, 3, 14, $noreg, implicit-def $cpsr
|
||||
tBcc %bb.7, 2, killed $cpsr
|
||||
|
||||
bb.6:
|
||||
successors: %bb.9(0x80000000)
|
||||
liveins: $r0, $r1, $r12
|
||||
|
||||
renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg
|
||||
tB %bb.9, 14, $noreg
|
||||
|
||||
bb.7 (%ir-block.31):
|
||||
successors: %bb.8(0x80000000)
|
||||
liveins: $r0, $r1, $r3, $r12
|
||||
|
||||
renamable $r2 = t2BICri killed renamable $r3, 2, 14, $noreg, $noreg
|
||||
renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg
|
||||
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg
|
||||
renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14, $noreg, $noreg
|
||||
renamable $r2, dead $cpsr = tMOVi8 0, 14, $noreg
|
||||
renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg
|
||||
t2DoLoopStart renamable $lr
|
||||
|
||||
bb.8 (%ir-block.65):
|
||||
successors: %bb.8(0x7c000000), %bb.9(0x04000000)
|
||||
liveins: $lr, $r0, $r1, $r2, $r3, $r12
|
||||
|
||||
renamable $r4 = tLDRr renamable $r1, $r2, 14, $noreg
|
||||
renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 4, 14, $noreg
|
||||
renamable $r5 = tLDRr renamable $r0, $r2, 14, $noreg
|
||||
renamable $lr = t2LoopDec killed renamable $lr, 1
|
||||
renamable $r4, dead $cpsr = nsw tMUL killed renamable $r5, killed renamable $r4, 14, $noreg
|
||||
renamable $r5, dead $cpsr = tADDrr renamable $r0, renamable $r2, 14, $noreg
|
||||
$r10, $r8 = t2LDRDi8 $r5, 4, 14, $noreg
|
||||
renamable $r9 = t2LDRi12 renamable $r5, 12, 14, $noreg
|
||||
tSTRr killed renamable $r4, renamable $r0, $r2, 14, $noreg
|
||||
renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r2, 14, $noreg
|
||||
renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 16, 14, $noreg
|
||||
renamable $r6 = tLDRi renamable $r4, 1, 14, $noreg
|
||||
renamable $r6 = nsw t2MUL killed renamable $r10, killed renamable $r6, 14, $noreg
|
||||
tSTRi killed renamable $r6, renamable $r5, 1, 14, $noreg
|
||||
renamable $r6 = tLDRi renamable $r4, 2, 14, $noreg
|
||||
renamable $r6 = nsw t2MUL killed renamable $r8, killed renamable $r6, 14, $noreg
|
||||
tSTRi killed renamable $r6, renamable $r5, 2, 14, $noreg
|
||||
renamable $r4 = tLDRi killed renamable $r4, 3, 14, $noreg
|
||||
renamable $r4 = nsw t2MUL killed renamable $r9, killed renamable $r4, 14, $noreg
|
||||
tSTRi killed renamable $r4, killed renamable $r5, 3, 14, $noreg
|
||||
t2LoopEnd renamable $lr, %bb.8, implicit-def dead $cpsr
|
||||
tB %bb.9, 14, $noreg
|
||||
|
||||
bb.9 (%ir-block.49):
|
||||
successors: %bb.4(0x40000000), %bb.10(0x40000000)
|
||||
liveins: $r0, $r1, $r3, $r12
|
||||
|
||||
t2CMPri killed renamable $r12, 0, 14, $noreg, implicit-def $cpsr
|
||||
tBcc %bb.4, 0, killed $cpsr
|
||||
|
||||
bb.10 (%ir-block.52):
|
||||
liveins: $r0, $r1, $r3
|
||||
|
||||
renamable $r12 = t2LDRs renamable $r1, renamable $r3, 2, 14, $noreg
|
||||
renamable $r2 = t2LDRs renamable $r0, renamable $r3, 2, 14, $noreg
|
||||
renamable $r12 = nsw t2MUL killed renamable $r2, killed renamable $r12, 14, $noreg
|
||||
renamable $r2, dead $cpsr = tADDi3 renamable $r3, 1, 14, $noreg
|
||||
renamable $lr = t2LDRs renamable $r0, renamable $r2, 2, 14, $noreg
|
||||
t2STRs killed renamable $r12, renamable $r0, killed renamable $r3, 2, 14, $noreg
|
||||
renamable $r1 = t2LDRs killed renamable $r1, renamable $r2, 2, 14, $noreg
|
||||
renamable $r1 = nsw t2MUL killed renamable $lr, killed renamable $r1, 14, $noreg
|
||||
t2STRs killed renamable $r1, killed renamable $r0, killed renamable $r2, 2, 14, $noreg
|
||||
$sp = t2LDMIA_UPD $sp, 14, $noreg, def $r8, def $r9, def $r10
|
||||
tPOP_RET 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc
|
||||
|
||||
...
|
||||
160
test/CodeGen/Thumb2/LowOverheadLoops/multi-cond-iter-count.mir
Normal file
160
test/CodeGen/Thumb2/LowOverheadLoops/multi-cond-iter-count.mir
Normal file
@ -0,0 +1,160 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s
|
||||
|
||||
--- |
|
||||
define dso_local arm_aapcs_vfpcc void @multi_cond_iter_count(i32* noalias nocapture %0, i32* nocapture readonly %1, i32 %2, i32 %3) {
|
||||
%5 = icmp eq i32 %3, 2
|
||||
%6 = select i1 %5, i32 2, i32 4
|
||||
%7 = icmp eq i32 %3, 4
|
||||
%8 = select i1 %7, i32 1, i32 %6
|
||||
%9 = shl i32 %2, %8
|
||||
%10 = icmp eq i32 %9, 0
|
||||
%11 = add i32 %9, 3
|
||||
%12 = lshr i32 %11, 2
|
||||
%13 = shl nuw i32 %12, 2
|
||||
%14 = add i32 %13, -4
|
||||
%15 = lshr i32 %14, 2
|
||||
%16 = add nuw nsw i32 %15, 1
|
||||
br i1 %10, label %34, label %17
|
||||
|
||||
17: ; preds = %4
|
||||
call void @llvm.set.loop.iterations.i32(i32 %16)
|
||||
br label %18
|
||||
|
||||
18: ; preds = %18, %17
|
||||
%19 = phi i32* [ %31, %18 ], [ %0, %17 ]
|
||||
%20 = phi i32* [ %30, %18 ], [ %1, %17 ]
|
||||
%21 = phi i32 [ %16, %17 ], [ %32, %18 ]
|
||||
%22 = phi i32 [ %9, %17 ], [ %26, %18 ]
|
||||
%23 = bitcast i32* %19 to <4 x i32>*
|
||||
%24 = bitcast i32* %20 to <4 x i32>*
|
||||
%25 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %22)
|
||||
%26 = sub i32 %22, 4
|
||||
%27 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %24, i32 4, <4 x i1> %25, <4 x i32> undef)
|
||||
%28 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %23, i32 4, <4 x i1> %25, <4 x i32> undef)
|
||||
%29 = mul nsw <4 x i32> %28, %27
|
||||
call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %29, <4 x i32>* %23, i32 4, <4 x i1> %25)
|
||||
%30 = getelementptr i32, i32* %20, i32 4
|
||||
%31 = getelementptr i32, i32* %19, i32 4
|
||||
%32 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %21, i32 1)
|
||||
%33 = icmp ne i32 %32, 0
|
||||
br i1 %33, label %18, label %34
|
||||
|
||||
34: ; preds = %18, %4
|
||||
ret void
|
||||
}
|
||||
declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>)
|
||||
declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>)
|
||||
declare void @llvm.set.loop.iterations.i32(i32)
|
||||
declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
|
||||
declare <4 x i1> @llvm.arm.mve.vctp32(i32)
|
||||
|
||||
...
|
||||
---
|
||||
name: multi_cond_iter_count
|
||||
alignment: 2
|
||||
tracksRegLiveness: true
|
||||
registers: []
|
||||
liveins:
|
||||
- { reg: '$r0', virtual-reg: '' }
|
||||
- { reg: '$r1', virtual-reg: '' }
|
||||
- { reg: '$r2', virtual-reg: '' }
|
||||
- { reg: '$r3', virtual-reg: '' }
|
||||
frameInfo:
|
||||
stackSize: 8
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 4
|
||||
fixedStack: []
|
||||
stack:
|
||||
- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
|
||||
stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
|
||||
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
|
||||
- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
|
||||
stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
|
||||
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
|
||||
callSites: []
|
||||
constants: []
|
||||
machineFunctionInfo: {}
|
||||
body: |
|
||||
; CHECK-LABEL: name: multi_cond_iter_count
|
||||
; CHECK: bb.0 (%ir-block.4):
|
||||
; CHECK: successors: %bb.1(0x80000000)
|
||||
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3
|
||||
; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
|
||||
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
|
||||
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
|
||||
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
|
||||
; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
|
||||
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7
|
||||
; CHECK: tCMPi8 renamable $r3, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr
|
||||
; CHECK: $r12 = tMOVr $r3, 14 /* CC::al */, $noreg
|
||||
; CHECK: t2IT 1, 8, implicit-def $itstate
|
||||
; CHECK: $r12 = t2MOVi 4, 1 /* CC::ne */, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate
|
||||
; CHECK: tCMPi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr
|
||||
; CHECK: t2IT 0, 8, implicit-def $itstate
|
||||
; CHECK: $r12 = t2MOVi 1, 0 /* CC::eq */, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate
|
||||
; CHECK: renamable $r2 = t2LSLrr killed renamable $r2, killed renamable $r12, 14 /* CC::al */, $noreg, def $cpsr
|
||||
; CHECK: t2IT 0, 8, implicit-def $itstate
|
||||
; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
|
||||
; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg
|
||||
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2
|
||||
; CHECK: bb.1 (%ir-block.18):
|
||||
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
|
||||
; CHECK: liveins: $lr, $r0, $r1, $r3
|
||||
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg
|
||||
; CHECK: renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 0, $noreg
|
||||
; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
|
||||
; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg
|
||||
; CHECK: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg
|
||||
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
|
||||
; CHECK: bb.2 (%ir-block.34):
|
||||
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
|
||||
bb.0 (%ir-block.4):
|
||||
successors: %bb.1(0x80000000)
|
||||
liveins: $r0, $r1, $r2, $r3, $lr
|
||||
|
||||
frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp
|
||||
frame-setup CFI_INSTRUCTION def_cfa_offset 8
|
||||
frame-setup CFI_INSTRUCTION offset $lr, -4
|
||||
frame-setup CFI_INSTRUCTION offset $r7, -8
|
||||
$r7 = frame-setup tMOVr $sp, 14, $noreg
|
||||
frame-setup CFI_INSTRUCTION def_cfa_register $r7
|
||||
tCMPi8 renamable $r3, 2, 14, $noreg, implicit-def $cpsr
|
||||
$r12 = tMOVr $r3, 14, $noreg
|
||||
t2IT 1, 8, implicit-def $itstate
|
||||
$r12 = t2MOVi 4, 1, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate
|
||||
tCMPi8 killed renamable $r3, 4, 14, $noreg, implicit-def $cpsr
|
||||
t2IT 0, 8, implicit-def $itstate
|
||||
$r12 = t2MOVi 1, 0, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate
|
||||
renamable $r2 = t2LSLrr killed renamable $r2, killed renamable $r12, 14, $noreg, def $cpsr
|
||||
t2IT 0, 8, implicit-def $itstate
|
||||
tPOP_RET 0, killed $cpsr, def $r7, def $pc, implicit killed $itstate
|
||||
renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg
|
||||
renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg
|
||||
renamable $r12 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg
|
||||
renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg
|
||||
renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg
|
||||
$r3 = tMOVr $r0, 14, $noreg
|
||||
t2DoLoopStart renamable $lr
|
||||
|
||||
bb.1 (%ir-block.18):
|
||||
successors: %bb.1(0x7c000000), %bb.2(0x04000000)
|
||||
liveins: $lr, $r0, $r1, $r2, $r3
|
||||
|
||||
renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg
|
||||
MVE_VPST 4, implicit $vpr
|
||||
renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr
|
||||
renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr
|
||||
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg
|
||||
renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
|
||||
MVE_VPST 8, implicit $vpr
|
||||
MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr
|
||||
renamable $lr = t2LoopDec killed renamable $lr, 1
|
||||
$r0 = tMOVr $r3, 14, $noreg
|
||||
t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr
|
||||
tB %bb.2, 14, $noreg
|
||||
|
||||
bb.2 (%ir-block.34):
|
||||
tPOP_RET 14, $noreg, def $r7, def $pc
|
||||
|
||||
...
|
||||
Loading…
Reference in New Issue
Block a user