RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-21 18:22:53 +01:00
Code Issues Projects Releases Wiki Activity

[MachineVerifier] Make INSERT_SUBREG diagnostic respect operand 2 subregs

Browse Source 
This came out of post-commit review: https://reviews.llvm.org/D105953#inline-1012919

Thanks uabelho!
This commit is contained in:
Jon Roelofs 2021-07-21 08:23:17 -07:00
parent 2b759c7f74
commit 48d5dbf972
2 changed files with 11 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
lib/CodeGen/MachineVerifier.cpp
View File

@ -1783,8 +1783,11 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
// TODO: verify we have properly encoded deopt arguments
} break;
case TargetOpcode::INSERT_SUBREG: {
unsigned InsertedSize =
TRI->getRegSizeInBits(MI->getOperand(2).getReg(), *MRI);
unsigned InsertedSize;
if (unsigned SubIdx = MI->getOperand(2).getSubReg())
InsertedSize = TRI->getSubRegIdxSize(SubIdx);
else
InsertedSize = TRI->getRegSizeInBits(MI->getOperand(2).getReg(), *MRI);
unsigned SubRegSize = TRI->getSubRegIdxSize(MI->getOperand(3).getImm());
if (SubRegSize < InsertedSize) {
report("INSERT_SUBREG expected inserted value to have equal or lesser "

7
test/MachineVerifier/test_insert_subreg.mir
View File

@ -10,7 +10,7 @@ tracksRegLiveness: true
liveins:
body: |
bb.0:
liveins: $s0, $h1
liveins: $s0, $h1, $q2
%0:fpr32 = COPY $s0
@ -28,4 +28,9 @@ body: |
%7:fpr128 = IMPLICIT_DEF
%8:fpr128 = INSERT_SUBREG %7:fpr128, %0:fpr32, %subreg.ssub
; CHECK-NOT: *** Bad machine code:
%9:fpr128 = COPY $q2
%10:fpr128 = IMPLICIT_DEF
%11:fpr128 = INSERT_SUBREG %10:fpr128, %9.ssub, %subreg.ssub
...