diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index c64aceceb65..ea605e1eb2e 100644 --- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -3276,8 +3276,22 @@ SDValue PPCDAGToDAGISel::get64BitZExtCompare(SDValue LHS, SDValue RHS, ShiftR, ShiftL, SubtractCarry), 0); } case ISD::SETGT: { + // {subc.reg, subc.CA} = (subcarry %b, %a) + // (zext (setcc %a, %b, setgt)) -> + // (xor (adde (lshr %a, 63), (ashr %b, 63), subc.CA), 1) + // (zext (setcc %a, 0, setgt)) -> (lshr (nor (add %a, -1), %a), 63) if (IsRHSNegOne) return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GEZExt); + if (IsRHSZero) { + SDValue Addi = + SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, LHS, + getI64Imm(~0ULL, dl)), 0); + SDValue Nor = + SDValue(CurDAG->getMachineNode(PPC::NOR8, dl, MVT::i64, Addi, LHS), 0); + return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Nor, + getI64Imm(1, dl), + getI64Imm(63, dl)), 0); + } std::swap(LHS, RHS); ConstantSDNode *RHSConst = dyn_cast(RHS); IsRHSZero = RHSConst && RHSConst->isNullValue(); @@ -3285,9 +3299,31 @@ SDValue PPCDAGToDAGISel::get64BitZExtCompare(SDValue LHS, SDValue RHS, LLVM_FALLTHROUGH; } case ISD::SETLT: { + // {subc.reg, subc.CA} = (subcarry %a, %b) + // (zext (setcc %a, %b, setlt)) -> + // (xor (adde (lshr %b, 63), (ashr %a, 63), subc.CA), 1) + // (zext (setcc %a, 0, setlt)) -> (lshr %a, 63) if (IsRHSOne) return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LEZExt); - return SDValue(); + if (IsRHSZero) + return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, LHS, + getI64Imm(1, dl), + getI64Imm(63, dl)), 0); + SDValue SRADINode = + SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, + LHS, getI64Imm(63, dl)), 0); + SDValue SRDINode = + SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, + RHS, getI64Imm(1, dl), + getI64Imm(63, dl)), 0); + SDValue SUBFC8Carry = + SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue, + RHS, LHS), 1); + SDValue ADDE8Node = + SDValue(CurDAG->getMachineNode(PPC::ADDE8, dl, MVT::i64, MVT::Glue, + SRDINode, SRADINode, SUBFC8Carry), 0); + return SDValue(CurDAG->getMachineNode(PPC::XORI8, dl, MVT::i64, + ADDE8Node, getI64Imm(1, dl)), 0); } } } @@ -3362,8 +3398,21 @@ SDValue PPCDAGToDAGISel::get64BitSExtCompare(SDValue LHS, SDValue RHS, return SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64, Adde), 0); } case ISD::SETGT: { + // {subc.reg, subc.CA} = (subcarry %b, %a) + // (zext (setcc %a, %b, setgt)) -> + // -(xor (adde (lshr %a, 63), (ashr %b, 63), subc.CA), 1) + // (zext (setcc %a, 0, setgt)) -> (ashr (nor (add %a, -1), %a), 63) if (IsRHSNegOne) return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GESExt); + if (IsRHSZero) { + SDValue Add = + SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, LHS, + getI64Imm(-1, dl)), 0); + SDValue Nor = + SDValue(CurDAG->getMachineNode(PPC::NOR8, dl, MVT::i64, Add, LHS), 0); + return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, Nor, + getI64Imm(63, dl)), 0); + } std::swap(LHS, RHS); ConstantSDNode *RHSConst = dyn_cast(RHS); IsRHSZero = RHSConst && RHSConst->isNullValue(); @@ -3371,9 +3420,34 @@ SDValue PPCDAGToDAGISel::get64BitSExtCompare(SDValue LHS, SDValue RHS, LLVM_FALLTHROUGH; } case ISD::SETLT: { + // {subc.reg, subc.CA} = (subcarry %a, %b) + // (zext (setcc %a, %b, setlt)) -> + // -(xor (adde (lshr %b, 63), (ashr %a, 63), subc.CA), 1) + // (zext (setcc %a, 0, setlt)) -> (ashr %a, 63) if (IsRHSOne) return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LESExt); - return SDValue(); + if (IsRHSZero) { + return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, LHS, + getI64Imm(63, dl)), 0); + } + SDValue SRADINode = + SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, + LHS, getI64Imm(63, dl)), 0); + SDValue SRDINode = + SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, + RHS, getI64Imm(1, dl), + getI64Imm(63, dl)), 0); + SDValue SUBFC8Carry = + SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue, + RHS, LHS), 1); + SDValue ADDE8Node = + SDValue(CurDAG->getMachineNode(PPC::ADDE8, dl, MVT::i64, + SRDINode, SRADINode, SUBFC8Carry), 0); + SDValue XORI8Node = + SDValue(CurDAG->getMachineNode(PPC::XORI8, dl, MVT::i64, + ADDE8Node, getI64Imm(1, dl)), 0); + return SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64, + XORI8Node), 0); } } } diff --git a/test/CodeGen/PowerPC/optcmp.ll b/test/CodeGen/PowerPC/optcmp.ll index a1921452d62..cfd138caf5a 100644 --- a/test/CodeGen/PowerPC/optcmp.ll +++ b/test/CodeGen/PowerPC/optcmp.ll @@ -127,7 +127,7 @@ entry: ret i64 %conv1 ; CHECK: @foo2l -; CHECK: sld. 4, 3, 4 +; CHECK: sld 4, 3, 4 ; CHECK: std 4, 0(5) } diff --git a/test/CodeGen/PowerPC/testComparesigtsll.ll b/test/CodeGen/PowerPC/testComparesigtsll.ll new file mode 100644 index 00000000000..ea50b492d60 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesigtsll.ll @@ -0,0 +1,134 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i64 0, align 8 + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igtsll(i64 %a, i64 %b) { +; CHECK-LABEL: test_igtsll: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r4, 63 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r3, 1, 63 +; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r3, r4 +; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK-NEXT: xori r3, [[REG4]], 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igtsll_sext(i64 %a, i64 %b) { +; CHECK-LABEL: test_igtsll_sext: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r4, 63 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r3, 1, 63 +; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r3, r4 +; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK-NEXT: xori [[REG5:r[0-9]+]], [[REG4]], 1 +; CHECK-NEXT: neg r3, [[REG5]] +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +; FIXME +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igtsll_z(i64 %a) { +; CHECK-LABEL: test_igtsll_z: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addi r4, r3, -1 +; CHECK-NEXT: nor r3, r4, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, 0 + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igtsll_sext_z(i64 %a) { +; CHECK-LABEL: test_igtsll_sext_z: +; CHECK: addi [[REG1:r[0-9]+]], r3, -1 +; CHECK-NEXT: nor [[REG2:r[0-9]+]], [[REG1]], r3 +; CHECK-NEXT: sradi r3, [[REG2]], 63 +entry: + %cmp = icmp sgt i64 %a, 0 + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +; Function Attrs: norecurse nounwind +define void @test_igtsll_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_igtsll_store: +; CHECK: # BB#0: # %entry +; CHECK: sradi [[REG1:r[0-9]+]], r4, 63 +; CHECK: rldicl [[REG2:r[0-9]+]], r3, 1, 63 +; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4 +; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1 +; CHECK-NOT: neg +entry: + %cmp = icmp sgt i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_igtsll_sext_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_igtsll_sext_store: +; CHECK: # BB#0: # %entry +; CHECK: sradi [[REG1:r[0-9]+]], r4, 63 +; CHECK: rldicl [[REG2:r[0-9]+]], r3, 1, 63 +; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4 +; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1 +; CHECK: neg {{r[0-9]+}}, [[REG5]] +entry: + %cmp = icmp sgt i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; FIXME +; Function Attrs: norecurse nounwind +define void @test_igtsll_z_store(i64 %a) { +; CHECK-LABEL: test_igtsll_z_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: addi r5, r3, -1 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: nor r3, r5, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_igtsll_sext_z_store(i64 %a) { +; CHECK-LABEL: test_igtsll_sext_z_store: +; CHECK: addi [[REG1:r[0-9]+]], r3, -1 +; CHECK: nor [[REG2:r[0-9]+]], [[REG1]], r3 +; CHECK: sradi [[REG3:r[0-9]+]], [[REG2]], 63 +entry: + %cmp = icmp sgt i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesiltsll.ll b/test/CodeGen/PowerPC/testComparesiltsll.ll new file mode 100644 index 00000000000..70de905ed20 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesiltsll.ll @@ -0,0 +1,99 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py + +@glob = common local_unnamed_addr global i64 0, align 8 + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_iltsll(i64 %a, i64 %b) { +; CHECK-LABEL: test_iltsll: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r3, 63 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r4, 1, 63 +; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r4, r3 +; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK-NEXT: xori r3, [[REG4]], 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i64 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_iltsll_sext(i64 %a, i64 %b) { +; CHECK-LABEL: test_iltsll_sext: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r3, 63 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r4, 1, 63 +; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r4, r3 +; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK-NEXT: xori [[REG5:r[0-9]+]], [[REG4]], 1 +; CHECK-NEXT: neg r3, [[REG5]] +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i64 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_iltsll_sext_z(i64 %a) { +; CHECK-LABEL: test_iltsll_sext_z: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i64 %a, 0 + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +; Function Attrs: norecurse nounwind +define void @test_iltsll_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_iltsll_store: +; CHECK: # BB#0: # %entry +; CHECK: sradi [[REG1:r[0-9]+]], r3, 63 +; CHECK: rldicl [[REG2:r[0-9]+]], r4, 1, 63 +; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3 +; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1 +; CHECK-NOT: neg {{r[0-9]+}}, [[REG5]] +entry: + %cmp = icmp slt i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_iltsll_sext_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_iltsll_sext_store: +; CHECK: # BB#0: # %entry +; CHECK: sradi [[REG1:r[0-9]+]], r3, 63 +; CHECK: rldicl [[REG2:r[0-9]+]], r4, 1, 63 +; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3 +; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1 +; CHECK: neg {{r[0-9]+}}, [[REG5]] +entry: + %cmp = icmp slt i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_iltsll_sext_z_store(i64 %a) { +; CHECK-LABEL: test_iltsll_sext_z_store: +; CHECK: sradi r3, r3, 63 +entry: + %cmp = icmp slt i64 %a, 0 + %conv2 = sext i1 %cmp to i64 + store i64 %conv2, i64* @glob, align 8 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesllgtsll.ll b/test/CodeGen/PowerPC/testComparesllgtsll.ll new file mode 100644 index 00000000000..b20f7e099d9 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesllgtsll.ll @@ -0,0 +1,134 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i64 0, align 8 + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgtsll(i64 %a, i64 %b) { +; CHECK-LABEL: test_llgtsll: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r4, 63 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r3, 1, 63 +; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r3, r4 +; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK-NEXT: xori r3, [[REG4]], 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, %b + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgtsll_sext(i64 %a, i64 %b) { +; CHECK-LABEL: test_llgtsll_sext: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r4, 63 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r3, 1, 63 +; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r3, r4 +; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK-NEXT: xori [[REG5:r[0-9]+]], [[REG4]], 1 +; CHECK-NEXT: neg r3, [[REG5]] +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, %b + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +} + +; FIXME +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgtsll_z(i64 %a) { +; CHECK-LABEL: test_llgtsll_z: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addi r4, r3, -1 +; CHECK-NEXT: nor r3, r4, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgtsll_sext_z(i64 %a) { +; CHECK-LABEL: test_llgtsll_sext_z: +; CHECK: addi [[REG1:r[0-9]+]], r3, -1 +; CHECK-NEXT: nor [[REG2:r[0-9]+]], [[REG1]], r3 +; CHECK-NEXT: sradi r3, [[REG2]], 63 +entry: + %cmp = icmp sgt i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +} + +; Function Attrs: norecurse nounwind +define void @test_llgtsll_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_llgtsll_store: +; CHECK: # BB#0: # %entry +; CHECK: sradi [[REG1:r[0-9]+]], r4, 63 +; CHECK: rldicl [[REG2:r[0-9]+]], r3, 1, 63 +; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4 +; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1 +; CHECK-NOT: neg +entry: + %cmp = icmp sgt i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_llgtsll_sext_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_llgtsll_sext_store: +; CHECK: # BB#0: # %entry +; CHECK: sradi [[REG1:r[0-9]+]], r4, 63 +; CHECK: rldicl [[REG2:r[0-9]+]], r3, 1, 63 +; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4 +; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1 +; CHECK: neg {{r[0-9]+}}, [[REG5]] +entry: + %cmp = icmp sgt i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; FIXME +; Function Attrs: norecurse nounwind +define void @test_llgtsll_z_store(i64 %a) { +; CHECK-LABEL: test_llgtsll_z_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: addi r5, r3, -1 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: nor r3, r5, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_llgtsll_sext_z_store(i64 %a) { +; CHECK-LABEL: test_llgtsll_sext_z_store: +; CHECK: addi [[REG1:r[0-9]+]], r3, -1 +; CHECK: nor [[REG2:r[0-9]+]], [[REG1]], r3 +; CHECK: sradi [[REG3:r[0-9]+]], [[REG2]], 63 +entry: + %cmp = icmp sgt i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesllltsll.ll b/test/CodeGen/PowerPC/testComparesllltsll.ll new file mode 100644 index 00000000000..657b6c4f47b --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesllltsll.ll @@ -0,0 +1,99 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py + +@glob = common local_unnamed_addr global i64 0, align 8 + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llltsll(i64 %a, i64 %b) { +; CHECK-LABEL: test_llltsll: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r3, 63 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r4, 1, 63 +; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r4, r3 +; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK-NEXT: xori r3, [[REG4]], 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i64 %a, %b + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llltsll_sext(i64 %a, i64 %b) { +; CHECK-LABEL: test_llltsll_sext: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r3, 63 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r4, 1, 63 +; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r4, r3 +; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK-NEXT: xori [[REG5:r[0-9]+]], [[REG4]], 1 +; CHECK-NEXT: neg r3, [[REG5]] +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i64 %a, %b + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llltsll_sext_z(i64 %a) { +; CHECK-LABEL: test_llltsll_sext_z: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i64 %a, 0 + %sub = sext i1 %cmp to i64 + ret i64 %sub +} + +; Function Attrs: norecurse nounwind +define void @test_llltsll_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_llltsll_store: +; CHECK: # BB#0: # %entry +; CHECK: sradi [[REG1:r[0-9]+]], r3, 63 +; CHECK: rldicl [[REG2:r[0-9]+]], r4, 1, 63 +; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3 +; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1 +; CHECK-NOT: neg +entry: + %cmp = icmp slt i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_llltsll_sext_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_llltsll_sext_store: +; CHECK: # BB#0: # %entry +; CHECK: sradi [[REG1:r[0-9]+]], r3, 63 +; CHECK: rldicl [[REG2:r[0-9]+]], r4, 1, 63 +; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3 +; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1 +; CHECK: neg {{r[0-9]+}}, [[REG5]] +entry: + %cmp = icmp slt i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_llltsll_sext_z_store(i64 %a) { +; CHECK-LABEL: test_llltsll_sext_z_store: +; CHECK: sradi r3, r3, 63 +entry: + %cmp = icmp slt i64 %a, 0 + %sub = sext i1 %cmp to i64 + store i64 %sub, i64* @glob, align 8 + ret void +}