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[RISCV] Add support for VECTOR_REVERSE for scalable vector types.
I've left mask registers to a future patch as we'll need to convert them to full vectors, shuffle, and then truncate. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D97609
This commit is contained in:
Craig Topper
parent
f9107e0902
commit
48f016a681
@ -472,6 +472,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
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setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
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setOperationAction(ISD::VECTOR_REVERSE, VT, Custom);
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}
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// Expand various CCs to best match the RVV ISA, which natively supports UNE
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@ -509,6 +511,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
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setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
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setOperationAction(ISD::VECTOR_REVERSE, VT, Custom);
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};
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if (Subtarget.hasStdExtZfh())
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@ -1528,6 +1532,8 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
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return lowerINSERT_SUBVECTOR(Op, DAG);
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case ISD::EXTRACT_SUBVECTOR:
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return lowerEXTRACT_SUBVECTOR(Op, DAG);
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case ISD::VECTOR_REVERSE:
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return lowerVECTOR_REVERSE(Op, DAG);
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case ISD::BUILD_VECTOR:
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return lowerBUILD_VECTOR(Op, DAG, Subtarget);
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case ISD::VECTOR_SHUFFLE:
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@ -2793,6 +2799,84 @@ SDValue RISCVTargetLowering::lowerEXTRACT_SUBVECTOR(SDValue Op,
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return DAG.getBitcast(Op.getSimpleValueType(), Slidedown);
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}
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// Implement vector_reverse using vrgather.vv with indices determined by
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// subtracting the id of each element from (VLMAX-1). This will convert
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// the indices like so:
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// (0, 1,..., VLMAX-2, VLMAX-1) -> (VLMAX-1, VLMAX-2,..., 1, 0).
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// TODO: This code assumes VLMAX <= 65536 for LMUL=8 SEW=16.
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SDValue RISCVTargetLowering::lowerVECTOR_REVERSE(SDValue Op,
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SelectionDAG &DAG) const {
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SDLoc DL(Op);
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MVT VecVT = Op.getSimpleValueType();
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unsigned EltSize = VecVT.getScalarSizeInBits();
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unsigned MinSize = VecVT.getSizeInBits().getKnownMinValue();
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unsigned MaxVLMAX = 0;
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unsigned VectorBitsMax = Subtarget.getMaxRVVVectorSizeInBits();
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if (VectorBitsMax != 0)
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MaxVLMAX = ((VectorBitsMax / EltSize) * MinSize) / RISCV::RVVBitsPerBlock;
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unsigned GatherOpc = RISCVISD::VRGATHER_VV_VL;
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MVT IntVT = VecVT.changeVectorElementTypeToInteger();
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// If this is SEW=8 and VLMAX is unknown or more than 256, we need
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// to use vrgatherei16.vv.
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// TODO: It's also possible to use vrgatherei16.vv for other types to
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// decrease register width for the index calculation.
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if ((MaxVLMAX == 0 || MaxVLMAX > 256) && EltSize == 8) {
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// If this is LMUL=8, we have to split before can use vrgatherei16.vv.
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// Reverse each half, then reassemble them in reverse order.
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// NOTE: It's also possible that after splitting that VLMAX no longer
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// requires vrgatherei16.vv.
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if (MinSize == (8 * RISCV::RVVBitsPerBlock)) {
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SDValue Lo, Hi;
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std::tie(Lo, Hi) = DAG.SplitVectorOperand(Op.getNode(), 0);
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EVT LoVT, HiVT;
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std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VecVT);
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Lo = DAG.getNode(ISD::VECTOR_REVERSE, DL, LoVT, Lo);
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Hi = DAG.getNode(ISD::VECTOR_REVERSE, DL, HiVT, Hi);
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// Reassemble the low and high pieces reversed.
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// FIXME: This is a CONCAT_VECTORS.
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SDValue Res =
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DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VecVT, DAG.getUNDEF(VecVT), Hi,
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DAG.getIntPtrConstant(0, DL));
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return DAG.getNode(
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ISD::INSERT_SUBVECTOR, DL, VecVT, Res, Lo,
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DAG.getIntPtrConstant(LoVT.getVectorMinNumElements(), DL));
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}
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// Just promote the int type to i16 which will double the LMUL.
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IntVT = MVT::getVectorVT(MVT::i16, VecVT.getVectorElementCount());
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GatherOpc = RISCVISD::VRGATHEREI16_VV_VL;
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}
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MVT XLenVT = Subtarget.getXLenVT();
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SDValue Mask, VL;
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std::tie(Mask, VL) = getDefaultScalableVLOps(VecVT, DL, DAG, Subtarget);
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// Calculate VLMAX-1 for the desired SEW.
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unsigned MinElts = VecVT.getVectorMinNumElements();
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SDValue VLMax = DAG.getNode(ISD::VSCALE, DL, XLenVT,
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DAG.getConstant(MinElts, DL, XLenVT));
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SDValue VLMinus1 =
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DAG.getNode(ISD::SUB, DL, XLenVT, VLMax, DAG.getConstant(1, DL, XLenVT));
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// Splat VLMAX-1 taking care to handle SEW==64 on RV32.
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bool IsRV32E64 =
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!Subtarget.is64Bit() && IntVT.getVectorElementType() == MVT::i64;
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SDValue SplatVL;
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if (!IsRV32E64)
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SplatVL = DAG.getSplatVector(IntVT, DL, VLMinus1);
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else
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SplatVL = DAG.getNode(RISCVISD::SPLAT_VECTOR_I64, DL, IntVT, VLMinus1);
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SDValue VID = DAG.getNode(RISCVISD::VID_VL, DL, IntVT, Mask, VL);
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SDValue Indices =
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DAG.getNode(RISCVISD::SUB_VL, DL, IntVT, SplatVL, VID, Mask, VL);
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return DAG.getNode(GatherOpc, DL, VecVT, Op.getOperand(0), Indices, Mask, VL);
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}
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SDValue
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RISCVTargetLowering::lowerFixedLengthVectorLoadToRVV(SDValue Op,
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SelectionDAG &DAG) const {
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@ -5907,6 +5991,8 @@ const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const {
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NODE_NAME_CASE(VMCLR_VL)
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NODE_NAME_CASE(VMSET_VL)
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NODE_NAME_CASE(VRGATHER_VX_VL)
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NODE_NAME_CASE(VRGATHER_VV_VL)
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NODE_NAME_CASE(VRGATHEREI16_VV_VL)
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NODE_NAME_CASE(VSEXT_VL)
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NODE_NAME_CASE(VZEXT_VL)
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NODE_NAME_CASE(VLE_VL)
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@ -203,8 +203,11 @@ enum NodeType : unsigned {
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VMCLR_VL,
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VMSET_VL,
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// Matches the semantics of vrgather.vx with an extra operand for VL.
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// Matches the semantics of vrgather.vx and vrgather.vv with an extra operand
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// for VL.
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VRGATHER_VX_VL,
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VRGATHER_VV_VL,
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VRGATHEREI16_VV_VL,
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// Vector sign/zero extend with additional mask & VL operands.
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VSEXT_VL,
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@ -446,6 +449,7 @@ private:
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SDValue lowerFPVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerVECTOR_REVERSE(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerABS(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerFixedLengthVectorLoadToRVV(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerFixedLengthVectorStoreToRVV(SDValue Op, SelectionDAG &DAG) const;
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@ -142,6 +142,24 @@ def riscv_vrgather_vx_vl : SDNode<"RISCVISD::VRGATHER_VX_VL",
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SDTCVecEltisVT<3, i1>,
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SDTCisSameNumEltsAs<0, 3>,
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SDTCisVT<4, XLenVT>]>>;
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def riscv_vrgather_vv_vl : SDNode<"RISCVISD::VRGATHER_VV_VL",
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SDTypeProfile<1, 4, [SDTCisVec<0>,
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SDTCisSameAs<0, 1>,
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SDTCisInt<2>,
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SDTCisSameNumEltsAs<0, 2>,
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SDTCisSameSizeAs<0, 2>,
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SDTCVecEltisVT<3, i1>,
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SDTCisSameNumEltsAs<0, 3>,
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SDTCisVT<4, XLenVT>]>>;
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def riscv_vrgatherei16_vv_vl : SDNode<"RISCVISD::VRGATHEREI16_VV_VL",
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SDTypeProfile<1, 4, [SDTCisVec<0>,
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SDTCisSameAs<0, 1>,
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SDTCisInt<2>,
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SDTCVecEltisVT<2, i16>,
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SDTCisSameNumEltsAs<0, 2>,
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SDTCVecEltisVT<3, i1>,
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SDTCisSameNumEltsAs<0, 3>,
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SDTCisVT<4, XLenVT>]>>;
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def riscv_vselect_vl : SDNode<"RISCVISD::VSELECT_VL",
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SDTypeProfile<1, 4, [SDTCisVec<0>,
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@ -995,6 +1013,12 @@ foreach vti = AllIntegerVectors in {
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(!cast<Instruction>("PseudoVMV_S_X_"#vti.LMul.MX)
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vti.RegClass:$merge,
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(vti.Scalar vti.ScalarRegClass:$rs1), GPR:$vl, vti.SEW)>;
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def : Pat<(vti.Vector (riscv_vrgather_vv_vl vti.RegClass:$rs2,
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(vti.Vector vti.RegClass:$rs1),
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(vti.Mask true_mask),
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(XLenVT (VLOp GPR:$vl)))),
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(!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX)
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vti.RegClass:$rs2, vti.RegClass:$rs1, GPR:$vl, vti.SEW)>;
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def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, GPR:$rs1,
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(vti.Mask true_mask),
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(XLenVT (VLOp GPR:$vl)))),
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@ -1005,6 +1029,22 @@ foreach vti = AllIntegerVectors in {
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(XLenVT (VLOp GPR:$vl)))),
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(!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX)
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vti.RegClass:$rs2, uimm5:$imm, GPR:$vl, vti.SEW)>;
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// emul = lmul * 16 / sew
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defvar vlmul = vti.LMul;
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defvar octuple_lmul = octuple_from_str<vlmul.MX>.ret;
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defvar octuple_emul = !srl(!mul(octuple_lmul, 16), shift_amount<vti.SEW>.val);
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if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
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defvar emul_str = octuple_to_str<octuple_emul>.ret;
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defvar ivti = !cast<VTypeInfo>("VI16" # emul_str);
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defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_" # emul_str;
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def : Pat<(vti.Vector (riscv_vrgatherei16_vv_vl vti.RegClass:$rs2,
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(ivti.Vector ivti.RegClass:$rs1),
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(vti.Mask true_mask),
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(XLenVT (VLOp GPR:$vl)))),
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(!cast<Instruction>(inst)
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vti.RegClass:$rs2, ivti.RegClass:$rs1, GPR:$vl, vti.SEW)>;
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}
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}
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} // Predicates = [HasStdExtV]
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@ -1019,6 +1059,13 @@ foreach vti = AllFloatVectors in {
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(!cast<Instruction>("PseudoVFMV_S_"#vti.ScalarSuffix#"_"#vti.LMul.MX)
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vti.RegClass:$merge,
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(vti.Scalar vti.ScalarRegClass:$rs1), GPR:$vl, vti.SEW)>;
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defvar ivti = GetIntVTypeInfo<vti>.Vti;
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def : Pat<(vti.Vector (riscv_vrgather_vv_vl vti.RegClass:$rs2,
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(ivti.Vector vti.RegClass:$rs1),
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(vti.Mask true_mask),
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(XLenVT (VLOp GPR:$vl)))),
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(!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX)
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vti.RegClass:$rs2, vti.RegClass:$rs1, GPR:$vl, vti.SEW)>;
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def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, GPR:$rs1,
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(vti.Mask true_mask),
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(XLenVT (VLOp GPR:$vl)))),
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@ -1029,6 +1076,21 @@ foreach vti = AllFloatVectors in {
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(XLenVT (VLOp GPR:$vl)))),
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(!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX)
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vti.RegClass:$rs2, uimm5:$imm, GPR:$vl, vti.SEW)>;
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defvar vlmul = vti.LMul;
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defvar octuple_lmul = octuple_from_str<vlmul.MX>.ret;
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defvar octuple_emul = !srl(!mul(octuple_lmul, 16), shift_amount<vti.SEW>.val);
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if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
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defvar emul_str = octuple_to_str<octuple_emul>.ret;
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defvar ivti = !cast<VTypeInfo>("VI16" # emul_str);
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defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_" # emul_str;
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def : Pat<(vti.Vector (riscv_vrgatherei16_vv_vl vti.RegClass:$rs2,
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(ivti.Vector ivti.RegClass:$rs1),
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(vti.Mask true_mask),
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(XLenVT (VLOp GPR:$vl)))),
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(!cast<Instruction>(inst)
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vti.RegClass:$rs2, ivti.RegClass:$rs1, GPR:$vl, vti.SEW)>;
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}
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}
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} // Predicates = [HasStdExtV, HasStdExtF]
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1113
test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
Normal file
1113
test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
Normal file
File diff suppressed because it is too large
Load Diff
@ -714,6 +714,15 @@ bool TypeInfer::EnforceSameNumElts(TypeSetByHwMode &V, TypeSetByHwMode &W) {
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return Changed;
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}
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namespace {
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struct TypeSizeComparator {
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bool operator()(const TypeSize &LHS, const TypeSize &RHS) const {
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return std::make_tuple(LHS.isScalable(), LHS.getKnownMinValue()) <
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std::make_tuple(RHS.isScalable(), RHS.getKnownMinValue());
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}
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};
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} // end anonymous namespace
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/// 1. Ensure that for each type T in A, there exists a type U in B,
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/// such that T and U have equal size in bits.
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/// 2. Ensure that for each type U in B, there exists a type T in A
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@ -728,14 +737,16 @@ bool TypeInfer::EnforceSameSize(TypeSetByHwMode &A, TypeSetByHwMode &B) {
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if (B.empty())
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Changed |= EnforceAny(B);
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auto NoSize = [](const SmallSet<TypeSize, 2> &Sizes, MVT T) -> bool {
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typedef SmallSet<TypeSize, 2, TypeSizeComparator> TypeSizeSet;
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auto NoSize = [](const TypeSizeSet &Sizes, MVT T) -> bool {
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return !Sizes.count(T.getSizeInBits());
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};
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for (unsigned M : union_modes(A, B)) {
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TypeSetByHwMode::SetType &AS = A.get(M);
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TypeSetByHwMode::SetType &BS = B.get(M);
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SmallSet<TypeSize, 2> AN, BN;
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TypeSizeSet AN, BN;
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for (MVT T : AS)
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AN.insert(T.getSizeInBits());
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