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include/llvm/CodeGen/MachineInstrBuilder.h: Add addClobber() inline
convenience method. Fix typo in comment. lib/Target/X86/InstSelectSimple.cpp: Explicitly specify some implicit uses. Use MOVZX/MOVSX instead of MOV instructions with sign extend instructions. Take out LEAVE instructions. 32-bit IDIV and DIV use CDQ, not CWQ (CWQ is a typo). Fix typo in comment and remove some FIXME comments. lib/Target/X86/Printer.cpp: Include X86InstrInfo.h and llvm/Function.h. Add some simple code to Printer::runOnFunction to iterate over MachineBasicBlocks and call X86InstrInfo::print(). lib/Target/X86/X86InstrInfo.def: Make some more instructions with implicit defs "Void". Add more sign/zero extending "move" insns (movsx, movzx). lib/Target/X86/X86RegisterInfo.def: Add EFLAGS as a register. llvm-svn: 4707
This commit is contained in:
Brian Gaeke
parent
9da9f0534e
commit
492e05ba01
@ -34,13 +34,22 @@ struct MachineInstrBuilder {
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return *this;
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}
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/// addReg - Add an LLVM value that is to be used as a register...x
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/// addReg - Add an LLVM value that is to be used as a register...
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///
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MachineInstrBuilder &addReg(Value *V, bool isDef = false, bool isDNU = false){
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MI->addRegOperand(V, isDef, isDNU);
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return *this;
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}
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/// addClobber - Assert that this MI is going to clobber a specific
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/// register. Useful for instructions that always clobber certain hard regs.
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/// (Same as addReg(RegNo, true) but shorter and more obvious).
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///
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MachineInstrBuilder &addClobber(int RegNo) {
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MI->addRegOperand(RegNo, true);
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return *this;
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}
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/// addPCDisp - Add an LLVM value to be treated as a PC relative
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/// displacement...
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///
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@ -211,33 +211,30 @@ ISel::visitSetCondInst (SetCondInst & I)
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break;
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}
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// (Non-trapping) compare and pop twice.
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// FIXME: Result of comparison -> condition codes, not a register.
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BuildMI (BB, X86::FUCOMPP, 0);
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// Move fp status word (concodes) to ax.
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BuildMI (BB, X86::FNSTSWr8, 1, X86::AX);
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// Load real concodes from ax.
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// FIXME: Once again, flags are not modeled.
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BuildMI (BB, X86::SAHF, 0);
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BuildMI (BB, X86::SAHF, 1, X86::EFLAGS).addReg(X86::AH);
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}
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else
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{ // integer comparison
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// Emit: cmp <var1>, <var2> (do the comparison). We can
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// compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with
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// 32-bit.
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// FIXME: Result of comparison -> condition codes, not a register.
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switch (comparisonWidth)
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{
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case 1:
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BuildMI (BB, X86::CMPrr8, 2,
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X86::NoReg).addReg (reg1).addReg (reg2);
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X86::EFLAGS).addReg (reg1).addReg (reg2);
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break;
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case 2:
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BuildMI (BB, X86::CMPrr16, 2,
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X86::NoReg).addReg (reg1).addReg (reg2);
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X86::EFLAGS).addReg (reg1).addReg (reg2);
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break;
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case 4:
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BuildMI (BB, X86::CMPrr32, 2,
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X86::NoReg).addReg (reg1).addReg (reg2);
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X86::EFLAGS).addReg (reg1).addReg (reg2);
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break;
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case 8:
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default:
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@ -297,15 +294,11 @@ ISel::visitSetCondInst (SetCondInst & I)
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case 1:
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BuildMI (BB, X86::MOVrr8, 1, resultReg).addReg (X86::AL);
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break;
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// FIXME: What to do about implicit destination registers?
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// E.g., you don't specify it, but CBW is more like AX = CBW(AL).
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case 2:
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BuildMI (BB, X86::CBW, 0, X86::AX);
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BuildMI (BB, X86::MOVrr16, 1, resultReg).addReg (X86::AX);
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BuildMI (BB, X86::MOVZXr16r8, 1, resultReg).addReg (X86::AL);
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break;
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case 4:
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BuildMI (BB, X86::CWDE, 0, X86::EAX);
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BuildMI (BB, X86::MOVrr32, 1, resultReg).addReg (X86::EAX);
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BuildMI (BB, X86::MOVZXr32r8, 1, resultReg).addReg (X86::AL);
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break;
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case 8:
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default:
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@ -331,6 +324,7 @@ ISel::visitReturnInst (ReturnInst & I)
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{
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if (I.getNumOperands () == 1)
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{
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bool unsignedReturnValue = I.getOperand(0)->getType()->isUnsigned();
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unsigned val = getReg (I.getOperand (0));
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unsigned operandSize =
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I.getOperand (0)->getType ()->getPrimitiveSize ();
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@ -358,21 +352,22 @@ ISel::visitReturnInst (ReturnInst & I)
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{
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case 1:
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// ret sbyte, ubyte: Extend value into EAX and return
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// MOV AL, <val>
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// CBW
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BuildMI (BB, X86::MOVrr8, 1, X86::AL).addReg (val);
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BuildMI (BB, X86::CBW, 0);
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if (unsignedReturnValue) {
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BuildMI (BB, X86::MOVZXr32r8, 1, X86::EAX).addReg (val);
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} else {
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BuildMI (BB, X86::MOVSXr32r8, 1, X86::EAX).addReg (val);
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}
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break;
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case 2:
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// ret short, ushort: Extend value into EAX and return
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// MOV AX, <val>
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// CWDE
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BuildMI (BB, X86::MOVrr16, 1, X86::AX).addReg (val);
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BuildMI (BB, X86::CWDE, 0);
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if (unsignedReturnValue) {
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BuildMI (BB, X86::MOVZXr32r16, 1, X86::EAX).addReg (val);
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} else {
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BuildMI (BB, X86::MOVSXr32r16, 1, X86::EAX).addReg (val);
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}
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break;
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case 4:
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// ret int, uint, ptr: Move value into EAX and return
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// MOV EAX, <val>
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BuildMI (BB, X86::MOVrr32, 1, X86::EAX).addReg (val);
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break;
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case 8:
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@ -387,8 +382,7 @@ ISel::visitReturnInst (ReturnInst & I)
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}
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}
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}
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// Emit a 'leave' and a 'ret'
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BuildMI (BB, X86::LEAVE, 0);
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// Emit a 'ret' -- the 'leave' will be added by the reg allocator, I guess?
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BuildMI (BB, X86::RET, 0);
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}
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@ -473,7 +467,7 @@ void ISel::visitDivRem(BinaryOperator &I) {
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static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
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static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
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static const unsigned ExtOpcode[]={ X86::CBW , X86::CWD , X86::CWQ };
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static const unsigned ExtOpcode[]={ X86::CBW , X86::CWD , X86::CDQ };
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static const unsigned ClrOpcode[]={ X86::XORrr8, X86::XORrr16, X86::XORrr32 };
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static const unsigned ExtRegs[] ={ X86::AH , X86::DX , X86::EDX };
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@ -502,7 +496,7 @@ void ISel::visitDivRem(BinaryOperator &I) {
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// Figure out which register we want to pick the result out of...
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unsigned DestReg = (I.getOpcode() == Instruction::Div) ? Reg : ExtReg;
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// Emit the appropriate multiple instruction...
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// Emit the appropriate divide or remainder instruction...
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// FIXME: We need to mark that this modified AH, DX, or EDX also!!
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BuildMI(BB,DivOpcode[isSigned][Class], 2, DestReg).addReg(Reg).addReg(Op1Reg);
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@ -6,7 +6,10 @@
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "X86InstrInfo.h"
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#include "llvm/Pass.h"
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#include "llvm/Function.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include <iostream>
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@ -21,18 +24,41 @@ namespace {
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};
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}
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bool Printer::runOnFunction(Function &F) {
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MachineFunction &MF = MachineFunction::get(&F);
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O << "x86 printing not implemented yet!\n";
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// This should use the X86InstructionInfo::print method to print assembly
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// for each instruction
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/// runOnFunction - This uses the X86InstructionInfo::print method
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/// to print assembly for each instruction.
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bool Printer::runOnFunction (Function & F)
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{
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static unsigned bbnumber = 0;
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MachineFunction & MF = MachineFunction::get (&F);
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const MachineInstrInfo & MII = TM.getInstrInfo ();
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const X86InstrInfo & x86ii = dynamic_cast <const X86InstrInfo &> (MII);
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O << "# x86 printing not implemented yet!\n";
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// Print out labels for the function.
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O << "\t.globl\t" << F.getName () << "\n";
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O << "\t.type\t" << F.getName () << ", @function\n";
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O << F.getName () << ":\n";
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// Print out code for the function.
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for (MachineFunction::const_iterator bb_i = MF.begin (), bb_e = MF.end ();
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bb_i != bb_e; ++bb_i)
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{
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// Print a label for the basic block.
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O << ".BB" << bbnumber++ << ":\n";
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for (MachineBasicBlock::const_iterator i_i = bb_i->begin (), i_e =
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bb_i->end (); i_i != i_e; ++i_i)
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{
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// Print the assembly for the instruction.
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O << "\t";
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x86ii.print (*i_i, O);
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}
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}
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// We didn't modify anything.
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return false;
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}
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/// createX86CodePrinterPass - Print out the specified machine code function to
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/// the specified stream. This function should work regardless of whether or
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/// not the function is in SSA form or not.
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@ -99,14 +99,14 @@ I(SARrr32 , "sarl", 0, 0) // R32 >>= cl D3/7
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I(SARir32 , "sarl", 0, 0) // R32 >>= imm8 C1/7 ib
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// Floating point loads
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I(FLDr4 , "flds", 0, 0) // push float D9/0
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I(FLDr8 , "fldl ", 0, 0) // push double DD/0
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I(FLDr4 , "flds", 0, X86II::Void) // push float D9/0
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I(FLDr8 , "fldl ", 0, X86II::Void) // push double DD/0
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// Floating point compares
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I(FUCOMPP , "fucompp", 0, 0) // compare+pop2x DA E9
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I(FUCOMPP , "fucompp", 0, X86II::Void) // compare+pop2x DA E9
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// Floating point flag ops
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I(FNSTSWr8 , "fnstsw", 0, 0) // AX = fp flags DF E0
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I(FNSTSWr8 , "fnstsw", 0, X86II::Void) // AX = fp flags DF E0
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// Condition code ops, incl. set if equal/not equal/...
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I(SAHF , "sahf", 0, 0) // flags = AH 9E
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@ -126,11 +126,16 @@ I(CMPrr8 , "cmpb", 0, 0) // compare R8,R8 38/r
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I(CMPrr16 , "cmpw", 0, 0) // compare R16,R16 39/r
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I(CMPrr32 , "cmpl", 0, 0) // compare R32,R32 39/r
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// Sign extenders
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I(CBW , "cbw", 0, 0) // AH = signext(AL) 98
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I(CWD , "cwd", 0, 0) // DX = signext(AX) 99
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I(CWQ , "cwq", 0, 0) // EDX= signext(EAX) 99
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I(CWDE , "cwde", 0, 0) // EAX = extend AX 98
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// Sign extenders (first 3 are good for DIV/IDIV; the others are more general)
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I(CBW , "cbw", 0, 0) // AX = signext(AL) 98
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I(CWD , "cwd", 0, 0) // DX:AX = signext(AX) 99
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I(CDQ , "cdq", 0, 0) // EDX:EAX = signext(EAX) 99
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I(MOVSXr16r8 , "movsx", 0, 0) // R32 = signext(R8) 0F BE /r
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I(MOVSXr32r8 , "movsx", 0, 0) // R32 = signext(R8) 0F BE /r
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I(MOVSXr32r16 , "movsx", 0, 0) // R32 = signext(R16) 0F BF /r
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I(MOVZXr16r8 , "movzx", 0, 0) // R32 = zeroext(R8) 0F B6 /r
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I(MOVZXr32r8 , "movzx", 0, 0) // R32 = zeroext(R8) 0F B6 /r
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I(MOVZXr32r16 , "movzx", 0, 0) // R32 = zeroext(R16) 0F B7 /r
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// At this point, I is dead, so undefine the macro
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#undef I
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@ -64,5 +64,10 @@ R(BH, "bh", MRF::INT8, 0)
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// Flags, Segment registers, etc...
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// This is a slimy hack to make it possible to say that flags are clobbered...
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// Ideally we'd model instructions based on which particular flag(s) they
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// could clobber.
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R(EFLAGS, "eflags", MRF::INT8, 0)
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// We are now done with the R macro
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#undef R
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