RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 03:33:20 +01:00
Code Issues Projects Releases Wiki Activity

PSHUFW is in SSE, not SSSE3.

Browse Source 
llvm-svn: 115691
This commit is contained in:
Bill Wendling 2010-10-05 21:58:12 +00:00
parent 7065387c35
commit 4938e4d00a
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
test/CodeGen/X86/mmx-builtins.ll
View File

@ -1028,14 +1028,14 @@ entry:
ret i64 %5 ret i64 %5
} }
declare x86_mmx @llvm.x86.ssse3.pshuf.w(x86_mmx, i8) nounwind readnone declare x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx, i8) nounwind readnone
define i64 @test21(<1 x i64> %a) nounwind readnone optsize ssp { define i64 @test21(<1 x i64> %a) nounwind readnone optsize ssp {
; CHECK: pshufw ; CHECK: pshufw
entry: entry:
%0 = bitcast <1 x i64> %a to <4 x i16> %0 = bitcast <1 x i64> %a to <4 x i16>
%1 = bitcast <4 x i16> %0 to x86_mmx %1 = bitcast <4 x i16> %0 to x86_mmx
%2 = tail call x86_mmx @llvm.x86.ssse3.pshuf.w(x86_mmx %1, i8 3) nounwind readnone %2 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %1, i8 3) nounwind readnone
%3 = bitcast x86_mmx %2 to <4 x i16> %3 = bitcast x86_mmx %2 to <4 x i16>
%4 = bitcast <4 x i16> %3 to <1 x i64> %4 = bitcast <4 x i16> %3 to <1 x i64>
%5 = extractelement <1 x i64> %4, i32 0 %5 = extractelement <1 x i64> %4, i32 0