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https://github.com/RPCS3/llvm-mirror.git
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Add definitions of conditional moves with 64-bit operands. Comment out code for
expanding conditional moves, which is not needed since architectures that lack support for conditional moves have been removed. llvm-svn: 142226
This commit is contained in:
Akira Hatanaka
parent
f61af0e4b0
commit
4939842b5a
@ -3,30 +3,29 @@
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// MipsISelLowering::EmitInstrWithCustomInserter if target does not have
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// conditional move instructions.
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// cond:int, data:int
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class CondMovIntInt<bits<6> funct, string instr_asm> :
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FR<0, funct, (outs CPURegs:$rd), (ins CPURegs:$rs, CPURegs:$rt, CPURegs:$F),
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class CondMovIntInt<RegisterClass CRC, RegisterClass DRC, bits<6> funct,
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string instr_asm> :
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FR<0, funct, (outs DRC:$rd), (ins DRC:$rs, CRC:$rt, DRC:$F),
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!strconcat(instr_asm, "\t$rd, $rs, $rt"), [], NoItinerary> {
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let shamt = 0;
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let usesCustomInserter = 1;
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let Constraints = "$F = $rd";
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}
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// cond:int, data:float
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class CondMovIntFP<RegisterClass RC, bits<5> fmt, bits<6> func,
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string instr_asm> :
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FFR<0x11, func, fmt, (outs RC:$fd), (ins RC:$fs, CPURegs:$rt, RC:$F),
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class CondMovIntFP<RegisterClass CRC, RegisterClass DRC, bits<5> fmt,
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bits<6> func, string instr_asm> :
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FFR<0x11, func, fmt, (outs DRC:$fd), (ins DRC:$fs, CRC:$rt, DRC:$F),
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!strconcat(instr_asm, "\t$fd, $fs, $rt"), []> {
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let usesCustomInserter = 1;
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let Constraints = "$F = $fd";
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}
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// cond:float, data:int
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class CondMovFPInt<SDNode cmov, bits<1> tf, string instr_asm> :
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FCMOV<tf, (outs CPURegs:$rd), (ins CPURegs:$rs, CPURegs:$F),
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class CondMovFPInt<RegisterClass RC, SDNode cmov, bits<1> tf,
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string instr_asm> :
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FCMOV<tf, (outs RC:$rd), (ins RC:$rs, RC:$F),
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!strconcat(instr_asm, "\t$rd, $rs, $$fcc0"),
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[(set CPURegs:$rd, (cmov CPURegs:$rs, CPURegs:$F))]> {
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[(set RC:$rd, (cmov RC:$rs, RC:$F))]> {
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let cc = 0;
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let usesCustomInserter = 1;
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let Uses = [FCR31];
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let Constraints = "$F = $rd";
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}
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@ -38,70 +37,143 @@ class CondMovFPFP<RegisterClass RC, SDNode cmov, bits<5> fmt, bits<1> tf,
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!strconcat(instr_asm, "\t$fd, $fs, $$fcc0"),
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[(set RC:$fd, (cmov RC:$fs, RC:$F))]> {
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let cc = 0;
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let usesCustomInserter = 1;
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let Uses = [FCR31];
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let Constraints = "$F = $fd";
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}
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// select patterns
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multiclass MovzPats<RegisterClass RC, Instruction MOVZInst> {
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def : Pat<(select (i32 (setge CPURegs:$lhs, CPURegs:$rhs)), RC:$T, RC:$F),
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(MOVZInst RC:$T, (SLT CPURegs:$lhs, CPURegs:$rhs), RC:$F)>;
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def : Pat<(select (i32 (setuge CPURegs:$lhs, CPURegs:$rhs)), RC:$T, RC:$F),
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(MOVZInst RC:$T, (SLTu CPURegs:$lhs, CPURegs:$rhs), RC:$F)>;
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def : Pat<(select (i32 (setge CPURegs:$lhs, immSExt16:$rhs)), RC:$T, RC:$F),
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(MOVZInst RC:$T, (SLTi CPURegs:$lhs, immSExt16:$rhs), RC:$F)>;
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def : Pat<(select (i32 (setuge CPURegs:$lh, immSExt16:$rh)), RC:$T, RC:$F),
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(MOVZInst RC:$T, (SLTiu CPURegs:$lh, immSExt16:$rh), RC:$F)>;
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def : Pat<(select (i32 (setle CPURegs:$lhs, CPURegs:$rhs)), RC:$T, RC:$F),
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(MOVZInst RC:$T, (SLT CPURegs:$rhs, CPURegs:$lhs), RC:$F)>;
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def : Pat<(select (i32 (setule CPURegs:$lhs, CPURegs:$rhs)), RC:$T, RC:$F),
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(MOVZInst RC:$T, (SLTu CPURegs:$rhs, CPURegs:$lhs), RC:$F)>;
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def : Pat<(select (i32 (seteq CPURegs:$lhs, CPURegs:$rhs)), RC:$T, RC:$F),
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(MOVZInst RC:$T, (XOR CPURegs:$lhs, CPURegs:$rhs), RC:$F)>;
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def : Pat<(select (i32 (seteq CPURegs:$lhs, 0)), RC:$T, RC:$F),
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(MOVZInst RC:$T, CPURegs:$lhs, RC:$F)>;
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multiclass MovzPats0<RegisterClass CRC, RegisterClass DRC,
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Instruction MOVZInst, Instruction SLTOp,
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Instruction SLTuOp, Instruction SLTiOp,
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Instruction SLTiuOp> {
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def : Pat<(select (i32 (setge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
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(MOVZInst DRC:$T, (SLTOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
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def : Pat<(select (i32 (setuge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
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(MOVZInst DRC:$T, (SLTuOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
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def : Pat<(select (i32 (setge CRC:$lhs, immSExt16:$rhs)), DRC:$T, DRC:$F),
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(MOVZInst DRC:$T, (SLTiOp CRC:$lhs, immSExt16:$rhs), DRC:$F)>;
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def : Pat<(select (i32 (setuge CRC:$lh, immSExt16:$rh)), DRC:$T, DRC:$F),
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(MOVZInst DRC:$T, (SLTiuOp CRC:$lh, immSExt16:$rh), DRC:$F)>;
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def : Pat<(select (i32 (setle CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
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(MOVZInst DRC:$T, (SLTOp CRC:$rhs, CRC:$lhs), DRC:$F)>;
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def : Pat<(select (i32 (setule CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
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(MOVZInst DRC:$T, (SLTuOp CRC:$rhs, CRC:$lhs), DRC:$F)>;
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}
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multiclass MovnPats<RegisterClass RC, Instruction MOVNInst> {
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def : Pat<(select (i32 (setne CPURegs:$lhs, CPURegs:$rhs)), RC:$T, RC:$F),
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(MOVNInst RC:$T, (XOR CPURegs:$lhs, CPURegs:$rhs), RC:$F)>;
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def : Pat<(select CPURegs:$cond, RC:$T, RC:$F),
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(MOVNInst RC:$T, CPURegs:$cond, RC:$F)>;
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def : Pat<(select (i32 (setne CPURegs:$lhs, 0)), RC:$T, RC:$F),
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(MOVNInst RC:$T, CPURegs:$lhs, RC:$F)>;
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multiclass MovzPats1<RegisterClass CRC, RegisterClass DRC,
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Instruction MOVZInst, Instruction XOROp> {
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def : Pat<(select (i32 (seteq CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
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(MOVZInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;
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def : Pat<(select (i32 (seteq CRC:$lhs, 0)), DRC:$T, DRC:$F),
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(MOVZInst DRC:$T, CRC:$lhs, DRC:$F)>;
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}
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multiclass MovnPats<RegisterClass CRC, RegisterClass DRC, Instruction MOVNInst,
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Instruction XOROp> {
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def : Pat<(select (i32 (setne CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
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(MOVNInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;
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def : Pat<(select CRC:$cond, DRC:$T, DRC:$F),
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(MOVNInst DRC:$T, CRC:$cond, DRC:$F)>;
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def : Pat<(select (i32 (setne CRC:$lhs, 0)),DRC:$T, DRC:$F),
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(MOVNInst DRC:$T, CRC:$lhs, DRC:$F)>;
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}
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// Instantiation of instructions.
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def MOVZ_I : CondMovIntInt<0x0a, "movz">;
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def MOVN_I : CondMovIntInt<0x0b, "movn">;
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def MOVZ_S : CondMovIntFP<FGR32, 16, 18, "movz.s">;
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def MOVN_S : CondMovIntFP<FGR32, 16, 19, "movn.s">;
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let Predicates = [NotFP64bit] in {
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def MOVZ_D : CondMovIntFP<AFGR64, 17, 18, "movz.d">;
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def MOVN_D : CondMovIntFP<AFGR64, 17, 19, "movn.d">;
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def MOVZ_I_I : CondMovIntInt<CPURegs, CPURegs, 0x0a, "movz">;
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let Predicates = [HasMips64] in {
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def MOVZ_I_I64 : CondMovIntInt<CPURegs, CPU64Regs, 0x0a, "movz">;
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def MOVZ_I64_I : CondMovIntInt<CPU64Regs, CPURegs, 0x0a, "movz">;
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def MOVZ_I64_I64 : CondMovIntInt<CPU64Regs, CPU64Regs, 0x0a, "movz">;
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}
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def MOVT : CondMovFPInt<MipsCMovFP_T, 1, "movt">;
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def MOVF : CondMovFPInt<MipsCMovFP_F, 0, "movf">;
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def MOVN_I_I : CondMovIntInt<CPURegs, CPURegs, 0x0b, "movn">;
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let Predicates = [HasMips64] in {
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def MOVN_I_I64 : CondMovIntInt<CPURegs, CPU64Regs, 0x0b, "movn">;
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def MOVN_I64_I : CondMovIntInt<CPU64Regs, CPURegs, 0x0b, "movn">;
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def MOVN_I64_I64 : CondMovIntInt<CPU64Regs, CPU64Regs, 0x0b, "movn">;
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}
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def MOVZ_I_S : CondMovIntFP<CPURegs, FGR32, 16, 18, "movz.s">;
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def MOVZ_I64_S : CondMovIntFP<CPU64Regs, FGR32, 16, 18, "movz.s">,
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Requires<[HasMips64]>;
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def MOVN_I_S : CondMovIntFP<CPURegs, FGR32, 16, 19, "movn.s">;
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def MOVN_I64_S : CondMovIntFP<CPU64Regs, FGR32, 16, 19, "movn.s">,
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Requires<[HasMips64]>;
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let Predicates = [NotFP64bit] in {
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def MOVZ_I_D32 : CondMovIntFP<CPURegs, AFGR64, 17, 18, "movz.d">;
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def MOVN_I_D32 : CondMovIntFP<CPURegs, AFGR64, 17, 19, "movn.d">;
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}
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let Predicates = [IsFP64bit] in {
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def MOVZ_I_D64 : CondMovIntFP<CPURegs, FGR64, 17, 18, "movz.d">;
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def MOVZ_I64_D64 : CondMovIntFP<CPU64Regs, FGR64, 17, 18, "movz.d">;
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def MOVN_I_D64 : CondMovIntFP<CPURegs, FGR64, 17, 19, "movn.d">;
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def MOVN_I64_D64 : CondMovIntFP<CPU64Regs, FGR64, 17, 19, "movn.d">;
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}
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def MOVT_I : CondMovFPInt<CPURegs, MipsCMovFP_T, 1, "movt">;
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def MOVT_I64 : CondMovFPInt<CPU64Regs, MipsCMovFP_T, 1, "movt">,
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Requires<[HasMips64]>;
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def MOVF_I : CondMovFPInt<CPURegs, MipsCMovFP_F, 1, "movf">;
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def MOVF_I64 : CondMovFPInt<CPU64Regs, MipsCMovFP_F, 1, "movf">,
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Requires<[HasMips64]>;
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def MOVT_S : CondMovFPFP<FGR32, MipsCMovFP_T, 16, 1, "movt.s">;
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def MOVF_S : CondMovFPFP<FGR32, MipsCMovFP_F, 16, 0, "movf.s">;
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let Predicates = [NotFP64bit] in {
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def MOVT_D : CondMovFPFP<AFGR64, MipsCMovFP_T, 17, 1, "movt.d">;
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def MOVF_D : CondMovFPFP<AFGR64, MipsCMovFP_F, 17, 0, "movf.d">;
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def MOVT_D32 : CondMovFPFP<AFGR64, MipsCMovFP_T, 17, 1, "movt.d">;
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def MOVF_D32 : CondMovFPFP<AFGR64, MipsCMovFP_F, 17, 0, "movf.d">;
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}
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let Predicates = [IsFP64bit] in {
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def MOVT_D64 : CondMovFPFP<FGR64, MipsCMovFP_T, 17, 1, "movt.d">;
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def MOVF_D64 : CondMovFPFP<FGR64, MipsCMovFP_F, 17, 0, "movf.d">;
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}
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// Instantiation of conditional move patterns.
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defm : MovzPats<CPURegs, MOVZ_I>;
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defm : MovnPats<CPURegs, MOVN_I>;
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defm : MovzPats<FGR32, MOVZ_S>;
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defm : MovnPats<FGR32, MOVN_S>;
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let Predicates = [NotFP64bit] in {
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defm : MovzPats<AFGR64, MOVZ_D>;
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defm : MovnPats<AFGR64, MOVN_D>;
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defm : MovzPats0<CPURegs, CPURegs, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>;
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defm : MovzPats1<CPURegs, CPURegs, MOVZ_I_I, XOR>;
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let Predicates = [HasMips64] in {
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defm : MovzPats0<CPURegs, CPU64Regs, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>;
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defm : MovzPats0<CPU64Regs, CPURegs, MOVZ_I_I, SLT64, SLTu64, SLTi64,
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SLTiu64>;
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defm : MovzPats0<CPU64Regs, CPU64Regs, MOVZ_I_I64, SLT64, SLTu64, SLTi64,
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SLTiu64>;
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defm : MovzPats1<CPURegs, CPU64Regs, MOVZ_I_I64, XOR>;
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defm : MovzPats1<CPU64Regs, CPURegs, MOVZ_I64_I, XOR64>;
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defm : MovzPats1<CPU64Regs, CPU64Regs, MOVZ_I64_I64, XOR64>;
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}
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defm : MovnPats<CPURegs, CPURegs, MOVN_I_I, XOR>;
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let Predicates = [HasMips64] in {
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defm : MovnPats<CPURegs, CPU64Regs, MOVN_I_I64, XOR>;
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defm : MovnPats<CPU64Regs, CPURegs, MOVN_I64_I, XOR64>;
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defm : MovnPats<CPU64Regs, CPU64Regs, MOVN_I64_I64, XOR64>;
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}
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defm : MovzPats0<CPURegs, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>;
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defm : MovzPats1<CPURegs, FGR32, MOVZ_I_S, XOR>;
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defm : MovnPats<CPURegs, FGR32, MOVN_I_S, XOR>;
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let Predicates = [HasMips64] in {
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defm : MovzPats0<CPU64Regs, FGR32, MOVZ_I_S, SLT64, SLTu64, SLTi64,
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SLTiu64>;
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defm : MovzPats1<CPU64Regs, FGR32, MOVZ_I64_S, XOR64>;
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defm : MovnPats<CPU64Regs, FGR32, MOVN_I64_S, XOR64>;
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}
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let Predicates = [NotFP64bit] in {
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defm : MovzPats0<CPURegs, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>;
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defm : MovzPats1<CPURegs, AFGR64, MOVZ_I_D32, XOR>;
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defm : MovnPats<CPURegs, AFGR64, MOVN_I_D32, XOR>;
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}
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let Predicates = [IsFP64bit] in {
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defm : MovzPats0<CPURegs, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>;
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defm : MovzPats0<CPU64Regs, FGR64, MOVZ_I_D64, SLT64, SLTu64, SLTi64,
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SLTiu64>;
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defm : MovzPats1<CPURegs, FGR64, MOVZ_I_D64, XOR>;
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defm : MovzPats1<CPU64Regs, FGR64, MOVZ_I64_D64, XOR64>;
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defm : MovnPats<CPURegs, FGR64, MOVN_I_D64, XOR>;
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defm : MovnPats<CPU64Regs, FGR64, MOVN_I64_D64, XOR64>;
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}
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@ -708,6 +708,7 @@ static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
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return Mips::BRANCH_INVALID;
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}
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/*
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static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB,
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DebugLoc dl,
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const MipsSubtarget* Subtarget,
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@ -783,34 +784,16 @@ static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB,
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MI->eraseFromParent(); // The pseudo instruction is gone now.
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return BB;
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}
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*/
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MachineBasicBlock *
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MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *BB) const {
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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DebugLoc dl = MI->getDebugLoc();
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switch (MI->getOpcode()) {
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default:
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assert(false && "Unexpected instr type to insert");
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return NULL;
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case Mips::MOVT:
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case Mips::MOVT_S:
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case Mips::MOVT_D:
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return ExpandCondMov(MI, BB, dl, Subtarget, TII, true, Mips::BC1F);
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case Mips::MOVF:
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case Mips::MOVF_S:
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case Mips::MOVF_D:
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return ExpandCondMov(MI, BB, dl, Subtarget, TII, true, Mips::BC1T);
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case Mips::MOVZ_I:
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case Mips::MOVZ_S:
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case Mips::MOVZ_D:
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return ExpandCondMov(MI, BB, dl, Subtarget, TII, false, Mips::BNE);
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case Mips::MOVN_I:
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case Mips::MOVN_S:
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case Mips::MOVN_D:
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return ExpandCondMov(MI, BB, dl, Subtarget, TII, false, Mips::BEQ);
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case Mips::ATOMIC_LOAD_ADD_I8:
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return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
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case Mips::ATOMIC_LOAD_ADD_I16:
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@ -983,6 +983,6 @@ def : Pat<(MipsDynAlloc addr:$f), (DynAlloc addr:$f)>;
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//===----------------------------------------------------------------------===//
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include "MipsInstrFPU.td"
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include "MipsCondMov.td"
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include "Mips64InstrInfo.td"
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include "MipsCondMov.td"
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