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[AArch64][MachineCombine] Fold FNMUL+FSUB -> FNMADD.

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Differential Revision: http://reviews.llvm.org/D33101.

llvm-svn: 302822
This commit is contained in:
Chad Rosier 2017-05-11 20:07:24 +00:00
parent 2059f769c1
commit 4962115cec
3 changed files with 53 additions and 1 deletions
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2
include/llvm/CodeGen/MachineCombinerPattern.h
View File

@ -48,6 +48,8 @@ enum class MachineCombinerPattern {
FMULADDD_OP2,
FMULSUBD_OP1,
FMULSUBD_OP2,
FNMULSUBS_OP1,
FNMULSUBD_OP1,
FMLAv1i32_indexed_OP1,
FMLAv1i32_indexed_OP2,
FMLAv1i64_indexed_OP1,

28
lib/Target/AArch64/AArch64InstrInfo.cpp
View File

@ -3427,6 +3427,10 @@ static bool getFMAPatterns(MachineInstr &Root,
Patterns.push_back(MachineCombinerPattern::FMLSv1i32_indexed_OP2);
Found = true;
}
if (canCombineWithFMUL(MBB, Root.getOperand(1), AArch64::FNMULSrr)) {
Patterns.push_back(MachineCombinerPattern::FNMULSUBS_OP1);
Found = true;
}
break;
case AArch64::FSUBDrr:
if (canCombineWithFMUL(MBB, Root.getOperand(1), AArch64::FMULDrr)) {
@ -3441,6 +3445,10 @@ static bool getFMAPatterns(MachineInstr &Root,
Patterns.push_back(MachineCombinerPattern::FMLSv1i64_indexed_OP2);
Found = true;
}
if (canCombineWithFMUL(MBB, Root.getOperand(1), AArch64::FNMULDrr)) {
Patterns.push_back(MachineCombinerPattern::FNMULSUBD_OP1);
Found = true;
}
break;
case AArch64::FSUBv2f32:
if (canCombineWithFMUL(MBB, Root.getOperand(2),
@ -3495,6 +3503,8 @@ AArch64InstrInfo::isThroughputPattern(MachineCombinerPattern Pattern) const {
case MachineCombinerPattern::FMULADDD_OP2:
case MachineCombinerPattern::FMULSUBD_OP1:
case MachineCombinerPattern::FMULSUBD_OP2:
case MachineCombinerPattern::FNMULSUBS_OP1:
case MachineCombinerPattern::FNMULSUBD_OP1:
case MachineCombinerPattern::FMLAv1i32_indexed_OP1:
case MachineCombinerPattern::FMLAv1i32_indexed_OP2:
case MachineCombinerPattern::FMLAv1i64_indexed_OP1:
@ -3996,6 +4006,24 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
break;
}
case MachineCombinerPattern::FNMULSUBS_OP1:
case MachineCombinerPattern::FNMULSUBD_OP1: {
// FNMUL I=A,B,0
// FSUB R,I,C
// ==> FNMADD R,A,B,C // = -A*B - C
// --- Create(FNMADD);
if (Pattern == MachineCombinerPattern::FNMULSUBS_OP1) {
Opc = AArch64::FNMADDSrrr;
RC = &AArch64::FPR32RegClass;
} else {
Opc = AArch64::FNMADDDrrr;
RC = &AArch64::FPR64RegClass;
}
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
break;
}
case MachineCombinerPattern::FMULSUBS_OP2:
case MachineCombinerPattern::FMULSUBD_OP2: {
// FMUL I=A,B,0

24
test/CodeGen/AArch64/arm64-fml-combines.ll
View File

@ -1,4 +1,6 @@
; RUN: llc < %s -O=3 -mtriple=arm64-apple-ios -mcpu=cyclone -enable-unsafe-fp-math | FileCheck %s
; RUN: llc < %s -O3 -mtriple=arm64-apple-ios -enable-unsafe-fp-math | FileCheck %s
; RUN: llc < %s -O3 -mtriple=arm64-apple-ios -fp-contract=fast | FileCheck %s
define void @foo_2d(double* %src) {
entry:
%arrayidx1 = getelementptr inbounds double, double* %src, i64 5
@ -126,3 +128,23 @@ for.body: ; preds = %for.body, %entry
for.end: ; preds = %for.body
ret void
}
; CHECK-LABEL: test1:
; CHECK: fnmadd s0, s0, s1, s2
define float @test1(float %a, float %b, float %c) {
entry:
%0 = fmul float %a, %b
%mul = fsub float -0.000000e+00, %0
%sub1 = fsub float %mul, %c
ret float %sub1
}
; CHECK-LABEL: test2:
; CHECK: fnmadd d0, d0, d1, d2
define double @test2(double %a, double %b, double %c) {
entry:
%0 = fmul double %a, %b
%mul = fsub double -0.000000e+00, %0
%sub1 = fsub double %mul, %c
ret double %sub1
}