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[RISCV] MC layer support for the standard RV64M instruction set extension
llvm-svn: 320026
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@ -26,3 +26,11 @@ def DIVU : ALU_rr<0b0000001, 0b101, "divu">;
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def REM : ALU_rr<0b0000001, 0b110, "rem">;
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def REMU : ALU_rr<0b0000001, 0b111, "remu">;
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} // Predicates = [HasStdExtM]
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let Predicates = [HasStdExtM, IsRV64] in {
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def MULW : ALUW_rr<0b0000001, 0b000, "mulw">;
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def DIVW : ALUW_rr<0b0000001, 0b100, "divw">;
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def DIVUW : ALUW_rr<0b0000001, 0b101, "divuw">;
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def REMW : ALUW_rr<0b0000001, 0b110, "remw">;
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def REMUW : ALUW_rr<0b0000001, 0b111, "remuw">;
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} // Predicates = [HasStdExtM, IsRV64]
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9
test/MC/RISCV/rv32m-invalid.s
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9
test/MC/RISCV/rv32m-invalid.s
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@ -0,0 +1,9 @@
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# RUN: not llvm-mc -triple riscv32 -mattr=+m < %s 2>&1 | FileCheck %s
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# RV64M instructions can't be used for RV32
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mulw ra, sp, gp # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled
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divw tp, t0, t1 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled
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divuw t2, s0, s2 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled
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remw a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled
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remuw a3, a4, a5 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled
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20
test/MC/RISCV/rv64m-valid.s
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20
test/MC/RISCV/rv64m-valid.s
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@ -0,0 +1,20 @@
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# RUN: llvm-mc %s -triple=riscv64 -mattr=+m -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
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# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+m < %s \
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# RUN: | llvm-objdump -mattr=+m -d - | FileCheck -check-prefix=CHECK-INST %s
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# CHECK-INST: mulw ra, sp, gp
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# CHECK: encoding: [0xbb,0x00,0x31,0x02]
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mulw ra, sp, gp
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# CHECK-INST: divw tp, t0, t1
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# CHECK: encoding: [0x3b,0xc2,0x62,0x02]
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divw tp, t0, t1
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# CHECK-INST: divuw t2, s0, s2
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# CHECK: encoding: [0xbb,0x53,0x24,0x03]
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divuw t2, s0, s2
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# CHECK-INST: remw a0, a1, a2
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# CHECK: encoding: [0x3b,0xe5,0xc5,0x02]
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remw a0, a1, a2
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# CHECK-INST: remuw a3, a4, a5
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# CHECK: encoding: [0xbb,0x76,0xf7,0x02]
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remuw a3, a4, a5
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