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[GlobalISel] Fix load-or combine moving loads across potential aliasing stores.
Although this combine checks that there's no load folding barriers between the loads that it's trying to merge, it was inserting the load at the MIRBuilder's default insertion point, which is the G_OR use inst. This was causing a miscompile in the test suite's SingleSource/Regression/C/gcc-c-torture/execute/GCC-C-execute-bswap-2 Differential Revision: https://reviews.llvm.org/D106251
This commit is contained in:
Amara Emerson
parent
8a42745952
commit
49ad61c372
@ -596,8 +596,10 @@ private:
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/// at to the index of the load.
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/// \param [in] MemSizeInBits - The number of bits each load should produce.
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///
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/// \returns The lowest-index load found and the lowest index on success.
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Optional<std::pair<GZExtLoad *, int64_t>> findLoadOffsetsForLoadOrCombine(
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/// \returns On success, a 3-tuple containing lowest-index load found, the
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/// lowest index, and the last load in the sequence.
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Optional<std::tuple<GZExtLoad *, int64_t, GZExtLoad *>>
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findLoadOffsetsForLoadOrCombine(
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SmallDenseMap<int64_t, int64_t, 8> &MemOffset2Idx,
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const SmallVector<Register, 8> &RegsToVisit,
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const unsigned MemSizeInBits);
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@ -28,6 +28,7 @@
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#include "llvm/CodeGen/TargetOpcodes.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Target/TargetMachine.h"
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#include <tuple>
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#define DEBUG_TYPE "gi-combiner"
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@ -3455,7 +3456,7 @@ matchLoadAndBytePosition(Register Reg, unsigned MemSizeInBits,
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return std::make_pair(Load, Shift / MemSizeInBits);
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}
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Optional<std::pair<GZExtLoad *, int64_t>>
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Optional<std::tuple<GZExtLoad *, int64_t, GZExtLoad *>>
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CombinerHelper::findLoadOffsetsForLoadOrCombine(
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SmallDenseMap<int64_t, int64_t, 8> &MemOffset2Idx,
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const SmallVector<Register, 8> &RegsToVisit, const unsigned MemSizeInBits) {
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@ -3478,10 +3479,10 @@ CombinerHelper::findLoadOffsetsForLoadOrCombine(
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const MachineMemOperand *MMO = nullptr;
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// Earliest instruction-order load in the pattern.
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MachineInstr *EarliestLoad = nullptr;
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GZExtLoad *EarliestLoad = nullptr;
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// Latest instruction-order load in the pattern.
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MachineInstr *LatestLoad = nullptr;
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GZExtLoad *LatestLoad = nullptr;
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// Base pointer which every load should share.
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Register BasePtr;
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@ -3586,7 +3587,7 @@ CombinerHelper::findLoadOffsetsForLoadOrCombine(
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return None;
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}
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return std::make_pair(LowestIdxLoad, LowestIdx);
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return std::make_tuple(LowestIdxLoad, LowestIdx, LatestLoad);
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}
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bool CombinerHelper::matchLoadOrCombine(
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@ -3634,13 +3635,13 @@ bool CombinerHelper::matchLoadOrCombine(
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// Also verify that each of these ends up putting a[i] into the same memory
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// offset as a load into a wide type would.
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SmallDenseMap<int64_t, int64_t, 8> MemOffset2Idx;
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GZExtLoad *LowestIdxLoad;
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GZExtLoad *LowestIdxLoad, *LatestLoad;
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int64_t LowestIdx;
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auto MaybeLoadInfo = findLoadOffsetsForLoadOrCombine(
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MemOffset2Idx, *RegsToVisit, NarrowMemSizeInBits);
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if (!MaybeLoadInfo)
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return false;
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std::tie(LowestIdxLoad, LowestIdx) = *MaybeLoadInfo;
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std::tie(LowestIdxLoad, LowestIdx, LatestLoad) = *MaybeLoadInfo;
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// We have a bunch of loads being OR'd together. Using the addresses + offsets
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// we found before, check if this corresponds to a big or little endian byte
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@ -3695,6 +3696,7 @@ bool CombinerHelper::matchLoadOrCombine(
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return false;
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MatchInfo = [=](MachineIRBuilder &MIB) {
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MIB.setInstrAndDebugLoc(*LatestLoad);
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Register LoadDst = NeedsBSwap ? MRI.cloneVirtualRegister(Dst) : Dst;
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MIB.buildLoad(LoadDst, Ptr, *NewMMO);
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if (NeedsBSwap)
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@ -1397,9 +1397,6 @@ body: |
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name: dont_combine_store_between_different_mbb
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tracksRegLiveness: true
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body: |
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; There is a store between the two loads, hidden away in a different MBB.
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; We should not combine here.
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; LITTLE-LABEL: name: dont_combine_store_between_different_mbb
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; LITTLE: bb.0:
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; LITTLE: successors: %bb.1(0x80000000)
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@ -1444,6 +1441,9 @@ body: |
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; BIG: %full_load:_(s32) = G_OR %low_half, %high_half
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; BIG: $w1 = COPY %full_load(s32)
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; BIG: RET_ReallyLR implicit $w1
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; There is a store between the two loads, hidden away in a different MBB.
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; We should not combine here.
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bb.0:
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successors: %bb.1(0x80000000)
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@ -1479,8 +1479,6 @@ body: |
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name: different_mbb
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tracksRegLiveness: true
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body: |
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; It should be possible to combine here, but it's not supported right now.
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; LITTLE-LABEL: name: different_mbb
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; LITTLE: bb.0:
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; LITTLE: successors: %bb.1(0x80000000)
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@ -1513,6 +1511,8 @@ body: |
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; BIG: %full_load:_(s32) = G_OR %low_half, %high_half
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; BIG: $w1 = COPY %full_load(s32)
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; BIG: RET_ReallyLR implicit $w1
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; It should be possible to combine here, but it's not supported right now.
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bb.0:
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successors: %bb.1(0x80000000)
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@ -1569,3 +1569,67 @@ body: |
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%full_load:_(s32) = G_OR %low_half, %high_half
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$w1 = COPY %full_load(s32)
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RET_ReallyLR implicit $w1
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...
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---
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name: store_between_loads_and_or
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$x0' }
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- { reg: '$x1' }
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frameInfo:
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maxAlignment: 1
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body: |
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bb.1:
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liveins: $x0, $x1
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; Check that we build the G_LOAD at the point of the last load, instead of place of the G_OR.
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; We could have a G_STORE in between which may not be safe to move the load across.
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liveins: $x0, $x1
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; LITTLE-LABEL: name: store_between_loads_and_or
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; LITTLE: liveins: $x0, $x1, $x0, $x1
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; LITTLE: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; LITTLE: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
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; LITTLE: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
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; LITTLE: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32), align 1)
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; LITTLE: G_STORE [[C]](s8), [[COPY1]](p0) :: (store (s8))
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; LITTLE: $w0 = COPY [[LOAD]](s32)
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; LITTLE: RET_ReallyLR implicit $w0
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; BIG-LABEL: name: store_between_loads_and_or
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; BIG: liveins: $x0, $x1, $x0, $x1
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; BIG: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; BIG: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
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; BIG: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
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; BIG: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32), align 1)
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; BIG: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[LOAD]]
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; BIG: G_STORE [[C]](s8), [[COPY1]](p0) :: (store (s8))
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; BIG: $w0 = COPY [[BSWAP]](s32)
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; BIG: RET_ReallyLR implicit $w0
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%0:_(p0) = COPY $x0
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%1:_(p0) = COPY $x1
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%12:_(s8) = G_CONSTANT i8 1
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%15:_(s32) = G_CONSTANT i32 8
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%19:_(s32) = G_CONSTANT i32 16
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%23:_(s32) = G_CONSTANT i32 24
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%13:_(s32) = G_ZEXTLOAD %0:_(p0) :: (load (s8))
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%3:_(s64) = G_CONSTANT i64 1
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%4:_(p0) = G_PTR_ADD %0:_, %3:_(s64)
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%14:_(s32) = G_ZEXTLOAD %4:_(p0) :: (load (s8))
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%6:_(s64) = G_CONSTANT i64 2
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%7:_(p0) = G_PTR_ADD %0:_, %6:_(s64)
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%18:_(s32) = G_ZEXTLOAD %7:_(p0) :: (load (s8))
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%9:_(s64) = G_CONSTANT i64 3
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%10:_(p0) = G_PTR_ADD %0:_, %9:_(s64)
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%22:_(s32) = G_ZEXTLOAD %10:_(p0) :: (load (s8))
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G_STORE %12:_(s8), %1:_(p0) :: (store (s8))
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%16:_(s32) = nuw nsw G_SHL %14:_, %15:_(s32)
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%17:_(s32) = G_OR %16:_, %13:_
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%20:_(s32) = nuw nsw G_SHL %18:_, %19:_(s32)
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%21:_(s32) = G_OR %17:_, %20:_
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%24:_(s32) = nuw G_SHL %22:_, %23:_(s32)
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%25:_(s32) = G_OR %21:_, %24:_
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$w0 = COPY %25:_(s32)
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RET_ReallyLR implicit $w0
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...
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