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Change the calling convention used when tail call optimization is enabled from CC_X86_32_TailCall to CC_X86_32_FastCC.

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llvm-svn: 56436
This commit is contained in:
Arnold Schwaighofer 2008-09-22 14:50:07 +00:00
parent efe64e5f1e
commit 49f49e2086
6 changed files with 5 additions and 25 deletions
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16
lib/Target/X86/X86CallingConv.td
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@ -312,22 +312,6 @@ def CC_X86_32_C : CallingConv<[
CCDelegateTo<CC_X86_32_Common>
]>;
/// Same as C calling convention except for non-free ECX which is used for storing
/// a potential pointer to the tail called function.
def CC_X86_32_TailCall : CallingConv<[
// Promote i8/i16 arguments to i32.
CCIfType<[i8, i16], CCPromoteToType<i32>>,
// Nested function trampolines are currently not supported by fastcc.
// The first 3 integer arguments, if marked 'inreg' and if the call is not
// a vararg call, are passed in integer registers.
CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX]>>>>,
// Otherwise, same as everything else.
CCDelegateTo<CC_X86_32_Common>
]>;
def CC_X86_32_FastCall : CallingConv<[
// Promote i8/i16 arguments to i32.
CCIfType<[i8, i16], CCPromoteToType<i32>>,

2
lib/Target/X86/X86FastISel.cpp
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@ -142,8 +142,6 @@ CCAssignFn *X86FastISel::CCAssignFnForCall(unsigned CC, bool isTaillCall) {
if (CC == CallingConv::X86_FastCall)
return CC_X86_32_FastCall;
else if (CC == CallingConv::Fast && isTaillCall)
return CC_X86_32_TailCall;
else if (CC == CallingConv::Fast)
return CC_X86_32_FastCC;
else

6
lib/Target/X86/X86ISelLowering.cpp
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@ -890,7 +890,7 @@ SDValue X86TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
SDValue TargetAddress = TailCall.getOperand(1);
SDValue StackAdjustment = TailCall.getOperand(2);
assert(((TargetAddress.getOpcode() == ISD::Register &&
(cast<RegisterSDNode>(TargetAddress)->getReg() == X86::ECX ||
(cast<RegisterSDNode>(TargetAddress)->getReg() == X86::EAX ||
cast<RegisterSDNode>(TargetAddress)->getReg() == X86::R9)) ||
TargetAddress.getOpcode() == ISD::TargetExternalSymbol ||
TargetAddress.getOpcode() == ISD::TargetGlobalAddress) &&
@ -1098,8 +1098,6 @@ CCAssignFn *X86TargetLowering::CCAssignFnForNode(unsigned CC) const {
if (CC == CallingConv::X86_FastCall)
return CC_X86_32_FastCall;
else if (CC == CallingConv::Fast && PerformTailCallOpt)
return CC_X86_32_TailCall;
else if (CC == CallingConv::Fast)
return CC_X86_32_FastCC;
else
@ -1700,7 +1698,7 @@ SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
} else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
} else if (IsTailCall) {
unsigned Opc = Is64Bit ? X86::R9 : X86::ECX;
unsigned Opc = Is64Bit ? X86::R9 : X86::EAX;
Chain = DAG.getCopyToReg(Chain,
DAG.getRegister(Opc, getPointerTy()),

2
test/CodeGen/X86/tailcall-stackalign.ll
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@ -1,4 +1,4 @@
; RUN: llvm-as < %s | llc -mtriple=i686-unknown-linux -tailcallopt | grep -A 1 call | grep -A 1 tailcaller | grep subl | grep 20
; RUN: llvm-as < %s | llc -mtriple=i686-unknown-linux -tailcallopt | grep -A 1 call | grep -A 1 tailcaller | grep subl | grep 12
; Linux has 8 byte alignment so the params cause stack size 20 when tailcallopt
; is enabled, ensure that a normal fastcc call has matching stack size

2
test/CodeGen/X86/tailcallbyval.ll
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@ -1,6 +1,6 @@
; RUN: llvm-as < %s | llc -march=x86 -tailcallopt | grep TAILCALL
; check for the 2 byval moves
; RUN: llvm-as < %s | llc -march=x86 -tailcallopt | grep rep | wc -l | grep 2
; RUN: llvm-as < %s | llc -march=x86 -tailcallopt | grep movl | grep ecx | grep eax | wc -l | grep 1
%struct.s = type {i32, i32, i32, i32, i32, i32, i32, i32,
i32, i32, i32, i32, i32, i32, i32, i32,
i32, i32, i32, i32, i32, i32, i32, i32 }

2
test/CodeGen/X86/tailcallfp2.ll
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@ -1,4 +1,4 @@
; RUN: llvm-as < %s | llc -march=x86 -tailcallopt | grep {jmp} | grep {\\*%ecx}
; RUN: llvm-as < %s | llc -march=x86 -tailcallopt | grep {jmp} | grep {\\*%eax}
declare i32 @putchar(i32)