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[InstCombine] add vector select of binops tests (PR37806)
These represent the most basic requested transform - a matching operand and 2 constant operands. llvm-svn: 335151
This commit is contained in:
Sanjay Patel
parent
ac70638af3
commit
4a0755b37f
256
test/Transforms/InstCombine/shuffle_select.ll
Normal file
256
test/Transforms/InstCombine/shuffle_select.ll
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@ -0,0 +1,256 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instcombine -S | FileCheck %s
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; Try to eliminate binops and shuffles when the shuffle is a select in disguise:
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; PR37806 - https://bugs.llvm.org/show_bug.cgi?id=37806
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define <4 x i32> @add(<4 x i32> %v0) {
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; CHECK-LABEL: @add(
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; CHECK-NEXT: [[T1:%.*]] = add <4 x i32> [[V0:%.*]], <i32 1, i32 undef, i32 3, i32 undef>
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; CHECK-NEXT: [[T2:%.*]] = add <4 x i32> [[V0]], <i32 undef, i32 6, i32 undef, i32 8>
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; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x i32> [[T1]], <4 x i32> [[T2]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
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; CHECK-NEXT: ret <4 x i32> [[T3]]
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;
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%t1 = add <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
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%t2 = add <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
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%t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
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ret <4 x i32> %t3
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}
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; Constant operand 0 (LHS) also works.
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define <4 x i32> @sub(<4 x i32> %v0) {
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; CHECK-LABEL: @sub(
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; CHECK-NEXT: [[T1:%.*]] = sub <4 x i32> <i32 1, i32 2, i32 3, i32 undef>, [[V0:%.*]]
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; CHECK-NEXT: [[T2:%.*]] = sub <4 x i32> <i32 undef, i32 undef, i32 undef, i32 8>, [[V0]]
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; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x i32> [[T1]], <4 x i32> [[T2]], <4 x i32> <i32 0, i32 1, i32 2, i32 7>
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; CHECK-NEXT: ret <4 x i32> [[T3]]
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;
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%t1 = sub <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
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%t2 = sub <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0
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%t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
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ret <4 x i32> %t3
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}
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; If any element of the shuffle mask operand is undef, that element of the result is undef.
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; The shuffle is eliminated in this transform, but we can replace a constant element with undef.
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define <4 x i32> @mul(<4 x i32> %v0) {
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; CHECK-LABEL: @mul(
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; CHECK-NEXT: [[T1:%.*]] = mul <4 x i32> [[V0:%.*]], <i32 undef, i32 undef, i32 3, i32 undef>
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; CHECK-NEXT: [[T2:%.*]] = mul <4 x i32> [[V0]], <i32 undef, i32 6, i32 undef, i32 8>
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; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x i32> [[T1]], <4 x i32> [[T2]], <4 x i32> <i32 undef, i32 5, i32 2, i32 7>
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; CHECK-NEXT: ret <4 x i32> [[T3]]
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;
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%t1 = mul <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
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%t2 = mul <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
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%t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 5, i32 2, i32 7>
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ret <4 x i32> %t3
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}
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; Preserve flags when possible.
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define <4 x i32> @shl(<4 x i32> %v0) {
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; CHECK-LABEL: @shl(
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; CHECK-NEXT: [[T1:%.*]] = shl nuw <4 x i32> [[V0:%.*]], <i32 1, i32 2, i32 3, i32 4>
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; CHECK-NEXT: [[T2:%.*]] = shl nuw <4 x i32> [[V0]], <i32 5, i32 6, i32 7, i32 8>
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; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x i32> [[T1]], <4 x i32> [[T2]], <4 x i32> <i32 undef, i32 5, i32 2, i32 undef>
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; CHECK-NEXT: ret <4 x i32> [[T3]]
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;
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%t1 = shl nuw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
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%t2 = shl nuw <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
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%t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 5, i32 2, i32 undef>
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ret <4 x i32> %t3
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}
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; Can't propagate the flag here.
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define <4 x i32> @lshr(<4 x i32> %v0) {
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; CHECK-LABEL: @lshr(
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; CHECK-NEXT: [[T1:%.*]] = lshr exact <4 x i32> <i32 1, i32 2, i32 3, i32 4>, [[V0:%.*]]
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; CHECK-NEXT: [[T2:%.*]] = lshr <4 x i32> <i32 5, i32 6, i32 7, i32 8>, [[V0]]
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; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x i32> [[T1]], <4 x i32> [[T2]], <4 x i32> <i32 4, i32 5, i32 2, i32 7>
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; CHECK-NEXT: ret <4 x i32> [[T3]]
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;
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%t1 = lshr exact <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
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%t2 = lshr <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0
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%t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
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ret <4 x i32> %t3
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}
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; Try weird types.
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define <3 x i32> @ashr(<3 x i32> %v0) {
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; CHECK-LABEL: @ashr(
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; CHECK-NEXT: [[T1:%.*]] = ashr <3 x i32> [[V0:%.*]], <i32 1, i32 2, i32 3>
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; CHECK-NEXT: [[T2:%.*]] = ashr <3 x i32> [[V0]], <i32 4, i32 5, i32 6>
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; CHECK-NEXT: [[T3:%.*]] = shufflevector <3 x i32> [[T1]], <3 x i32> [[T2]], <3 x i32> <i32 3, i32 1, i32 2>
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; CHECK-NEXT: ret <3 x i32> [[T3]]
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;
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%t1 = ashr <3 x i32> %v0, <i32 1, i32 2, i32 3>
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%t2 = ashr <3 x i32> %v0, <i32 4, i32 5, i32 6>
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%t3 = shufflevector <3 x i32> %t1, <3 x i32> %t2, <3 x i32> <i32 3, i32 1, i32 2>
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ret <3 x i32> %t3
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}
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define <3 x i42> @and(<3 x i42> %v0) {
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; CHECK-LABEL: @and(
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; CHECK-NEXT: [[T1:%.*]] = and <3 x i42> [[V0:%.*]], <i42 1, i42 undef, i42 undef>
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; CHECK-NEXT: [[T2:%.*]] = and <3 x i42> [[V0]], <i42 undef, i42 5, i42 undef>
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; CHECK-NEXT: [[T3:%.*]] = shufflevector <3 x i42> [[T1]], <3 x i42> [[T2]], <3 x i32> <i32 0, i32 4, i32 undef>
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; CHECK-NEXT: ret <3 x i42> [[T3]]
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;
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%t1 = and <3 x i42> %v0, <i42 1, i42 2, i42 3>
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%t2 = and <3 x i42> %v0, <i42 4, i42 5, i42 6>
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%t3 = shufflevector <3 x i42> %t1, <3 x i42> %t2, <3 x i32> <i32 0, i32 4, i32 undef>
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ret <3 x i42> %t3
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}
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; It doesn't matter if the intermediate ops have extra uses.
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declare void @use_v4i32(<4 x i32>)
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define <4 x i32> @or(<4 x i32> %v0) {
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; CHECK-LABEL: @or(
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; CHECK-NEXT: [[T1:%.*]] = or <4 x i32> [[V0:%.*]], <i32 1, i32 2, i32 3, i32 4>
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; CHECK-NEXT: [[T2:%.*]] = or <4 x i32> [[V0]], <i32 5, i32 6, i32 undef, i32 undef>
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; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x i32> [[T1]], <4 x i32> [[T2]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>
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; CHECK-NEXT: call void @use_v4i32(<4 x i32> [[T1]])
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; CHECK-NEXT: ret <4 x i32> [[T3]]
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;
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%t1 = or <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
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%t2 = or <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
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%t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
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call void @use_v4i32(<4 x i32> %t1)
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ret <4 x i32> %t3
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}
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define <4 x i32> @xor(<4 x i32> %v0) {
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; CHECK-LABEL: @xor(
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; CHECK-NEXT: [[T1:%.*]] = xor <4 x i32> [[V0:%.*]], <i32 1, i32 undef, i32 3, i32 4>
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; CHECK-NEXT: [[T2:%.*]] = xor <4 x i32> [[V0]], <i32 5, i32 6, i32 7, i32 8>
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; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x i32> [[T1]], <4 x i32> [[T2]], <4 x i32> <i32 0, i32 5, i32 2, i32 3>
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; CHECK-NEXT: call void @use_v4i32(<4 x i32> [[T2]])
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; CHECK-NEXT: ret <4 x i32> [[T3]]
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;
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%t1 = xor <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
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%t2 = xor <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
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%t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
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call void @use_v4i32(<4 x i32> %t2)
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ret <4 x i32> %t3
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}
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define <4 x i32> @udiv(<4 x i32> %v0) {
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; CHECK-LABEL: @udiv(
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; CHECK-NEXT: [[T1:%.*]] = udiv <4 x i32> <i32 1, i32 2, i32 3, i32 4>, [[V0:%.*]]
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; CHECK-NEXT: [[T2:%.*]] = udiv <4 x i32> <i32 5, i32 6, i32 7, i32 8>, [[V0]]
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; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x i32> [[T1]], <4 x i32> [[T2]], <4 x i32> <i32 0, i32 1, i32 2, i32 7>
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; CHECK-NEXT: call void @use_v4i32(<4 x i32> [[T1]])
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; CHECK-NEXT: call void @use_v4i32(<4 x i32> [[T2]])
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; CHECK-NEXT: ret <4 x i32> [[T3]]
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;
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%t1 = udiv <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
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%t2 = udiv <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0
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%t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
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call void @use_v4i32(<4 x i32> %t1)
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call void @use_v4i32(<4 x i32> %t2)
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ret <4 x i32> %t3
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}
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; Div/rem need special handling if the shuffle has undef elements.
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define <4 x i32> @sdiv(<4 x i32> %v0) {
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; CHECK-LABEL: @sdiv(
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; CHECK-NEXT: [[T1:%.*]] = sdiv <4 x i32> [[V0:%.*]], <i32 1, i32 2, i32 3, i32 4>
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; CHECK-NEXT: [[T2:%.*]] = sdiv <4 x i32> [[V0]], <i32 5, i32 6, i32 7, i32 8>
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; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x i32> [[T1]], <4 x i32> [[T2]], <4 x i32> <i32 undef, i32 1, i32 6, i32 undef>
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; CHECK-NEXT: ret <4 x i32> [[T3]]
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;
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%t1 = sdiv <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
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%t2 = sdiv <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
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%t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 1, i32 6, i32 undef>
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ret <4 x i32> %t3
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}
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define <4 x i32> @urem(<4 x i32> %v0) {
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; CHECK-LABEL: @urem(
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; CHECK-NEXT: [[T1:%.*]] = urem <4 x i32> <i32 1, i32 2, i32 3, i32 4>, [[V0:%.*]]
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; CHECK-NEXT: [[T2:%.*]] = urem <4 x i32> <i32 5, i32 6, i32 7, i32 8>, [[V0]]
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; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x i32> [[T1]], <4 x i32> [[T2]], <4 x i32> <i32 0, i32 1, i32 6, i32 undef>
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; CHECK-NEXT: ret <4 x i32> [[T3]]
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;
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%t1 = urem <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
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%t2 = urem <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0
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%t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 1, i32 6, i32 undef>
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ret <4 x i32> %t3
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}
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define <4 x i32> @srem(<4 x i32> %v0) {
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; CHECK-LABEL: @srem(
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; CHECK-NEXT: [[T1:%.*]] = srem <4 x i32> <i32 1, i32 2, i32 3, i32 4>, [[V0:%.*]]
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; CHECK-NEXT: [[T2:%.*]] = srem <4 x i32> <i32 5, i32 6, i32 7, i32 8>, [[V0]]
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; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x i32> [[T1]], <4 x i32> [[T2]], <4 x i32> <i32 0, i32 1, i32 6, i32 3>
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; CHECK-NEXT: ret <4 x i32> [[T3]]
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;
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%t1 = srem <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
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%t2 = srem <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0
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%t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
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ret <4 x i32> %t3
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}
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; Try FP ops/types.
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define <4 x float> @fadd(<4 x float> %v0) {
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; CHECK-LABEL: @fadd(
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; CHECK-NEXT: [[T1:%.*]] = fadd <4 x float> [[V0:%.*]], <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>
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; CHECK-NEXT: [[T2:%.*]] = fadd <4 x float> [[V0]], <float 5.000000e+00, float 6.000000e+00, float 7.000000e+00, float 8.000000e+00>
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; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x float> [[T1]], <4 x float> [[T2]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
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; CHECK-NEXT: ret <4 x float> [[T3]]
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;
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%t1 = fadd <4 x float> %v0, <float 1.0, float 2.0, float 3.0, float 4.0>
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%t2 = fadd <4 x float> %v0, <float 5.0, float 6.0, float 7.0, float 8.0>
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%t3 = shufflevector <4 x float> %t1, <4 x float> %t2, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
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ret <4 x float> %t3
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}
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define <4 x double> @fsub(<4 x double> %v0) {
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; CHECK-LABEL: @fsub(
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; CHECK-NEXT: [[T1:%.*]] = fsub <4 x double> <double 1.000000e+00, double 2.000000e+00, double 3.000000e+00, double 4.000000e+00>, [[V0:%.*]]
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; CHECK-NEXT: [[T2:%.*]] = fsub <4 x double> <double 5.000000e+00, double 6.000000e+00, double 7.000000e+00, double 8.000000e+00>, [[V0]]
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; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x double> [[T1]], <4 x double> [[T2]], <4 x i32> <i32 undef, i32 1, i32 6, i32 7>
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; CHECK-NEXT: ret <4 x double> [[T3]]
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;
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%t1 = fsub <4 x double> <double 1.0, double 2.0, double 3.0, double 4.0>, %v0
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%t2 = fsub <4 x double> <double 5.0, double 6.0, double 7.0, double 8.0>, %v0
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%t3 = shufflevector <4 x double> %t1, <4 x double> %t2, <4 x i32> <i32 undef, i32 1, i32 6, i32 7>
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ret <4 x double> %t3
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}
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; Union any FMF.
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define <4 x float> @fmul(<4 x float> %v0) {
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; CHECK-LABEL: @fmul(
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; CHECK-NEXT: [[T1:%.*]] = fmul nnan ninf <4 x float> [[V0:%.*]], <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>
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; CHECK-NEXT: [[T2:%.*]] = fmul nnan ninf <4 x float> [[V0]], <float 5.000000e+00, float 6.000000e+00, float 7.000000e+00, float 8.000000e+00>
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; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x float> [[T1]], <4 x float> [[T2]], <4 x i32> <i32 0, i32 5, i32 6, i32 7>
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; CHECK-NEXT: ret <4 x float> [[T3]]
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;
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%t1 = fmul nnan ninf <4 x float> %v0, <float 1.0, float 2.0, float 3.0, float 4.0>
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%t2 = fmul nnan ninf <4 x float> %v0, <float 5.0, float 6.0, float 7.0, float 8.0>
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%t3 = shufflevector <4 x float> %t1, <4 x float> %t2, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
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ret <4 x float> %t3
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}
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define <4 x double> @fdiv(<4 x double> %v0) {
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; CHECK-LABEL: @fdiv(
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; CHECK-NEXT: [[T1:%.*]] = fdiv fast <4 x double> <double 1.000000e+00, double 2.000000e+00, double 3.000000e+00, double 4.000000e+00>, [[V0:%.*]]
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; CHECK-NEXT: [[T2:%.*]] = fdiv nnan arcp <4 x double> <double 5.000000e+00, double 6.000000e+00, double 7.000000e+00, double 8.000000e+00>, [[V0]]
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; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x double> [[T1]], <4 x double> [[T2]], <4 x i32> <i32 undef, i32 1, i32 6, i32 7>
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; CHECK-NEXT: ret <4 x double> [[T3]]
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;
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%t1 = fdiv fast <4 x double> <double 1.0, double 2.0, double 3.0, double 4.0>, %v0
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%t2 = fdiv nnan arcp <4 x double> <double 5.0, double 6.0, double 7.0, double 8.0>, %v0
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%t3 = shufflevector <4 x double> %t1, <4 x double> %t2, <4 x i32> <i32 undef, i32 1, i32 6, i32 7>
|
||||
ret <4 x double> %t3
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user