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[APFloat] convert SNaN to QNaN in convert() and raise Invalid signal

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This is an alternate fix (see D87835) for a bug where a NaN constant
gets wrongly transformed into Infinity via truncation.
In this patch, we uniformly convert any SNaN to QNaN while raising
'invalid op'.
But we don't have a way to directly specify a 32-bit SNaN value in LLVM IR,
so those are always encoded/decoded by calling convert from/to 64-bit hex.

See D88664 for a clang fix needed to allow this change.

Differential Revision: https://reviews.llvm.org/D88238
This commit is contained in:
Sanjay Patel 2020-10-01 14:23:18 -04:00
parent 920d09ef67
commit 4a25740376
6 changed files with 51 additions and 37 deletions
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10
lib/AsmParser/LLParser.cpp
View File

@ -5345,6 +5345,8 @@ bool LLParser::ConvertValIDToValue(Type *Ty, ValID &ID, Value *&V,
// The lexer has no type info, so builds all half, bfloat, float, and double
// FP constants as double. Fix this here. Long double does not need this.
if (&ID.APFloatVal.getSemantics() == &APFloat::IEEEdouble()) {
// Check for signaling before potentially converting and losing that info.
bool IsSNAN = ID.APFloatVal.isSignaling();
bool Ignored;
if (Ty->isHalfTy())
ID.APFloatVal.convert(APFloat::IEEEhalf(), APFloat::rmNearestTiesToEven,
@ -5355,6 +5357,14 @@ bool LLParser::ConvertValIDToValue(Type *Ty, ValID &ID, Value *&V,
else if (Ty->isFloatTy())
ID.APFloatVal.convert(APFloat::IEEEsingle(), APFloat::rmNearestTiesToEven,
&Ignored);
if (IsSNAN) {
// The convert call above may quiet an SNaN, so manufacture another
// SNaN. The bitcast works because the payload (significand) parameter
// is truncated to fit.
APInt Payload = ID.APFloatVal.bitcastToAPInt();
ID.APFloatVal = APFloat::getSNaN(ID.APFloatVal.getSemantics(),
ID.APFloatVal.isNegative(), &Payload);
}
}
V = ConstantFP::get(Context, ID.APFloatVal);

14
lib/IR/AsmWriter.cpp
View File

@ -1373,9 +1373,19 @@ static void WriteConstantInternal(raw_ostream &Out, const Constant *CV,
"assuming that double is 64 bits!");
APFloat apf = APF;
// Floats are represented in ASCII IR as double, convert.
if (!isDouble)
// FIXME: We should allow 32-bit hex float and remove this.
if (!isDouble) {
// A signaling NaN is quieted on conversion, so we need to recreate the
// expected value after convert (quiet bit of the payload is clear).
bool IsSNAN = apf.isSignaling();
apf.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven,
&ignored);
&ignored);
if (IsSNAN) {
APInt Payload = apf.bitcastToAPInt();
apf = APFloat::getSNaN(APFloat::IEEEdouble(), apf.isNegative(),
&Payload);
}
}
Out << format_hex(apf.bitcastToAPInt().getZExtValue(), 0, /*Upper=*/true);
return;
}

27
lib/Support/APFloat.cpp
View File

@ -2243,26 +2243,15 @@ IEEEFloat::opStatus IEEEFloat::convert(const fltSemantics &toSemantics,
if (!X86SpecialNan && semantics == &semX87DoubleExtended)
APInt::tcSetBit(significandParts(), semantics->precision - 1);
// If we are truncating NaN, it is possible that we shifted out all of the
// set bits in a signalling NaN payload. But NaN must remain NaN, so some
// bit in the significand must be set (otherwise it is Inf).
// This can only happen with sNaN. Set the 1st bit after the quiet bit,
// so that we still have an sNaN.
// FIXME: Set quiet and return opInvalidOp (on convert of any sNaN).
// But this requires fixing LLVM to parse 32-bit hex FP or ignoring
// conversions while parsing IR.
if (APInt::tcIsZero(significandParts(), newPartCount)) {
assert(shift < 0 && "Should not lose NaN payload on extend");
assert(semantics->precision >= 3 && "Unexpectedly narrow significand");
assert(*losesInfo && "Missing payload should have set lost info");
APInt::tcSetBit(significandParts(), semantics->precision - 3);
// Convert of sNaN creates qNaN and raises an exception (invalid op).
// This also guarantees that a sNaN does not become Inf on a truncation
// that loses all payload bits.
if (isSignaling()) {
makeQuiet();
fs = opInvalidOp;
} else {
fs = opOK;
}
// gcc forces the Quiet bit on, which means (float)(double)(float_sNan)
// does not give you back the same bits. This is dubious, and we
// don't currently do it. You're really supposed to get
// an invalid operation signal at runtime, but nobody does that.
fs = opOK;
} else {
*losesInfo = false;
fs = opOK;

8
test/Transforms/InstSimplify/ConstProp/cast.ll
View File

@ -40,24 +40,24 @@ define float @overflow_sitofp() {
}
; https://llvm.org/PR43907 - make sure that NaN doesn't morph into Inf.
; SNaN remains SNaN.
; SNaN becomes QNaN.
define float @nan_f64_trunc() {
; CHECK-LABEL: @nan_f64_trunc(
; CHECK-NEXT: ret float 0x7FF4000000000000
; CHECK-NEXT: ret float 0x7FF8000000000000
;
%f = fptrunc double 0x7FF0000000000001 to float
ret float %f
}
; Verify again with a vector and different destination type.
; SNaN remains SNaN (first two elements).
; SNaN becomes SNaN (first two elements).
; QNaN remains QNaN (third element).
; Lower 42 bits of NaN source payload are lost.
define <3 x half> @nan_v3f64_trunc() {
; CHECK-LABEL: @nan_v3f64_trunc(
; CHECK-NEXT: ret <3 x half> <half 0xH7D00, half 0xH7D00, half 0xH7E00>
; CHECK-NEXT: ret <3 x half> <half 0xH7E00, half 0xH7E00, half 0xH7E00>
;
%f = fptrunc <3 x double> <double 0x7FF0020000000000, double 0x7FF003FFFFFFFFFF, double 0x7FF8000000000001> to <3 x half>
ret <3 x half> %f

15
test/Transforms/PhaseOrdering/X86/nancvt.ll
View File

@ -18,6 +18,9 @@ target triple = "i686-apple-darwin8"
@var = external global i32
; SNAN becomes QNAN on fptrunc:
; 2147228864 = 0x7ffc1cc0 : QNAN
define i32 @main() {
; CHECK-LABEL: @main(
; CHECK-NEXT: entry:
@ -30,15 +33,15 @@ define i32 @main() {
; CHECK-NEXT: store volatile i32 2147228864, i32* @var, align 4
; CHECK-NEXT: store volatile i32 2147228864, i32* @var, align 4
; CHECK-NEXT: store volatile i32 2147228864, i32* @var, align 4
; CHECK-NEXT: store volatile i32 2146502828, i32* @var, align 4
; CHECK-NEXT: store volatile i32 2147027116, i32* @var, align 4
; CHECK-NEXT: store volatile i32 -1610612736, i32* @var, align 4
; CHECK-NEXT: store volatile i32 2146502828, i32* @var, align 4
; CHECK-NEXT: store volatile i32 2147027116, i32* @var, align 4
; CHECK-NEXT: store volatile i32 -2147483648, i32* @var, align 4
; CHECK-NEXT: store volatile i32 2146502828, i32* @var, align 4
; CHECK-NEXT: store volatile i32 2147027116, i32* @var, align 4
; CHECK-NEXT: store volatile i32 -1073741824, i32* @var, align 4
; CHECK-NEXT: store volatile i32 2143034560, i32* @var, align 4
; CHECK-NEXT: store volatile i32 2143034560, i32* @var, align 4
; CHECK-NEXT: store volatile i32 2143034560, i32* @var, align 4
; CHECK-NEXT: store volatile i32 2147228864, i32* @var, align 4
; CHECK-NEXT: store volatile i32 2147228864, i32* @var, align 4
; CHECK-NEXT: store volatile i32 2147228864, i32* @var, align 4
; CHECK-NEXT: ret i32 undef
;
entry:

14
unittests/ADT/APFloatTest.cpp
View File

@ -1816,11 +1816,12 @@ TEST(APFloatTest, convert) {
EXPECT_FALSE(losesInfo);
test = APFloat::getSNaN(APFloat::IEEEsingle());
APFloat X87SNaN = APFloat::getSNaN(APFloat::x87DoubleExtended());
APFloat::opStatus status = test.convert(APFloat::x87DoubleExtended(), APFloat::rmNearestTiesToEven, &losesInfo);
EXPECT_TRUE(test.bitwiseIsEqual(X87SNaN));
// Conversion quiets the SNAN, so now 2 bits of the 64-bit significand should be set.
APInt topTwoBits(64, 0x6000000000000000);
EXPECT_TRUE(test.bitwiseIsEqual(APFloat::getQNaN(APFloat::x87DoubleExtended(), false, &topTwoBits)));
EXPECT_FALSE(losesInfo);
EXPECT_EQ(status, APFloat::opOK);
EXPECT_EQ(status, APFloat::opInvalidOp);
test = APFloat::getQNaN(APFloat::IEEEsingle());
APFloat X87QNaN = APFloat::getQNaN(APFloat::x87DoubleExtended());
@ -1832,6 +1833,7 @@ TEST(APFloatTest, convert) {
test = APFloat::getSNaN(APFloat::x87DoubleExtended());
test.convert(APFloat::x87DoubleExtended(), APFloat::rmNearestTiesToEven,
&losesInfo);
APFloat X87SNaN = APFloat::getSNaN(APFloat::x87DoubleExtended());
EXPECT_TRUE(test.bitwiseIsEqual(X87SNaN));
EXPECT_FALSE(losesInfo);
@ -1841,13 +1843,13 @@ TEST(APFloatTest, convert) {
EXPECT_TRUE(test.bitwiseIsEqual(X87QNaN));
EXPECT_FALSE(losesInfo);
// The payload is lost in truncation, but we must retain NaN, so we set the bit after the quiet bit.
// The payload is lost in truncation, but we retain NaN by setting the quiet bit.
APInt payload(52, 1);
test = APFloat::getSNaN(APFloat::IEEEdouble(), false, &payload);
status = test.convert(APFloat::IEEEsingle(), APFloat::rmNearestTiesToEven, &losesInfo);
EXPECT_EQ(0x7fa00000, test.bitcastToAPInt());
EXPECT_EQ(0x7fc00000, test.bitcastToAPInt());
EXPECT_TRUE(losesInfo);
EXPECT_EQ(status, APFloat::opOK);
EXPECT_EQ(status, APFloat::opInvalidOp);
// The payload is lost in truncation. QNaN remains QNaN.
test = APFloat::getQNaN(APFloat::IEEEdouble(), false, &payload);