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Explictly pass MCSubtargetInfo to MCCodeEmitter::EncodeInstruction()

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llvm-svn: 200348
This commit is contained in:
David Woodhouse 2014-01-28 23:13:07 +00:00
parent b9294892a1
commit 4a4c611e36
18 changed files with 52 additions and 30 deletions
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4
include/llvm/MC/MCCodeEmitter.h
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@ -15,6 +15,7 @@
namespace llvm {
class MCFixup;
class MCInst;
class MCSubtargetInfo;
class raw_ostream;
template<typename T> class SmallVectorImpl;
@ -35,7 +36,8 @@ public:
/// EncodeInstruction - Encode the given \p Inst to bytes on the output
/// stream \p OS.
virtual void EncodeInstruction(const MCInst &Inst, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups) const = 0;
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const = 0;
};
} // End llvm namespace

9
lib/MC/MCAsmStreamer.cpp
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@ -104,7 +104,7 @@ public:
virtual void AddComment(const Twine &T);
/// AddEncodingComment - Add a comment showing the encoding of an instruction.
virtual void AddEncodingComment(const MCInst &Inst);
virtual void AddEncodingComment(const MCInst &Inst, const MCSubtargetInfo &);
/// GetCommentOS - Return a raw_ostream that comments can be written to.
/// Unlike AddComment, you are required to terminate comments with \n if you
@ -1234,12 +1234,13 @@ void MCAsmStreamer::EmitWin64EHEndProlog(void) {
EmitEOL();
}
void MCAsmStreamer::AddEncodingComment(const MCInst &Inst) {
void MCAsmStreamer::AddEncodingComment(const MCInst &Inst,
const MCSubtargetInfo &STI) {
raw_ostream &OS = GetCommentOS();
SmallString<256> Code;
SmallVector<MCFixup, 4> Fixups;
raw_svector_ostream VecOS(Code);
Emitter->EncodeInstruction(Inst, VecOS, Fixups);
Emitter->EncodeInstruction(Inst, VecOS, Fixups, STI);
VecOS.flush();
// If we are showing fixups, create symbolic markers in the encoded
@ -1324,7 +1325,7 @@ void MCAsmStreamer::EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &S
// Show the encoding in a comment if we have a code emitter.
if (Emitter)
AddEncodingComment(Inst);
AddEncodingComment(Inst, STI);
// Show the MCInst if enabled.
if (ShowInst) {

2
lib/MC/MCAssembler.cpp
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@ -875,7 +875,7 @@ bool MCAssembler::relaxInstruction(MCAsmLayout &Layout,
SmallVector<MCFixup, 4> Fixups;
SmallString<256> Code;
raw_svector_ostream VecOS(Code);
getEmitter().EncodeInstruction(Relaxed, VecOS, Fixups);
getEmitter().EncodeInstruction(Relaxed, VecOS, Fixups, F.getSubtargetInfo());
VecOS.flush();
// Update the fragment.

2
lib/MC/MCELFStreamer.cpp
View File

@ -412,7 +412,7 @@ void MCELFStreamer::EmitInstToData(const MCInst &Inst,
SmallVector<MCFixup, 4> Fixups;
SmallString<256> Code;
raw_svector_ostream VecOS(Code);
Assembler.getEmitter().EncodeInstruction(Inst, VecOS, Fixups);
Assembler.getEmitter().EncodeInstruction(Inst, VecOS, Fixups, STI);
VecOS.flush();
for (unsigned i = 0, e = Fixups.size(); i != e; ++i)

2
lib/MC/MCMachOStreamer.cpp
View File

@ -371,7 +371,7 @@ void MCMachOStreamer::EmitInstToData(const MCInst &Inst,
SmallVector<MCFixup, 4> Fixups;
SmallString<256> Code;
raw_svector_ostream VecOS(Code);
getAssembler().getEmitter().EncodeInstruction(Inst, VecOS, Fixups);
getAssembler().getEmitter().EncodeInstruction(Inst, VecOS, Fixups, STI);
VecOS.flush();
// Add the fixups and data.

3
lib/MC/MCObjectStreamer.cpp
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@ -235,7 +235,8 @@ void MCObjectStreamer::EmitInstToFragment(const MCInst &Inst,
SmallString<128> Code;
raw_svector_ostream VecOS(Code);
getAssembler().getEmitter().EncodeInstruction(Inst, VecOS, IF->getFixups());
getAssembler().getEmitter().EncodeInstruction(Inst, VecOS, IF->getFixups(),
STI);
VecOS.flush();
IF->getContents().append(Code.begin(), Code.end());
}

4
lib/MC/MCPureStreamer.cpp
View File

@ -191,7 +191,7 @@ void MCPureStreamer::EmitInstToFragment(const MCInst &Inst,
SmallVector<MCFixup, 4> Fixups;
SmallString<256> Code;
raw_svector_ostream VecOS(Code);
getAssembler().getEmitter().EncodeInstruction(Inst, VecOS, Fixups);
getAssembler().getEmitter().EncodeInstruction(Inst, VecOS, Fixups, STI);
VecOS.flush();
IF->getContents() = Code;
@ -205,7 +205,7 @@ void MCPureStreamer::EmitInstToData(const MCInst &Inst,
SmallVector<MCFixup, 4> Fixups;
SmallString<256> Code;
raw_svector_ostream VecOS(Code);
getAssembler().getEmitter().EncodeInstruction(Inst, VecOS, Fixups);
getAssembler().getEmitter().EncodeInstruction(Inst, VecOS, Fixups, STI);
VecOS.flush();
// Add the fixups and data.

2
lib/MC/WinCOFFStreamer.cpp
View File

@ -84,7 +84,7 @@ private:
SmallVector<MCFixup, 4> Fixups;
SmallString<256> Code;
raw_svector_ostream VecOS(Code);
getAssembler().getEmitter().EncodeInstruction(Inst, VecOS, Fixups);
getAssembler().getEmitter().EncodeInstruction(Inst, VecOS, Fixups, STI);
VecOS.flush();
// Add the fixups and data.

6
lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
View File

@ -121,7 +121,8 @@ public:
void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups) const;
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
template<int hasRs, int hasRt2> unsigned
fixLoadStoreExclusive(const MCInst &MI, unsigned EncodedValue) const;
@ -545,7 +546,8 @@ MCCodeEmitter *llvm::createAArch64MCCodeEmitter(const MCInstrInfo &MCII,
void AArch64MCCodeEmitter::
EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups) const {
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
if (MI.getOpcode() == AArch64::TLSDESCCALL) {
// This is a directive which applies an R_AARCH64_TLSDESC_CALL to the
// following (BLR) instruction. It doesn't emit any code itself so it

6
lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
View File

@ -334,7 +334,8 @@ public:
}
void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups) const;
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
};
} // end anonymous namespace
@ -1539,7 +1540,8 @@ getShiftRight64Imm(const MCInst &MI, unsigned Op,
void ARMMCCodeEmitter::
EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups) const {
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
// Pseudo instructions don't get encoded.
const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
uint64_t TSFlags = Desc.TSFlags;

6
lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
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@ -71,7 +71,8 @@ public:
}
void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups) const;
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
// getBinaryCodeForInstr - TableGen'erated function for getting the
// binary encoding for an instruction.
@ -215,7 +216,8 @@ static void LowerDextDins(MCInst& InstIn) {
/// Size the instruction with Desc.getSize().
void MipsMCCodeEmitter::
EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups) const
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const
{
// Non-pseudo instructions that get changed for direct object

3
lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
View File

@ -76,7 +76,8 @@ public:
uint64_t getBinaryCodeForInstr(const MCInst &MI,
SmallVectorImpl<MCFixup> &Fixups) const;
void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups) const {
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
// For fast-isel, a float COPY_TO_REGCLASS can survive this long.
// It's just a nop to keep the register classes happy, so don't
// generate anything.

3
lib/Target/R600/AMDGPUMCInstLower.cpp
View File

@ -99,7 +99,8 @@ void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) {
MCObjectStreamer &ObjStreamer = (MCObjectStreamer &)OutStreamer;
MCCodeEmitter &InstEmitter = ObjStreamer.getAssembler().getEmitter();
InstEmitter.EncodeInstruction(TmpInst, CodeStream, Fixups);
InstEmitter.EncodeInstruction(TmpInst, CodeStream, Fixups,
TM.getSubtarget<MCSubtargetInfo>());
CodeStream.flush();
HexLines.resize(HexLines.size() + 1);

6
lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp
View File

@ -44,7 +44,8 @@ public:
/// \brief Encode the instruction and write it to the OS.
virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups) const;
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
/// \returns the encoding for an MCOperand.
virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
@ -87,7 +88,8 @@ MCCodeEmitter *llvm::createR600MCCodeEmitter(const MCInstrInfo &MCII,
}
void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups) const {
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
if (MI.getOpcode() == AMDGPU::RETURN ||
MI.getOpcode() == AMDGPU::FETCH_CLAUSE ||

6
lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp
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@ -55,7 +55,8 @@ public:
/// \brief Encode the instruction and write it to the OS.
virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups) const;
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
/// \returns the encoding for an MCOperand.
virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
@ -125,7 +126,8 @@ uint32_t SIMCCodeEmitter::getLitEncoding(const MCOperand &MO) const {
}
void SIMCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups) const {
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
uint64_t Encoding = getBinaryCodeForInstr(MI, Fixups);
const MCInstrDesc &Desc = MCII.get(MI.getOpcode());

6
lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp
View File

@ -39,7 +39,8 @@ public:
~SparcMCCodeEmitter() {}
void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups) const;
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
// getBinaryCodeForInstr - TableGen'erated function for getting the
// binary encoding for an instruction.
@ -68,7 +69,8 @@ MCCodeEmitter *llvm::createSparcMCCodeEmitter(const MCInstrInfo &MCII,
void SparcMCCodeEmitter::
EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups) const {
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
unsigned Bits = getBinaryCodeForInstr(MI, Fixups);
// Output the constant in big endian byte order.

6
lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp
View File

@ -35,7 +35,8 @@ public:
// OVerride MCCodeEmitter.
virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups) const
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const
LLVM_OVERRIDE;
private:
@ -91,7 +92,8 @@ MCCodeEmitter *llvm::createSystemZMCCodeEmitter(const MCInstrInfo &MCII,
void SystemZMCCodeEmitter::
EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups) const {
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
uint64_t Bits = getBinaryCodeForInstr(MI, Fixups);
unsigned Size = MCII.get(MI.getOpcode()).getSize();
// Big-endian insertion of Size bytes.

6
lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
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@ -152,7 +152,8 @@ public:
SmallVectorImpl<MCFixup> &Fixups) const;
void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups) const;
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
const MCInst &MI, const MCInstrDesc &Desc,
@ -1268,7 +1269,8 @@ void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
void X86MCCodeEmitter::
EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups) const {
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
unsigned Opcode = MI.getOpcode();
const MCInstrDesc &Desc = MCII.get(Opcode);
uint64_t TSFlags = Desc.TSFlags;