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GlobalISel: Make type for lower action more consistently optional
Some of the lower implementations were relying on this, however the type was not set depending on which form .lower* helper form you were using. For instance, if you used an unconditonal lower(), the type was never set. Most of the lower actions do not benefit from a type parameter, and just expand in terms of the original operation's types. However, some lowerings could benefit from an additional type hint to combine a promotion and an expansion. An example of this is for add/sub sat. The DAG integer legalization tries to use smarter expansions directly when promoting the integer type, and doesn't always produce the same instruction with a wider type. Treat this as an optional hint argument, that only means something for specific lower actions. It may be useful to generalize this mechanism to pass a full list of type indexes and desired types, but I haven't run into a case like that yet.
This commit is contained in:
Matt Arsenault
parent
78cee19819
commit
4a4ddffaf1
@ -176,10 +176,12 @@ few actions in common:
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elements in one of the types to a specific type would make it more legal.
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This action supports vectors.
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* ``lowerIf()``, ``lowerFor()``, etc. declare an instruction to be illegal if the
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predicate is satisfied and indicates that replacing it with equivalent
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instruction(s) would make it more legal. Support for this action differs for
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each opcode.
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* ``lowerIf()``, ``lowerFor()``, etc. declare an instruction to be
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illegal if the predicate is satisfied and indicates that replacing
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it with equivalent instruction(s) would make it more legal. Support
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for this action differs for each opcode. These may provide an
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optional LegalizeMutation containing a type to attempt to perform
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the expansion in a different type.
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* ``libcallIf()``, ``libcallFor()``, etc. declare an instruction to be illegal if the
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predicate is satisfied and indicates that replacing it with a libcall would
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@ -325,20 +325,20 @@ public:
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LegalizeResult lowerBitcast(MachineInstr &MI);
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LegalizeResult lowerLoad(MachineInstr &MI);
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LegalizeResult lowerStore(MachineInstr &MI);
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LegalizeResult lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
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LegalizeResult lowerBitCount(MachineInstr &MI);
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LegalizeResult lowerU64ToF32BitOps(MachineInstr &MI);
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LegalizeResult lowerUITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
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LegalizeResult lowerSITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
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LegalizeResult lowerFPTOUI(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
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LegalizeResult lowerUITOFP(MachineInstr &MI);
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LegalizeResult lowerSITOFP(MachineInstr &MI);
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LegalizeResult lowerFPTOUI(MachineInstr &MI);
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LegalizeResult lowerFPTOSI(MachineInstr &MI);
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LegalizeResult lowerFPTRUNC_F64_TO_F16(MachineInstr &MI);
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LegalizeResult lowerFPTRUNC(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
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LegalizeResult lowerFPTRUNC(MachineInstr &MI);
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LegalizeResult lowerFPOWI(MachineInstr &MI);
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LegalizeResult lowerMinMax(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
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LegalizeResult lowerFCopySign(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
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LegalizeResult lowerMinMax(MachineInstr &MI);
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LegalizeResult lowerFCopySign(MachineInstr &MI);
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LegalizeResult lowerFMinNumMaxNum(MachineInstr &MI);
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LegalizeResult lowerFMad(MachineInstr &MI);
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LegalizeResult lowerIntrinsicRound(MachineInstr &MI);
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@ -629,8 +629,7 @@ public:
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/// The instruction is lowered when type index 0 is any type in the given
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/// list. Keep type index 0 as the same type.
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LegalizeRuleSet &lowerFor(std::initializer_list<LLT> Types) {
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return actionFor(LegalizeAction::Lower, Types,
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LegalizeMutations::changeTo(0, 0));
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return actionFor(LegalizeAction::Lower, Types);
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}
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/// The instruction is lowered when type index 0 is any type in the given
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/// list.
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@ -641,8 +640,7 @@ public:
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/// The instruction is lowered when type indexes 0 and 1 is any type pair in
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/// the given list. Keep type index 0 as the same type.
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LegalizeRuleSet &lowerFor(std::initializer_list<std::pair<LLT, LLT>> Types) {
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return actionFor(LegalizeAction::Lower, Types,
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LegalizeMutations::changeTo(0, 0));
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return actionFor(LegalizeAction::Lower, Types);
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}
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/// The instruction is lowered when type indexes 0 and 1 is any type pair in
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/// the given list.
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@ -2804,7 +2804,7 @@ void LegalizerHelper::changeOpcode(MachineInstr &MI, unsigned NewOpcode) {
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}
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LegalizerHelper::LegalizeResult
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LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
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LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT LowerHintTy) {
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using namespace TargetOpcode;
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switch(MI.getOpcode()) {
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@ -2814,6 +2814,7 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
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return lowerBitcast(MI);
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case TargetOpcode::G_SREM:
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case TargetOpcode::G_UREM: {
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LLT Ty = MRI.getType(MI.getOperand(0).getReg());
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auto Quot =
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MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV, {Ty},
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{MI.getOperand(1), MI.getOperand(2)});
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@ -2834,6 +2835,7 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
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Register Overflow = MI.getOperand(1).getReg();
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Register LHS = MI.getOperand(2).getReg();
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Register RHS = MI.getOperand(3).getReg();
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LLT Ty = MRI.getType(Res);
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unsigned Opcode = MI.getOpcode() == TargetOpcode::G_SMULO
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? TargetOpcode::G_SMULH
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@ -2862,11 +2864,13 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
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return Legalized;
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}
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case TargetOpcode::G_FNEG: {
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Register Res = MI.getOperand(0).getReg();
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LLT Ty = MRI.getType(Res);
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// TODO: Handle vector types once we are able to
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// represent them.
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if (Ty.isVector())
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return UnableToLegalize;
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Register Res = MI.getOperand(0).getReg();
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LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
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Type *ZeroTy = getFloatTypeForLLT(Ctx, Ty);
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if (!ZeroTy)
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@ -2881,12 +2885,14 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
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return Legalized;
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}
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case TargetOpcode::G_FSUB: {
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Register Res = MI.getOperand(0).getReg();
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LLT Ty = MRI.getType(Res);
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// Lower (G_FSUB LHS, RHS) to (G_FADD LHS, (G_FNEG RHS)).
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// First, check if G_FNEG is marked as Lower. If so, we may
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// end up with an infinite loop as G_FSUB is used to legalize G_FNEG.
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if (LI.getAction({G_FNEG, {Ty}}).Action == Lower)
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return UnableToLegalize;
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Register Res = MI.getOperand(0).getReg();
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Register LHS = MI.getOperand(1).getReg();
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Register RHS = MI.getOperand(2).getReg();
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Register Neg = MRI.createGenericVirtualRegister(Ty);
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@ -2930,7 +2936,7 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
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case TargetOpcode::G_CTLZ:
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case TargetOpcode::G_CTTZ:
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case TargetOpcode::G_CTPOP:
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return lowerBitCount(MI, TypeIdx, Ty);
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return lowerBitCount(MI);
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case G_UADDO: {
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Register Res = MI.getOperand(0).getReg();
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Register CarryOut = MI.getOperand(1).getReg();
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@ -2992,24 +2998,24 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
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return Legalized;
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}
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case G_UITOFP:
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return lowerUITOFP(MI, TypeIdx, Ty);
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return lowerUITOFP(MI);
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case G_SITOFP:
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return lowerSITOFP(MI, TypeIdx, Ty);
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return lowerSITOFP(MI);
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case G_FPTOUI:
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return lowerFPTOUI(MI, TypeIdx, Ty);
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return lowerFPTOUI(MI);
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case G_FPTOSI:
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return lowerFPTOSI(MI);
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case G_FPTRUNC:
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return lowerFPTRUNC(MI, TypeIdx, Ty);
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return lowerFPTRUNC(MI);
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case G_FPOWI:
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return lowerFPOWI(MI);
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case G_SMIN:
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case G_SMAX:
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case G_UMIN:
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case G_UMAX:
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return lowerMinMax(MI, TypeIdx, Ty);
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return lowerMinMax(MI);
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case G_FCOPYSIGN:
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return lowerFCopySign(MI, TypeIdx, Ty);
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return lowerFCopySign(MI);
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case G_FMINNUM:
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case G_FMAXNUM:
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return lowerFMinNumMaxNum(MI);
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@ -4758,7 +4764,7 @@ LegalizerHelper::narrowScalarCTPOP(MachineInstr &MI, unsigned TypeIdx,
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}
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LegalizerHelper::LegalizeResult
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LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
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LegalizerHelper::lowerBitCount(MachineInstr &MI) {
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unsigned Opc = MI.getOpcode();
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const auto &TII = MIRBuilder.getTII();
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auto isSupported = [this](const LegalityQuery &Q) {
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@ -4848,15 +4854,15 @@ LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
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// unless the target has ctlz but not ctpop, in which case we use:
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// { return 32 - nlz(~x & (x-1)); }
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// Ref: "Hacker's Delight" by Henry Warren
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auto MIBCstNeg1 = MIRBuilder.buildConstant(Ty, -1);
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auto MIBNot = MIRBuilder.buildXor(Ty, SrcReg, MIBCstNeg1);
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auto MIBCstNeg1 = MIRBuilder.buildConstant(SrcTy, -1);
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auto MIBNot = MIRBuilder.buildXor(SrcTy, SrcReg, MIBCstNeg1);
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auto MIBTmp = MIRBuilder.buildAnd(
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Ty, MIBNot, MIRBuilder.buildAdd(Ty, SrcReg, MIBCstNeg1));
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if (!isSupported({TargetOpcode::G_CTPOP, {Ty, Ty}}) &&
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isSupported({TargetOpcode::G_CTLZ, {Ty, Ty}})) {
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auto MIBCstLen = MIRBuilder.buildConstant(Ty, Len);
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SrcTy, MIBNot, MIRBuilder.buildAdd(SrcTy, SrcReg, MIBCstNeg1));
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if (!isSupported({TargetOpcode::G_CTPOP, {SrcTy, SrcTy}}) &&
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isSupported({TargetOpcode::G_CTLZ, {SrcTy, SrcTy}})) {
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auto MIBCstLen = MIRBuilder.buildConstant(SrcTy, Len);
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MIRBuilder.buildSub(MI.getOperand(0), MIBCstLen,
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MIRBuilder.buildCTLZ(Ty, MIBTmp));
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MIRBuilder.buildCTLZ(SrcTy, MIBTmp));
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MI.eraseFromParent();
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return Legalized;
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}
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@ -4865,6 +4871,8 @@ LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
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return Legalized;
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}
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case TargetOpcode::G_CTPOP: {
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Register SrcReg = MI.getOperand(1).getReg();
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LLT Ty = MRI.getType(SrcReg);
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unsigned Size = Ty.getSizeInBits();
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MachineIRBuilder &B = MIRBuilder;
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@ -4874,11 +4882,11 @@ LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
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// B2Count = val - { (val >> 1) & 0x55555555 }
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// since it gives same result in blocks of 2 with one instruction less.
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auto C_1 = B.buildConstant(Ty, 1);
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auto B2Set1LoTo1Hi = B.buildLShr(Ty, MI.getOperand(1).getReg(), C_1);
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auto B2Set1LoTo1Hi = B.buildLShr(Ty, SrcReg, C_1);
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APInt B2Mask1HiTo0 = APInt::getSplat(Size, APInt(8, 0x55));
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auto C_B2Mask1HiTo0 = B.buildConstant(Ty, B2Mask1HiTo0);
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auto B2Count1Hi = B.buildAnd(Ty, B2Set1LoTo1Hi, C_B2Mask1HiTo0);
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auto B2Count = B.buildSub(Ty, MI.getOperand(1).getReg(), B2Count1Hi);
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auto B2Count = B.buildSub(Ty, SrcReg, B2Count1Hi);
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// In order to get count in blocks of 4 add values from adjacent block of 2.
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// B4Count = { B2Count & 0x33333333 } + { (B2Count >> 2) & 0x33333333 }
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@ -4977,8 +4985,7 @@ LegalizerHelper::lowerU64ToF32BitOps(MachineInstr &MI) {
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return Legalized;
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}
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LegalizerHelper::LegalizeResult
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LegalizerHelper::lowerUITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
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LegalizerHelper::LegalizeResult LegalizerHelper::lowerUITOFP(MachineInstr &MI) {
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Register Dst = MI.getOperand(0).getReg();
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Register Src = MI.getOperand(1).getReg();
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LLT DstTy = MRI.getType(Dst);
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@ -5006,8 +5013,7 @@ LegalizerHelper::lowerUITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
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return UnableToLegalize;
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}
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LegalizerHelper::LegalizeResult
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LegalizerHelper::lowerSITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
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LegalizerHelper::LegalizeResult LegalizerHelper::lowerSITOFP(MachineInstr &MI) {
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Register Dst = MI.getOperand(0).getReg();
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Register Src = MI.getOperand(1).getReg();
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LLT DstTy = MRI.getType(Dst);
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@ -5053,8 +5059,7 @@ LegalizerHelper::lowerSITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
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return UnableToLegalize;
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}
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LegalizerHelper::LegalizeResult
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LegalizerHelper::lowerFPTOUI(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
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LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPTOUI(MachineInstr &MI) {
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Register Dst = MI.getOperand(0).getReg();
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Register Src = MI.getOperand(1).getReg();
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LLT DstTy = MRI.getType(Dst);
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@ -5271,7 +5276,7 @@ LegalizerHelper::lowerFPTRUNC_F64_TO_F16(MachineInstr &MI) {
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}
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LegalizerHelper::LegalizeResult
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LegalizerHelper::lowerFPTRUNC(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
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LegalizerHelper::lowerFPTRUNC(MachineInstr &MI) {
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Register Dst = MI.getOperand(0).getReg();
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Register Src = MI.getOperand(1).getReg();
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@ -5315,8 +5320,7 @@ static CmpInst::Predicate minMaxToCompare(unsigned Opc) {
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}
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}
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LegalizerHelper::LegalizeResult
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LegalizerHelper::lowerMinMax(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
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LegalizerHelper::LegalizeResult LegalizerHelper::lowerMinMax(MachineInstr &MI) {
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Register Dst = MI.getOperand(0).getReg();
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Register Src0 = MI.getOperand(1).getReg();
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Register Src1 = MI.getOperand(2).getReg();
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@ -5332,7 +5336,7 @@ LegalizerHelper::lowerMinMax(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
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}
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LegalizerHelper::LegalizeResult
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LegalizerHelper::lowerFCopySign(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
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LegalizerHelper::lowerFCopySign(MachineInstr &MI) {
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Register Dst = MI.getOperand(0).getReg();
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Register Src0 = MI.getOperand(1).getReg();
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Register Src1 = MI.getOperand(2).getReg();
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