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X86, AArch64, ARM: Do not attach debug location to spill/reload instructions

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This rebases and recommits r343520. hwasan should be fixed now and this
shouldn't break the tests anymore.

Spill/reload instructions are artificially generated by the compiler and
have no relation to the original source code. So the best thing to do is
not attach any debug location to them (instead of just taking the next
debug location we find on following instructions).

Differential Revision: https://reviews.llvm.org/D52125

llvm-svn: 343895
This commit is contained in:
Matthias Braun 2018-10-05 22:00:13 +00:00
parent 896477513b
commit 4acd274986
5 changed files with 22 additions and 29 deletions
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10
lib/Target/AArch64/AArch64InstrInfo.cpp
View File

@ -2771,9 +2771,6 @@ void AArch64InstrInfo::storeRegToStackSlot(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg,
bool isKill, int FI, const TargetRegisterClass *RC, bool isKill, int FI, const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const { const TargetRegisterInfo *TRI) const {
DebugLoc DL;
if (MBBI != MBB.end())
DL = MBBI->getDebugLoc();
MachineFunction &MF = *MBB.getParent(); MachineFunction &MF = *MBB.getParent();
MachineFrameInfo &MFI = MF.getFrameInfo(); MachineFrameInfo &MFI = MF.getFrameInfo();
unsigned Align = MFI.getObjectAlignment(FI); unsigned Align = MFI.getObjectAlignment(FI);
@ -2867,7 +2864,7 @@ void AArch64InstrInfo::storeRegToStackSlot(
} }
assert(Opc && "Unknown register class"); assert(Opc && "Unknown register class");
const MachineInstrBuilder MI = BuildMI(MBB, MBBI, DL, get(Opc)) const MachineInstrBuilder MI = BuildMI(MBB, MBBI, DebugLoc(), get(Opc))
.addReg(SrcReg, getKillRegState(isKill)) .addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI); .addFrameIndex(FI);
@ -2905,9 +2902,6 @@ void AArch64InstrInfo::loadRegFromStackSlot(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg,
int FI, const TargetRegisterClass *RC, int FI, const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const { const TargetRegisterInfo *TRI) const {
DebugLoc DL;
if (MBBI != MBB.end())
DL = MBBI->getDebugLoc();
MachineFunction &MF = *MBB.getParent(); MachineFunction &MF = *MBB.getParent();
MachineFrameInfo &MFI = MF.getFrameInfo(); MachineFrameInfo &MFI = MF.getFrameInfo();
unsigned Align = MFI.getObjectAlignment(FI); unsigned Align = MFI.getObjectAlignment(FI);
@ -3001,7 +2995,7 @@ void AArch64InstrInfo::loadRegFromStackSlot(
} }
assert(Opc && "Unknown register class"); assert(Opc && "Unknown register class");
const MachineInstrBuilder MI = BuildMI(MBB, MBBI, DL, get(Opc)) const MachineInstrBuilder MI = BuildMI(MBB, MBBI, DebugLoc(), get(Opc))
.addReg(DestReg, getDefRegState(true)) .addReg(DestReg, getDefRegState(true))
.addFrameIndex(FI); .addFrameIndex(FI);
if (Offset) if (Offset)

30
lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -971,8 +971,6 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned SrcReg, bool isKill, int FI, unsigned SrcReg, bool isKill, int FI,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const { const TargetRegisterInfo *TRI) const {
DebugLoc DL;
if (I != MBB.end()) DL = I->getDebugLoc();
MachineFunction &MF = *MBB.getParent(); MachineFunction &MF = *MBB.getParent();
MachineFrameInfo &MFI = MF.getFrameInfo(); MachineFrameInfo &MFI = MF.getFrameInfo();
unsigned Align = MFI.getObjectAlignment(FI); unsigned Align = MFI.getObjectAlignment(FI);
@ -984,7 +982,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
switch (TRI->getSpillSize(*RC)) { switch (TRI->getSpillSize(*RC)) {
case 2: case 2:
if (ARM::HPRRegClass.hasSubClassEq(RC)) { if (ARM::HPRRegClass.hasSubClassEq(RC)) {
BuildMI(MBB, I, DL, get(ARM::VSTRH)) BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRH))
.addReg(SrcReg, getKillRegState(isKill)) .addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI) .addFrameIndex(FI)
.addImm(0) .addImm(0)
@ -995,14 +993,14 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
break; break;
case 4: case 4:
if (ARM::GPRRegClass.hasSubClassEq(RC)) { if (ARM::GPRRegClass.hasSubClassEq(RC)) {
BuildMI(MBB, I, DL, get(ARM::STRi12)) BuildMI(MBB, I, DebugLoc(), get(ARM::STRi12))
.addReg(SrcReg, getKillRegState(isKill)) .addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI) .addFrameIndex(FI)
.addImm(0) .addImm(0)
.addMemOperand(MMO) .addMemOperand(MMO)
.add(predOps(ARMCC::AL)); .add(predOps(ARMCC::AL));
} else if (ARM::SPRRegClass.hasSubClassEq(RC)) { } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
BuildMI(MBB, I, DL, get(ARM::VSTRS)) BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRS))
.addReg(SrcReg, getKillRegState(isKill)) .addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI) .addFrameIndex(FI)
.addImm(0) .addImm(0)
@ -1013,7 +1011,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
break; break;
case 8: case 8:
if (ARM::DPRRegClass.hasSubClassEq(RC)) { if (ARM::DPRRegClass.hasSubClassEq(RC)) {
BuildMI(MBB, I, DL, get(ARM::VSTRD)) BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRD))
.addReg(SrcReg, getKillRegState(isKill)) .addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI) .addFrameIndex(FI)
.addImm(0) .addImm(0)
@ -1021,7 +1019,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
.add(predOps(ARMCC::AL)); .add(predOps(ARMCC::AL));
} else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
if (Subtarget.hasV5TEOps()) { if (Subtarget.hasV5TEOps()) {
MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STRD)); MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STRD));
AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI); AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO) MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)
@ -1029,7 +1027,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
} else { } else {
// Fallback to STM instruction, which has existed since the dawn of // Fallback to STM instruction, which has existed since the dawn of
// time. // time.
MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STMIA)) MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STMIA))
.addFrameIndex(FI) .addFrameIndex(FI)
.addMemOperand(MMO) .addMemOperand(MMO)
.add(predOps(ARMCC::AL)); .add(predOps(ARMCC::AL));
@ -1043,14 +1041,14 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
if (ARM::DPairRegClass.hasSubClassEq(RC)) { if (ARM::DPairRegClass.hasSubClassEq(RC)) {
// Use aligned spills if the stack can be realigned. // Use aligned spills if the stack can be realigned.
if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
BuildMI(MBB, I, DL, get(ARM::VST1q64)) BuildMI(MBB, I, DebugLoc(), get(ARM::VST1q64))
.addFrameIndex(FI) .addFrameIndex(FI)
.addImm(16) .addImm(16)
.addReg(SrcReg, getKillRegState(isKill)) .addReg(SrcReg, getKillRegState(isKill))
.addMemOperand(MMO) .addMemOperand(MMO)
.add(predOps(ARMCC::AL)); .add(predOps(ARMCC::AL));
} else { } else {
BuildMI(MBB, I, DL, get(ARM::VSTMQIA)) BuildMI(MBB, I, DebugLoc(), get(ARM::VSTMQIA))
.addReg(SrcReg, getKillRegState(isKill)) .addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI) .addFrameIndex(FI)
.addMemOperand(MMO) .addMemOperand(MMO)
@ -1063,14 +1061,15 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
if (ARM::DTripleRegClass.hasSubClassEq(RC)) { if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
// Use aligned spills if the stack can be realigned. // Use aligned spills if the stack can be realigned.
if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
BuildMI(MBB, I, DL, get(ARM::VST1d64TPseudo)) BuildMI(MBB, I, DebugLoc(), get(ARM::VST1d64TPseudo))
.addFrameIndex(FI) .addFrameIndex(FI)
.addImm(16) .addImm(16)
.addReg(SrcReg, getKillRegState(isKill)) .addReg(SrcReg, getKillRegState(isKill))
.addMemOperand(MMO) .addMemOperand(MMO)
.add(predOps(ARMCC::AL)); .add(predOps(ARMCC::AL));
} else { } else {
MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(),
get(ARM::VSTMDIA))
.addFrameIndex(FI) .addFrameIndex(FI)
.add(predOps(ARMCC::AL)) .add(predOps(ARMCC::AL))
.addMemOperand(MMO); .addMemOperand(MMO);
@ -1086,14 +1085,15 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
// FIXME: It's possible to only store part of the QQ register if the // FIXME: It's possible to only store part of the QQ register if the
// spilled def has a sub-register index. // spilled def has a sub-register index.
BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo)) BuildMI(MBB, I, DebugLoc(), get(ARM::VST1d64QPseudo))
.addFrameIndex(FI) .addFrameIndex(FI)
.addImm(16) .addImm(16)
.addReg(SrcReg, getKillRegState(isKill)) .addReg(SrcReg, getKillRegState(isKill))
.addMemOperand(MMO) .addMemOperand(MMO)
.add(predOps(ARMCC::AL)); .add(predOps(ARMCC::AL));
} else { } else {
MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(),
get(ARM::VSTMDIA))
.addFrameIndex(FI) .addFrameIndex(FI)
.add(predOps(ARMCC::AL)) .add(predOps(ARMCC::AL))
.addMemOperand(MMO); .addMemOperand(MMO);
@ -1107,7 +1107,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
break; break;
case 64: case 64:
if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::VSTMDIA))
.addFrameIndex(FI) .addFrameIndex(FI)
.add(predOps(ARMCC::AL)) .add(predOps(ARMCC::AL))
.addMemOperand(MMO); .addMemOperand(MMO);

6
lib/Target/X86/X86InstrInfo.cpp
View File

@ -3313,8 +3313,7 @@ void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
(Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) || (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
RI.canRealignStack(MF); RI.canRealignStack(MF);
unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget); unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
DebugLoc DL = MBB.findDebugLoc(MI); addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc)), FrameIdx)
addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
.addReg(SrcReg, getKillRegState(isKill)); .addReg(SrcReg, getKillRegState(isKill));
} }
@ -3348,8 +3347,7 @@ void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
(Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) || (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
RI.canRealignStack(MF); RI.canRealignStack(MF);
unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget); unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
DebugLoc DL = MBB.findDebugLoc(MI); addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc), DestReg), FrameIdx);
addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
} }
void X86InstrInfo::loadRegFromAddr( void X86InstrInfo::loadRegFromAddr(

2
test/DebugInfo/X86/fission-ranges.ll
View File

@ -55,7 +55,7 @@
; V5RNGLISTS-NOT: DW_TAG ; V5RNGLISTS-NOT: DW_TAG
; V5RNGLISTS: DW_AT_rnglists_base [DW_FORM_sec_offset] (0x0000000c) ; V5RNGLISTS: DW_AT_rnglists_base [DW_FORM_sec_offset] (0x0000000c)
; V5RNGLISTS: .debug_rnglists contents: ; V5RNGLISTS: .debug_rnglists contents:
; V5RNGLISTS-NEXT: 0x00000000: range list header: length = 0x00000014, version = 0x0005, ; V5RNGLISTS-NEXT: 0x00000000: range list header: length = 0x00000015, version = 0x0005,
; V5RNGLISTS-SAME: addr_size = 0x08, seg_size = 0x00, offset_entry_count = 0x00000000 ; V5RNGLISTS-SAME: addr_size = 0x08, seg_size = 0x00, offset_entry_count = 0x00000000
; V5RNGLISTS-NEXT: ranges: ; V5RNGLISTS-NEXT: ranges:
; V5RNGLISTS-NEXT: 0x0000000c: [DW_RLE_offset_pair]: ; V5RNGLISTS-NEXT: 0x0000000c: [DW_RLE_offset_pair]:

3
test/DebugInfo/X86/parameters.ll
View File

@ -28,7 +28,8 @@
; CHECK: DW_TAG_subprogram ; CHECK: DW_TAG_subprogram
; CHECK: DW_AT_name{{.*}} = "func" ; CHECK: DW_AT_name{{.*}} = "func"
; CHECK: DW_TAG_formal_parameter ; CHECK: DW_TAG_formal_parameter
; CHECK: DW_AT_location {{.*}} (DW_OP_breg4 RSI+0, DW_OP_deref) ; CHECK: DW_AT_location {{.*}}
; CHECK-NEXT: DW_OP_breg4 RSI+0, DW_OP_deref
; CHECK-NOT: DW_TAG ; CHECK-NOT: DW_TAG
; CHECK: DW_AT_name{{.*}} = "f" ; CHECK: DW_AT_name{{.*}} = "f"