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[ARM] Transforming memcpy to Tail predicated Loop
This patch converts llvm.memcpy intrinsic into Tail Predicated Hardware loops for a target that supports the Arm M-profile Vector Extension (MVE). From an implementation point of view, the patch - adds an ARM specific SDAG Node (to which the llvm.memcpy intrinsic is lowered to, during first phase of ISel) - adds a corresponding TableGen entry to generate a pseudo instruction, with a custom inserter, on matching the above node. - Adds a custom inserter function that expands the pseudo instruction into MIR suitable to be (by later passes) into a WLSTP loop. Reviewed By: dmgreen Differential Revision: https://reviews.llvm.org/D99723
This commit is contained in:
Malhar Jajoo
parent
6e72fd82c1
commit
4adadbc511
@ -1802,6 +1802,7 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
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MAKE_CASE(ARMISD::CSINV)
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MAKE_CASE(ARMISD::CSNEG)
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MAKE_CASE(ARMISD::CSINC)
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MAKE_CASE(ARMISD::MEMCPYLOOP)
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#undef MAKE_CASE
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}
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return nullptr;
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@ -11097,6 +11098,141 @@ static bool checkAndUpdateCPSRKill(MachineBasicBlock::iterator SelectItr,
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return true;
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}
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/// Adds logic in loop entry MBB to calculate loop iteration count and adds
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/// t2WhileLoopSetup and t2WhileLoopStart to generate WLS loop
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static Register genTPEntry(MachineBasicBlock *TpEntry,
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MachineBasicBlock *TpLoopBody,
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MachineBasicBlock *TpExit, Register OpSizeReg,
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const TargetInstrInfo *TII, DebugLoc Dl,
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MachineRegisterInfo &MRI) {
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// Calculates loop iteration count = ceil(n/16)/16 = ((n + 15)&(-16)) / 16.
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Register AddDestReg = MRI.createVirtualRegister(&ARM::rGPRRegClass);
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BuildMI(TpEntry, Dl, TII->get(ARM::t2ADDri), AddDestReg)
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.addUse(OpSizeReg)
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.addImm(15)
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.add(predOps(ARMCC::AL))
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.addReg(0);
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Register BicDestReg = MRI.createVirtualRegister(&ARM::rGPRRegClass);
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BuildMI(TpEntry, Dl, TII->get(ARM::t2BICri), BicDestReg)
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.addUse(AddDestReg, RegState::Kill)
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.addImm(16)
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.add(predOps(ARMCC::AL))
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.addReg(0);
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Register LsrDestReg = MRI.createVirtualRegister(&ARM::GPRlrRegClass);
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BuildMI(TpEntry, Dl, TII->get(ARM::t2LSRri), LsrDestReg)
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.addUse(BicDestReg, RegState::Kill)
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.addImm(4)
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.add(predOps(ARMCC::AL))
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.addReg(0);
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Register TotalIterationsReg = MRI.createVirtualRegister(&ARM::GPRlrRegClass);
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BuildMI(TpEntry, Dl, TII->get(ARM::t2WhileLoopSetup), TotalIterationsReg)
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.addUse(LsrDestReg, RegState::Kill);
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BuildMI(TpEntry, Dl, TII->get(ARM::t2WhileLoopStart))
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.addUse(TotalIterationsReg)
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.addMBB(TpExit);
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return TotalIterationsReg;
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}
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/// Adds logic in the loopBody MBB to generate MVE_VCTP, t2DoLoopDec and
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/// t2DoLoopEnd. These are used by later passes to generate tail predicated
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/// loops.
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static void genTPLoopBody(MachineBasicBlock *TpLoopBody,
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MachineBasicBlock *TpEntry, MachineBasicBlock *TpExit,
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const TargetInstrInfo *TII, DebugLoc Dl,
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MachineRegisterInfo &MRI, Register OpSrcReg,
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Register OpDestReg, Register ElementCountReg,
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Register TotalIterationsReg) {
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// First insert 4 PHI nodes for: Current pointer to Src, Dest array, loop
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// iteration counter, predication counter Current position in the src array
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Register SrcPhiReg = MRI.createVirtualRegister(&ARM::rGPRRegClass);
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Register CurrSrcReg = MRI.createVirtualRegister(&ARM::rGPRRegClass);
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BuildMI(TpLoopBody, Dl, TII->get(ARM::PHI), SrcPhiReg)
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.addUse(OpSrcReg)
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.addMBB(TpEntry)
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.addUse(CurrSrcReg)
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.addMBB(TpLoopBody);
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// Current position in the dest array
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Register DestPhiReg = MRI.createVirtualRegister(&ARM::rGPRRegClass);
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Register CurrDestReg = MRI.createVirtualRegister(&ARM::rGPRRegClass);
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BuildMI(TpLoopBody, Dl, TII->get(ARM::PHI), DestPhiReg)
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.addUse(OpDestReg)
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.addMBB(TpEntry)
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.addUse(CurrDestReg)
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.addMBB(TpLoopBody);
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// Current loop counter
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Register LoopCounterPhiReg = MRI.createVirtualRegister(&ARM::GPRlrRegClass);
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Register RemainingLoopIterationsReg =
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MRI.createVirtualRegister(&ARM::GPRlrRegClass);
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BuildMI(TpLoopBody, Dl, TII->get(ARM::PHI), LoopCounterPhiReg)
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.addUse(TotalIterationsReg)
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.addMBB(TpEntry)
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.addUse(RemainingLoopIterationsReg)
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.addMBB(TpLoopBody);
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// Predication counter
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Register PredCounterPhiReg = MRI.createVirtualRegister(&ARM::rGPRRegClass);
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Register RemainingElementsReg = MRI.createVirtualRegister(&ARM::rGPRRegClass);
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BuildMI(TpLoopBody, Dl, TII->get(ARM::PHI), PredCounterPhiReg)
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.addUse(ElementCountReg)
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.addMBB(TpEntry)
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.addUse(RemainingElementsReg)
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.addMBB(TpLoopBody);
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// Pass predication counter to VCTP
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Register VccrReg = MRI.createVirtualRegister(&ARM::VCCRRegClass);
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BuildMI(TpLoopBody, Dl, TII->get(ARM::MVE_VCTP8), VccrReg)
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.addUse(PredCounterPhiReg)
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.addImm(ARMVCC::None)
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.addReg(0);
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BuildMI(TpLoopBody, Dl, TII->get(ARM::t2SUBri), RemainingElementsReg)
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.addUse(PredCounterPhiReg)
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.addImm(16)
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.add(predOps(ARMCC::AL))
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.addReg(0);
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// VLDRB and VSTRB instructions, predicated using VPR
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Register LoadedValueReg = MRI.createVirtualRegister(&ARM::MQPRRegClass);
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BuildMI(TpLoopBody, Dl, TII->get(ARM::MVE_VLDRBU8_post))
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.addDef(CurrSrcReg)
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.addDef(LoadedValueReg)
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.addReg(SrcPhiReg)
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.addImm(16)
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.addImm(ARMVCC::Then)
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.addUse(VccrReg);
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BuildMI(TpLoopBody, Dl, TII->get(ARM::MVE_VSTRBU8_post))
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.addDef(CurrDestReg)
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.addUse(LoadedValueReg, RegState::Kill)
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.addReg(DestPhiReg)
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.addImm(16)
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.addImm(ARMVCC::Then)
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.addUse(VccrReg);
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// Add the pseudoInstrs for decrementing the loop counter and marking the
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// end:t2DoLoopDec and t2DoLoopEnd
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BuildMI(TpLoopBody, Dl, TII->get(ARM::t2LoopDec), RemainingLoopIterationsReg)
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.addUse(LoopCounterPhiReg)
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.addImm(1);
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BuildMI(TpLoopBody, Dl, TII->get(ARM::t2LoopEnd))
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.addUse(RemainingLoopIterationsReg)
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.addMBB(TpLoopBody);
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BuildMI(TpLoopBody, Dl, TII->get(ARM::t2B))
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.addMBB(TpExit)
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.add(predOps(ARMCC::AL));
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}
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MachineBasicBlock *
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ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
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MachineBasicBlock *BB) const {
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@ -11123,6 +11259,95 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
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return BB;
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}
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case ARM::MVE_MEMCPYLOOPINST: {
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// Transformation below expands MVE_MEMCPYLOOPINST Pseudo instruction
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// into a Tail Predicated (TP) Loop. It adds the instructions to calculate
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// the iteration count =ceil(size_in_bytes/16)) in the TP entry block and
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// adds the relevant instructions in the TP loop Body for generation of a
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// WLSTP loop.
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// Below is relevant portion of the CFG after the transformation.
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// The Machine Basic Blocks are shown along with branch conditions (in
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// brackets). Note that TP entry/exit MBBs depict the entry/exit of this
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// portion of the CFG and may not necessarily be the entry/exit of the
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// function.
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// (Relevant) CFG after transformation:
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// TP entry MBB
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// |
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// |-----------------|
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// (n <= 0) (n > 0)
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// | |
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// | TP loop Body MBB<--|
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// | | |
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// \ |___________|
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// \ /
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// TP exit MBB
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MachineFunction *MF = BB->getParent();
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MachineFunctionProperties &Properties = MF->getProperties();
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MachineRegisterInfo &MRI = MF->getRegInfo();
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Register OpDestReg = MI.getOperand(0).getReg();
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Register OpSrcReg = MI.getOperand(1).getReg();
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Register OpSizeReg = MI.getOperand(2).getReg();
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// Allocate the required MBBs and add to parent function.
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MachineBasicBlock *TpEntry = BB;
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MachineBasicBlock *TpLoopBody = MF->CreateMachineBasicBlock();
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MachineBasicBlock *TpExit;
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MF->push_back(TpLoopBody);
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// If any instructions are present in the current block after
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// MVE_MEMCPYLOOPINST, split the current block and move the instructions
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// into the newly created exit block. If there are no instructions
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// add an explicit branch to the FallThrough block and then split.
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//
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// The split is required for two reasons:
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// 1) A terminator(t2WhileLoopStart) will be placed at that site.
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// 2) Since a TPLoopBody will be added later, any phis in successive blocks
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// need to be updated. splitAt() already handles this.
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TpExit = BB->splitAt(MI, false);
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if (TpExit == BB) {
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assert(BB->canFallThrough() &&
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"Exit block must be FallThrough of the block containing memcpy");
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TpExit = BB->getFallThrough();
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BuildMI(BB, dl, TII->get(ARM::t2B))
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.addMBB(TpExit)
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.add(predOps(ARMCC::AL));
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TpExit = BB->splitAt(MI, false);
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}
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// Add logic for iteration count
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Register TotalIterationsReg =
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genTPEntry(TpEntry, TpLoopBody, TpExit, OpSizeReg, TII, dl, MRI);
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// Add the vectorized (and predicated) loads/store instructions
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genTPLoopBody(TpLoopBody, TpEntry, TpExit, TII, dl, MRI, OpSrcReg,
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OpDestReg, OpSizeReg, TotalIterationsReg);
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// Required to avoid conflict with the MachineVerifier during testing.
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Properties.reset(MachineFunctionProperties::Property::NoPHIs);
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// Connect the blocks
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TpEntry->addSuccessor(TpLoopBody);
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TpLoopBody->addSuccessor(TpLoopBody);
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TpLoopBody->addSuccessor(TpExit);
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// Reorder for a more natural layout
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TpLoopBody->moveAfter(TpEntry);
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TpExit->moveAfter(TpLoopBody);
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// Finally, remove the memcpy Psuedo Instruction
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MI.eraseFromParent();
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// Return the exit block as it may contain other instructions requiring a
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// custom inserter
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return TpExit;
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}
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// The Thumb2 pre-indexed stores have the same MI operands, they just
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// define them differently in the .td files from the isel patterns, so
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// they need pseudos.
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@ -300,6 +300,10 @@ class VectorType;
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// instructions.
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MEMCPY,
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// Pseudo-instruction representing a memory copy using a tail predicated
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// loop
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MEMCPYLOOP,
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// V8.1MMainline condition select
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CSINV, // Conditional select invert.
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CSNEG, // Conditional select negate.
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@ -6865,6 +6865,18 @@ class MVE_WLSTP<string asm, bits<2> size>
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let isTerminator = 1;
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}
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def SDT_MVEMEMCPYLOOPNODE
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: SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
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def MVE_MEMCPYLOOPNODE : SDNode<"ARMISD::MEMCPYLOOP", SDT_MVEMEMCPYLOOPNODE,
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[SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
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let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in {
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def MVE_MEMCPYLOOPINST : PseudoInst<(outs),
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(ins rGPR:$dst, rGPR:$src, rGPR:$sz),
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NoItinerary,
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[(MVE_MEMCPYLOOPNODE rGPR:$dst, rGPR:$src, rGPR:$sz)]>;
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}
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def MVE_DLSTP_8 : MVE_DLSTP<"dlstp.8", 0b00>;
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def MVE_DLSTP_16 : MVE_DLSTP<"dlstp.16", 0b01>;
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def MVE_DLSTP_32 : MVE_DLSTP<"dlstp.32", 0b10>;
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@ -11,12 +11,27 @@
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//===----------------------------------------------------------------------===//
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#include "ARMTargetMachine.h"
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#include "ARMTargetTransformInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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#define DEBUG_TYPE "arm-selectiondag-info"
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cl::opt<TPLoop::MemTransfer> EnableMemtransferTPLoop(
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"arm-memtransfer-tploop", cl::Hidden,
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cl::desc("Control conversion of memcpy to "
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"Tail predicated loops (WLSTP)"),
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cl::init(TPLoop::ForceDisabled),
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cl::values(clEnumValN(TPLoop::ForceDisabled, "force-disabled",
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"Don't convert memcpy to TP loop."),
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clEnumValN(TPLoop::ForceEnabled, "force-enabled",
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"Always convert memcpy to TP loop."),
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clEnumValN(TPLoop::Allow, "allow",
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"Allow (may be subject to certain conditions) "
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"conversion of memcpy to TP loop.")));
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// Emit, if possible, a specialized version of the given Libcall. Typically this
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// means selecting the appropriately aligned version, but we also convert memset
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// of 0 into memclr.
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@ -130,13 +145,40 @@ SDValue ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(
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MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const {
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const ARMSubtarget &Subtarget =
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DAG.getMachineFunction().getSubtarget<ARMSubtarget>();
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ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
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auto GenInlineTP = [&](const ARMSubtarget &Subtarget,
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const SelectionDAG &DAG) {
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auto &F = DAG.getMachineFunction().getFunction();
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if (!EnableMemtransferTPLoop)
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return false;
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if (EnableMemtransferTPLoop == TPLoop::ForceEnabled)
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return true;
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// Do not generate inline TP loop if optimizations is disabled,
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// or if optimization for size (-Os or -Oz) is on.
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if (F.hasOptNone() || F.hasOptSize())
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return false;
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// If cli option is unset
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if (!ConstantSize && Alignment >= Align(4))
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return true;
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if (ConstantSize &&
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ConstantSize->getZExtValue() > Subtarget.getMaxInlineSizeThreshold() &&
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ConstantSize->getZExtValue() <
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Subtarget.getMaxTPLoopInlineSizeThreshold())
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return true;
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return false;
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};
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if (Subtarget.hasMVEIntegerOps() && GenInlineTP(Subtarget, DAG))
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return DAG.getNode(ARMISD::MEMCPYLOOP, dl, MVT::Other, Chain, Dst, Src,
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DAG.getZExtOrTrunc(Size, dl, MVT::i32));
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// Do repeated 4-byte loads and stores. To be improved.
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// This requires 4-byte alignment.
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if (Alignment < Align(4))
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return SDValue();
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// This requires the copy size to be a constant, preferably
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// within a subtarget-specific limit.
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ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
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if (!ConstantSize)
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return EmitSpecializedLibcall(DAG, dl, Chain, Dst, Src, Size,
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Alignment.value(), RTLIB::MEMCPY);
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@ -538,6 +538,11 @@ public:
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return 64;
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}
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/// getMaxTPLoopSizeThreshold - Returns the maximum memcpy size
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/// that still makes it profitable to inline the call as a Tail
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/// Predicated loop
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unsigned getMaxTPLoopInlineSizeThreshold() const { return 128; }
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/// ParseSubtargetFeatures - Parses features string setting specified
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/// subtarget options. Definition of function is auto generated by tblgen.
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void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
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@ -48,6 +48,11 @@ namespace TailPredication {
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};
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}
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// For controlling conversion of memcpy into Tail Predicated loop.
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namespace TPLoop {
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enum MemTransfer { ForceDisabled = 0, ForceEnabled, Allow };
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}
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class ARMTTIImpl : public BasicTTIImplBase<ARMTTIImpl> {
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using BaseT = BasicTTIImplBase<ARMTTIImpl>;
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using TTI = TargetTransformInfo;
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@ -1,34 +1,39 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs -tail-predication=enabled -o - %s | FileCheck %s
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; RUN: llc --arm-memtransfer-tploop=allow -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs -tail-predication=enabled -o - %s | FileCheck %s
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define void @test_memcpy(i32* nocapture %x, i32* nocapture readonly %y, i32 %n, i32 %m) {
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; CHECK-LABEL: test_memcpy:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, lr}
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; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, lr}
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; CHECK-NEXT: .pad #4
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; CHECK-NEXT: sub sp, #4
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; CHECK-NEXT: .save {r4, r5, r6, r7, lr}
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; CHECK-NEXT: push {r4, r5, r6, r7, lr}
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; CHECK-NEXT: cmp r2, #1
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; CHECK-NEXT: blt .LBB0_3
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; CHECK-NEXT: blt .LBB0_5
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; CHECK-NEXT: @ %bb.1: @ %for.body.preheader
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; CHECK-NEXT: mov r8, r3
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; CHECK-NEXT: mov r5, r2
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; CHECK-NEXT: mov r9, r1
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; CHECK-NEXT: mov r7, r0
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; CHECK-NEXT: lsls r4, r3, #2
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; CHECK-NEXT: movs r6, #0
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; CHECK-NEXT: lsl.w r12, r3, #2
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; CHECK-NEXT: movs r7, #0
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; CHECK-NEXT: b .LBB0_2
|
||||
; CHECK-NEXT: .LBB0_2: @ %for.body
|
||||
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
|
||||
; CHECK-NEXT: adds r0, r7, r6
|
||||
; CHECK-NEXT: add.w r1, r9, r6
|
||||
; CHECK-NEXT: mov r2, r8
|
||||
; CHECK-NEXT: bl __aeabi_memcpy4
|
||||
; CHECK-NEXT: add r6, r4
|
||||
; CHECK-NEXT: subs r5, #1
|
||||
; CHECK-NEXT: bne .LBB0_2
|
||||
; CHECK-NEXT: .LBB0_3: @ %for.cond.cleanup
|
||||
; CHECK-NEXT: add sp, #4
|
||||
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, pc}
|
||||
; CHECK-NEXT: @ =>This Loop Header: Depth=1
|
||||
; CHECK-NEXT: @ Child Loop BB0_4 Depth 2
|
||||
; CHECK-NEXT: adds r4, r1, r7
|
||||
; CHECK-NEXT: adds r5, r0, r7
|
||||
; CHECK-NEXT: mov r6, r3
|
||||
; CHECK-NEXT: wlstp.8 lr, r6, .LBB0_3
|
||||
; CHECK-NEXT: b .LBB0_4
|
||||
; CHECK-NEXT: .LBB0_3: @ %for.body
|
||||
; CHECK-NEXT: @ in Loop: Header=BB0_2 Depth=1
|
||||
; CHECK-NEXT: add r7, r12
|
||||
; CHECK-NEXT: subs r2, #1
|
||||
; CHECK-NEXT: beq .LBB0_5
|
||||
; CHECK-NEXT: b .LBB0_2
|
||||
; CHECK-NEXT: .LBB0_4: @ Parent Loop BB0_2 Depth=1
|
||||
; CHECK-NEXT: @ => This Inner Loop Header: Depth=2
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r4], #16
|
||||
; CHECK-NEXT: vstrb.8 q0, [r5], #16
|
||||
; CHECK-NEXT: letp lr, .LBB0_4
|
||||
; CHECK-NEXT: b .LBB0_3
|
||||
; CHECK-NEXT: .LBB0_5: @ %for.cond.cleanup
|
||||
; CHECK-NEXT: pop {r4, r5, r6, r7, pc}
|
||||
entry:
|
||||
%cmp8 = icmp sgt i32 %n, 0
|
||||
br i1 %cmp8, label %for.body, label %for.cond.cleanup
|
||||
|
||||
285
test/CodeGen/Thumb2/mve-tp-loop.ll
Normal file
285
test/CodeGen/Thumb2/mve-tp-loop.ll
Normal file
@ -0,0 +1,285 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc --arm-memtransfer-tploop=allow -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve --verify-machineinstrs %s -o - | FileCheck %s
|
||||
|
||||
; Check that WLSTP loop is not generated for alignment < 4
|
||||
; void test1(char* dest, char* src, int n){
|
||||
; memcpy(dest, src, n);
|
||||
; }
|
||||
|
||||
declare void @llvm.memcpy.p0i8.p0i8.i32(i8* noalias nocapture writeonly, i8* noalias nocapture readonly, i32, i1 immarg) #1
|
||||
declare void @llvm.memcpy.p0i8.p0i8.i64(i8* noalias nocapture writeonly, i8* noalias nocapture readonly, i64, i1 immarg) #1
|
||||
|
||||
define void @test1(i8* noalias nocapture %X, i8* noalias nocapture readonly %Y, i32 %n){
|
||||
; CHECK-LABEL: test1:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .save {r7, lr}
|
||||
; CHECK-NEXT: push {r7, lr}
|
||||
; CHECK-NEXT: bl __aeabi_memcpy
|
||||
; CHECK-NEXT: pop {r7, pc}
|
||||
entry:
|
||||
call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 %X, i8* align 1 %Y, i32 %n, i1 false)
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
; Check that WLSTP loop is generated for alignment >= 4
|
||||
; void test2(int* restrict X, int* restrict Y, int n){
|
||||
; memcpy(X, Y, n);
|
||||
; }
|
||||
|
||||
define void @test2(i32* noalias %X, i32* noalias readonly %Y, i32 %n){
|
||||
; CHECK-LABEL: test2:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .save {r7, lr}
|
||||
; CHECK-NEXT: push {r7, lr}
|
||||
; CHECK-NEXT: wlstp.8 lr, r2, .LBB1_2
|
||||
; CHECK-NEXT: .LBB1_1: @ =>This Inner Loop Header: Depth=1
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r1], #16
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0], #16
|
||||
; CHECK-NEXT: letp lr, .LBB1_1
|
||||
; CHECK-NEXT: .LBB1_2: @ %entry
|
||||
; CHECK-NEXT: pop {r7, pc}
|
||||
entry:
|
||||
%0 = bitcast i32* %X to i8*
|
||||
%1 = bitcast i32* %Y to i8*
|
||||
call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %0, i8* align 4 %1, i32 %n, i1 false)
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
; Checks that transform handles some arithmetic on the input arguments.
|
||||
; void test3(int* restrict X, int* restrict Y, int n)
|
||||
; {
|
||||
; memcpy(X+2, Y+3, (n*2)+10);
|
||||
; }
|
||||
|
||||
define void @test3(i32* noalias nocapture %X, i32* noalias nocapture readonly %Y, i32 %n) {
|
||||
; CHECK-LABEL: test3:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .save {r7, lr}
|
||||
; CHECK-NEXT: push {r7, lr}
|
||||
; CHECK-NEXT: movs r3, #10
|
||||
; CHECK-NEXT: add.w r2, r3, r2, lsl #1
|
||||
; CHECK-NEXT: adds r1, #12
|
||||
; CHECK-NEXT: adds r0, #8
|
||||
; CHECK-NEXT: wlstp.8 lr, r2, .LBB2_2
|
||||
; CHECK-NEXT: .LBB2_1: @ =>This Inner Loop Header: Depth=1
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r1], #16
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0], #16
|
||||
; CHECK-NEXT: letp lr, .LBB2_1
|
||||
; CHECK-NEXT: .LBB2_2: @ %entry
|
||||
; CHECK-NEXT: pop {r7, pc}
|
||||
entry:
|
||||
%add.ptr = getelementptr inbounds i32, i32* %X, i32 2
|
||||
%0 = bitcast i32* %add.ptr to i8*
|
||||
%add.ptr1 = getelementptr inbounds i32, i32* %Y, i32 3
|
||||
%1 = bitcast i32* %add.ptr1 to i8*
|
||||
%mul = shl nsw i32 %n, 1
|
||||
%add = add nsw i32 %mul, 10
|
||||
call void @llvm.memcpy.p0i8.p0i8.i32(i8* nonnull align 4 %0, i8* nonnull align 4 %1, i32 %add, i1 false)
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
; Checks that transform handles for loops that are implicitly converted to mempcy
|
||||
; void test4(int* restrict X, int* restrict Y, int n){
|
||||
; for(int i = 0; i < n; ++i){
|
||||
; X[i] = Y[i];
|
||||
; }
|
||||
; }
|
||||
|
||||
define void @test4(i32* noalias %X, i32* noalias readonly %Y, i32 %n) {
|
||||
; CHECK-LABEL: test4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: cmp r2, #1
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: bxlt lr
|
||||
; CHECK-NEXT: .LBB3_1: @ %for.body.preheader
|
||||
; CHECK-NEXT: .save {r7, lr}
|
||||
; CHECK-NEXT: push {r7, lr}
|
||||
; CHECK-NEXT: wlstp.8 lr, r2, .LBB3_3
|
||||
; CHECK-NEXT: .LBB3_2: @ =>This Inner Loop Header: Depth=1
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r1], #16
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0], #16
|
||||
; CHECK-NEXT: letp lr, .LBB3_2
|
||||
; CHECK-NEXT: .LBB3_3: @ %for.body.preheader
|
||||
; CHECK-NEXT: pop.w {r7, lr}
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%cmp6 = icmp sgt i32 %n, 0
|
||||
br i1 %cmp6, label %for.body.preheader, label %for.cond.cleanup
|
||||
|
||||
for.body.preheader: ; preds = %entry
|
||||
%X.bits = bitcast i32* %X to i8*
|
||||
%Y.bits = bitcast i32* %Y to i8*
|
||||
call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %X.bits, i8* align 4 %Y.bits, i32 %n, i1 false)
|
||||
br label %for.cond.cleanup
|
||||
|
||||
for.cond.cleanup: ; preds = %for.body.preheader, %entry
|
||||
ret void
|
||||
}
|
||||
|
||||
; Checks that transform can handle > i32 size inputs
|
||||
define void @test5(i8* noalias %X, i8* noalias %Y, i64 %n){
|
||||
; CHECK-LABEL: test5:
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: .save {r7, lr}
|
||||
; CHECK-NEXT: push {r7, lr}
|
||||
; CHECK-NEXT: wlstp.8 lr, r2, .LBB4_2
|
||||
; CHECK-NEXT: .LBB4_1: @ =>This Inner Loop Header: Depth=1
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r1], #16
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0], #16
|
||||
; CHECK-NEXT: letp lr, .LBB4_1
|
||||
; CHECK-NEXT: .LBB4_2:
|
||||
; CHECK-NEXT: pop {r7, pc}
|
||||
call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %X, i8* align 4 %Y, i64 %n, i1 false)
|
||||
ret void
|
||||
}
|
||||
|
||||
; Checks the transform is applied for constant size inputs below a certain threshold (128 in this case)
|
||||
define void @test6(i32* noalias nocapture %X, i32* noalias nocapture readonly %Y, i32 %n) {
|
||||
; CHECK-LABEL: test6:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .save {r7, lr}
|
||||
; CHECK-NEXT: push {r7, lr}
|
||||
; CHECK-NEXT: movs r2, #127
|
||||
; CHECK-NEXT: wlstp.8 lr, r2, .LBB5_2
|
||||
; CHECK-NEXT: .LBB5_1: @ =>This Inner Loop Header: Depth=1
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r1], #16
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0], #16
|
||||
; CHECK-NEXT: letp lr, .LBB5_1
|
||||
; CHECK-NEXT: .LBB5_2: @ %entry
|
||||
; CHECK-NEXT: pop {r7, pc}
|
||||
entry:
|
||||
%0 = bitcast i32* %X to i8*
|
||||
%1 = bitcast i32* %Y to i8*
|
||||
call void @llvm.memcpy.p0i8.p0i8.i32(i8* noundef nonnull align 4 dereferenceable(127) %0, i8* noundef nonnull align 4 dereferenceable(127) %1, i32 127, i1 false)
|
||||
ret void
|
||||
}
|
||||
|
||||
; Checks the transform is NOT applied for constant size inputs above a certain threshold (128 in this case)
|
||||
define void @test7(i32* noalias nocapture %X, i32* noalias nocapture readonly %Y, i32 %n) {
|
||||
; CHECK-LABEL: test7:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .save {r7, lr}
|
||||
; CHECK-NEXT: push {r7, lr}
|
||||
; CHECK-NEXT: movs r2, #128
|
||||
; CHECK-NEXT: bl __aeabi_memcpy4
|
||||
; CHECK-NEXT: pop {r7, pc}
|
||||
entry:
|
||||
%0 = bitcast i32* %X to i8*
|
||||
%1 = bitcast i32* %Y to i8*
|
||||
call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %0, i8* align 4 %1, i32 128, i1 false)
|
||||
ret void
|
||||
}
|
||||
|
||||
; Checks the transform is NOT applied for constant size inputs below a certain threshold (64 in this case)
|
||||
define void @test8(i32* noalias nocapture %X, i32* noalias nocapture readonly %Y, i32 %n) {
|
||||
; CHECK-LABEL: test8:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .save {r4, lr}
|
||||
; CHECK-NEXT: push {r4, lr}
|
||||
; CHECK-NEXT: ldm.w r1!, {r2, r3, r4, r12, lr}
|
||||
; CHECK-NEXT: stm.w r0!, {r2, r3, r4, r12, lr}
|
||||
; CHECK-NEXT: ldm.w r1!, {r2, r3, r4, r12, lr}
|
||||
; CHECK-NEXT: stm.w r0!, {r2, r3, r4, r12, lr}
|
||||
; CHECK-NEXT: ldm.w r1, {r2, r3, r4, r12, lr}
|
||||
; CHECK-NEXT: stm.w r0, {r2, r3, r4, r12, lr}
|
||||
; CHECK-NEXT: pop {r4, pc}
|
||||
entry:
|
||||
%0 = bitcast i32* %X to i8*
|
||||
%1 = bitcast i32* %Y to i8*
|
||||
call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %0, i8* align 4 %1, i32 60, i1 false)
|
||||
ret void
|
||||
}
|
||||
|
||||
; Checks the transform is NOT applied (regardless of alignment) when optimizations are disabled
|
||||
define void @test9(i32* noalias nocapture %X, i32* noalias nocapture readonly %Y, i32 %n) #0 {
|
||||
; CHECK-LABEL: test9:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .save {r7, lr}
|
||||
; CHECK-NEXT: push {r7, lr}
|
||||
; CHECK-NEXT: bl __aeabi_memcpy4
|
||||
; CHECK-NEXT: pop {r7, pc}
|
||||
entry:
|
||||
%0 = bitcast i32* %X to i8*
|
||||
%1 = bitcast i32* %Y to i8*
|
||||
call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %0, i8* align 4 %1, i32 %n, i1 false)
|
||||
ret void
|
||||
}
|
||||
|
||||
; Checks the transform is NOT applied (regardless of alignment) when optimization for size is on (-Os or -Oz)
|
||||
define void @test10(i32* noalias nocapture %X, i32* noalias nocapture readonly %Y, i32 %n) #1 {
|
||||
; CHECK-LABEL: test10:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .save {r7, lr}
|
||||
; CHECK-NEXT: push {r7, lr}
|
||||
; CHECK-NEXT: bl __aeabi_memcpy4
|
||||
; CHECK-NEXT: pop {r7, pc}
|
||||
entry:
|
||||
%0 = bitcast i32* %X to i8*
|
||||
%1 = bitcast i32* %Y to i8*
|
||||
call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %0, i8* align 4 %1, i32 %n, i1 false)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test11(i8* nocapture %x, i8* nocapture %y, i32 %n) {
|
||||
; CHECK-LABEL: test11:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .save {r4, lr}
|
||||
; CHECK-NEXT: push {r4, lr}
|
||||
; CHECK-NEXT: cmp.w r2, #-1
|
||||
; CHECK-NEXT: it gt
|
||||
; CHECK-NEXT: popgt {r4, pc}
|
||||
; CHECK-NEXT: .LBB10_1: @ %prehead
|
||||
; CHECK-NEXT: add.w r3, r2, #15
|
||||
; CHECK-NEXT: mov r12, r1
|
||||
; CHECK-NEXT: bic r3, r3, #16
|
||||
; CHECK-NEXT: mov r4, r0
|
||||
; CHECK-NEXT: lsr.w lr, r3, #4
|
||||
; CHECK-NEXT: mov r3, r2
|
||||
; CHECK-NEXT: subs.w lr, lr, #0
|
||||
; CHECK-NEXT: beq .LBB10_3
|
||||
; CHECK-NEXT: .LBB10_2: @ =>This Inner Loop Header: Depth=1
|
||||
; CHECK-NEXT: vctp.8 r3
|
||||
; CHECK-NEXT: subs r3, #16
|
||||
; CHECK-NEXT: vpstt
|
||||
; CHECK-NEXT: vldrbt.u8 q0, [r12], #16
|
||||
; CHECK-NEXT: vstrbt.8 q0, [r4], #16
|
||||
; CHECK-NEXT: subs.w lr, lr, #1
|
||||
; CHECK-NEXT: bne .LBB10_2
|
||||
; CHECK-NEXT: b .LBB10_3
|
||||
; CHECK-NEXT: .LBB10_3: @ %for.body
|
||||
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
|
||||
; CHECK-NEXT: ldrb r3, [r0], #1
|
||||
; CHECK-NEXT: subs r2, #2
|
||||
; CHECK-NEXT: strb r3, [r1], #1
|
||||
; CHECK-NEXT: bne .LBB10_3
|
||||
; CHECK-NEXT: @ %bb.4: @ %for.cond.cleanup
|
||||
; CHECK-NEXT: pop {r4, pc}
|
||||
entry:
|
||||
%cmp6 = icmp slt i32 %n, 0
|
||||
br i1 %cmp6, label %prehead, label %for.cond.cleanup
|
||||
|
||||
prehead: ; preds = %entry
|
||||
call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %x, i8* align 4 %y, i32 %n, i1 false)
|
||||
br label %for.body
|
||||
|
||||
for.body: ; preds = %for.body, %prehead
|
||||
%i.09 = phi i32 [ %inc, %for.body ], [ 0, %prehead ]
|
||||
%x.addr.08 = phi i8* [ %add.ptr, %for.body ], [ %x, %prehead ]
|
||||
%y.addr.07 = phi i8* [ %add.ptr1, %for.body ], [ %y, %prehead ]
|
||||
%add.ptr = getelementptr inbounds i8, i8* %x.addr.08, i32 1
|
||||
%add.ptr1 = getelementptr inbounds i8, i8* %y.addr.07, i32 1
|
||||
%l = load i8, i8* %x.addr.08, align 1
|
||||
store i8 %l, i8* %y.addr.07, align 1
|
||||
%inc = add nuw nsw i32 %i.09, 2
|
||||
%exitcond.not = icmp eq i32 %inc, %n
|
||||
br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
|
||||
|
||||
for.cond.cleanup: ; preds = %entry
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { noinline optnone }
|
||||
attributes #1 = { optsize }
|
||||
127
test/CodeGen/Thumb2/mve-tp-loop.mir
Normal file
127
test/CodeGen/Thumb2/mve-tp-loop.mir
Normal file
@ -0,0 +1,127 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve -simplify-mir --verify-machineinstrs -run-pass=finalize-isel %s -o - | FileCheck %s
|
||||
--- |
|
||||
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
|
||||
target triple = "arm-arm-none-eabi"
|
||||
|
||||
; Function Attrs: argmemonly nofree nosync nounwind willreturn
|
||||
declare void @llvm.memcpy.p0i8.p0i8.i32(i8* noalias nocapture writeonly, i8* noalias nocapture readonly, i32, i1 immarg)
|
||||
|
||||
define void @test1(i32* noalias %X, i32* noalias readonly %Y, i32 %n) {
|
||||
entry:
|
||||
%0 = bitcast i32* %X to i8*
|
||||
%1 = bitcast i32* %Y to i8*
|
||||
call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %0, i8* align 4 %1, i32 %n, i1 false)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test2(i32* noalias %X, i32* noalias readonly %Y, i32 %n) {
|
||||
entry:
|
||||
%cmp6 = icmp sgt i32 %n, 0
|
||||
br i1 %cmp6, label %for.body.preheader, label %for.cond.cleanup
|
||||
|
||||
for.body.preheader: ; preds = %entry
|
||||
%X.bits = bitcast i32* %X to i8*
|
||||
%Y.bits = bitcast i32* %Y to i8*
|
||||
call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %X.bits, i8* align 4 %Y.bits, i32 %n, i1 false)
|
||||
br label %for.cond.cleanup
|
||||
|
||||
for.cond.cleanup: ; preds = %for.body.preheader, %entry
|
||||
ret void
|
||||
}
|
||||
|
||||
...
|
||||
---
|
||||
name: test1
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0.entry:
|
||||
liveins: $r0, $r1, $r2
|
||||
|
||||
; CHECK-LABEL: name: test1
|
||||
; CHECK: liveins: $r0, $r1, $r2
|
||||
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r2
|
||||
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
|
||||
; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY $r0
|
||||
; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[COPY]], 15, 14 /* CC::al */, $noreg, $noreg
|
||||
; CHECK: [[t2BICri:%[0-9]+]]:rgpr = t2BICri killed [[t2ADDri]], 16, 14 /* CC::al */, $noreg, $noreg
|
||||
; CHECK: [[t2LSRri:%[0-9]+]]:gprlr = t2LSRri killed [[t2BICri]], 4, 14 /* CC::al */, $noreg, $noreg
|
||||
; CHECK: [[t2WhileLoopSetup:%[0-9]+]]:gprlr = t2WhileLoopSetup killed [[t2LSRri]]
|
||||
; CHECK: t2WhileLoopStart [[t2WhileLoopSetup]], %bb.2, implicit-def $cpsr
|
||||
; CHECK: .1:
|
||||
; CHECK: [[PHI:%[0-9]+]]:rgpr = PHI [[COPY1]], %bb.0, %8, %bb.1
|
||||
; CHECK: [[PHI1:%[0-9]+]]:rgpr = PHI [[COPY2]], %bb.0, %10, %bb.1
|
||||
; CHECK: [[PHI2:%[0-9]+]]:gprlr = PHI [[t2WhileLoopSetup]], %bb.0, %12, %bb.1
|
||||
; CHECK: [[PHI3:%[0-9]+]]:rgpr = PHI [[COPY]], %bb.0, %14, %bb.1
|
||||
; CHECK: [[MVE_VCTP8_:%[0-9]+]]:vccr = MVE_VCTP8 [[PHI3]], 0, $noreg
|
||||
; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[PHI3]], 16, 14 /* CC::al */, $noreg, $noreg
|
||||
; CHECK: [[MVE_VLDRBU8_post:%[0-9]+]]:rgpr, [[MVE_VLDRBU8_post1:%[0-9]+]]:mqpr = MVE_VLDRBU8_post [[PHI]], 16, 1, [[MVE_VCTP8_]]
|
||||
; CHECK: [[MVE_VSTRBU8_post:%[0-9]+]]:rgpr = MVE_VSTRBU8_post killed [[MVE_VLDRBU8_post1]], [[PHI1]], 16, 1, [[MVE_VCTP8_]]
|
||||
; CHECK: [[t2LoopDec:%[0-9]+]]:gprlr = t2LoopDec [[PHI2]], 1
|
||||
; CHECK: t2LoopEnd [[t2LoopDec]], %bb.1, implicit-def $cpsr
|
||||
; CHECK: t2B %bb.2, 14 /* CC::al */, $noreg
|
||||
; CHECK: .2.entry:
|
||||
; CHECK: tBX_RET 14 /* CC::al */, $noreg
|
||||
%2:rgpr = COPY $r2
|
||||
%1:rgpr = COPY $r1
|
||||
%0:rgpr = COPY $r0
|
||||
MVE_MEMCPYLOOPINST %0, %1, %2
|
||||
tBX_RET 14 /* CC::al */, $noreg
|
||||
|
||||
...
|
||||
---
|
||||
name: test2
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
; CHECK-LABEL: name: test2
|
||||
; CHECK: bb.0.entry:
|
||||
; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
|
||||
; CHECK: liveins: $r0, $r1, $r2
|
||||
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r2
|
||||
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
|
||||
; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY $r0
|
||||
; CHECK: t2CMPri [[COPY]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
|
||||
; CHECK: t2Bcc %bb.2, 11 /* CC::lt */, $cpsr
|
||||
; CHECK: t2B %bb.1, 14 /* CC::al */, $noreg
|
||||
; CHECK: bb.1.for.body.preheader:
|
||||
; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[COPY]], 15, 14 /* CC::al */, $noreg, $noreg
|
||||
; CHECK: [[t2BICri:%[0-9]+]]:rgpr = t2BICri killed [[t2ADDri]], 16, 14 /* CC::al */, $noreg, $noreg
|
||||
; CHECK: [[t2LSRri:%[0-9]+]]:gprlr = t2LSRri killed [[t2BICri]], 4, 14 /* CC::al */, $noreg, $noreg
|
||||
; CHECK: [[t2WhileLoopSetup:%[0-9]+]]:gprlr = t2WhileLoopSetup killed [[t2LSRri]]
|
||||
; CHECK: t2WhileLoopStart [[t2WhileLoopSetup]], %bb.4, implicit-def $cpsr
|
||||
; CHECK: bb.3:
|
||||
; CHECK: [[PHI:%[0-9]+]]:rgpr = PHI [[COPY1]], %bb.1, %8, %bb.3
|
||||
; CHECK: [[PHI1:%[0-9]+]]:rgpr = PHI [[COPY2]], %bb.1, %10, %bb.3
|
||||
; CHECK: [[PHI2:%[0-9]+]]:gprlr = PHI [[t2WhileLoopSetup]], %bb.1, %12, %bb.3
|
||||
; CHECK: [[PHI3:%[0-9]+]]:rgpr = PHI [[COPY]], %bb.1, %14, %bb.3
|
||||
; CHECK: [[MVE_VCTP8_:%[0-9]+]]:vccr = MVE_VCTP8 [[PHI3]], 0, $noreg
|
||||
; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[PHI3]], 16, 14 /* CC::al */, $noreg, $noreg
|
||||
; CHECK: [[MVE_VLDRBU8_post:%[0-9]+]]:rgpr, [[MVE_VLDRBU8_post1:%[0-9]+]]:mqpr = MVE_VLDRBU8_post [[PHI]], 16, 1, [[MVE_VCTP8_]]
|
||||
; CHECK: [[MVE_VSTRBU8_post:%[0-9]+]]:rgpr = MVE_VSTRBU8_post killed [[MVE_VLDRBU8_post1]], [[PHI1]], 16, 1, [[MVE_VCTP8_]]
|
||||
; CHECK: [[t2LoopDec:%[0-9]+]]:gprlr = t2LoopDec [[PHI2]], 1
|
||||
; CHECK: t2LoopEnd [[t2LoopDec]], %bb.3, implicit-def $cpsr
|
||||
; CHECK: t2B %bb.4, 14 /* CC::al */, $noreg
|
||||
; CHECK: bb.4.for.body.preheader:
|
||||
; CHECK: t2B %bb.2, 14 /* CC::al */, $noreg
|
||||
; CHECK: bb.2.for.cond.cleanup:
|
||||
; CHECK: tBX_RET 14 /* CC::al */, $noreg
|
||||
bb.0.entry:
|
||||
successors: %bb.1(0x50000000), %bb.2(0x30000000)
|
||||
liveins: $r0, $r1, $r2
|
||||
|
||||
%2:rgpr = COPY $r2
|
||||
%1:rgpr = COPY $r1
|
||||
%0:rgpr = COPY $r0
|
||||
t2CMPri %2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
|
||||
t2Bcc %bb.2, 11 /* CC::lt */, $cpsr
|
||||
t2B %bb.1, 14 /* CC::al */, $noreg
|
||||
|
||||
bb.1.for.body.preheader:
|
||||
successors: %bb.2(0x80000000)
|
||||
|
||||
MVE_MEMCPYLOOPINST %0, %1, %2
|
||||
|
||||
bb.2.for.cond.cleanup:
|
||||
tBX_RET 14 /* CC::al */, $noreg
|
||||
|
||||
...
|
||||
Loading…
Reference in New Issue
Block a user