From 4adb8143cefcd905d50ec50ef227329421fbec25 Mon Sep 17 00:00:00 2001 From: Duraid Madina Date: Thu, 3 Nov 2005 10:09:32 +0000 Subject: [PATCH] add pattern to load constant 0 into a predicate reg llvm-svn: 24164 --- lib/Target/IA64/IA64InstrInfo.td | 2 ++ 1 file changed, 2 insertions(+) diff --git a/lib/Target/IA64/IA64InstrInfo.td b/lib/Target/IA64/IA64InstrInfo.td index 7620f4a6ab9..26d5e2c02ba 100644 --- a/lib/Target/IA64/IA64InstrInfo.td +++ b/lib/Target/IA64/IA64InstrInfo.td @@ -361,6 +361,8 @@ def SELECTINT : Pat<(select PR:$which, GR:$src1, GR:$src2), def : Pat<(i64 immSExt14:$imm), (ADDS r0, immSExt14:$imm)>; def : Pat<(i64 imm64:$imm), (MOVL imm64:$imm)>; def : Pat<(i1 -1), (CMPEQ r0, r0)>; // TODO: this should just be a ref to p0 +def : Pat<(i1 0), (CMPNE r0, r0)>; // TODO: any instruction actually *using* + // this predicate should be killed! // TODO: support postincrement (reg, imm9) loads+stores - this needs more // tablegen support