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Code clean up. The peephole pass should be the one updating the instruction

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iterator, not TII->OptimizeCompareInstr.

llvm-svn: 119186
This commit is contained in:
Evan Cheng 2010-11-15 21:20:45 +00:00
parent db1a4541c2
commit 4afa3a6b1f
4 changed files with 19 additions and 27 deletions
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6
include/llvm/Target/TargetInstrInfo.h
View File

@ -602,12 +602,10 @@ public:
/// OptimizeCompareInstr - See if the comparison instruction can be converted
/// into something more efficient. E.g., on ARM most instructions can set the
/// flags register, obviating the need for a separate CMP. Update the iterator
/// *only* if a transformation took place.
/// flags register, obviating the need for a separate CMP.
virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr,
unsigned SrcReg, int Mask, int Value,
const MachineRegisterInfo *MRI,
MachineBasicBlock::iterator &) const {
const MachineRegisterInfo *MRI) const {
return false;
}

28
lib/CodeGen/PeepholeOptimizer.cpp
View File

@ -82,8 +82,7 @@ namespace {
}
private:
bool OptimizeCmpInstr(MachineInstr *MI, MachineBasicBlock *MBB,
MachineBasicBlock::iterator &MII);
bool OptimizeCmpInstr(MachineInstr *MI, MachineBasicBlock *MBB);
bool OptimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB,
SmallPtrSet<MachineInstr*, 8> &LocalMIs);
};
@ -112,8 +111,6 @@ FunctionPass *llvm::createPeepholeOptimizerPass() {
bool PeepholeOptimizer::
OptimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB,
SmallPtrSet<MachineInstr*, 8> &LocalMIs) {
LocalMIs.insert(MI);
unsigned SrcReg, DstReg, SubIdx;
if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx))
return false;
@ -242,8 +239,7 @@ OptimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB,
/// set) the same flag as the compare, then we can remove the comparison and use
/// the flag from the previous instruction.
bool PeepholeOptimizer::OptimizeCmpInstr(MachineInstr *MI,
MachineBasicBlock *MBB,
MachineBasicBlock::iterator &NextIter){
MachineBasicBlock *MBB){
// If this instruction is a comparison against zero and isn't comparing a
// physical register, we can try to optimize it.
unsigned SrcReg;
@ -253,7 +249,7 @@ bool PeepholeOptimizer::OptimizeCmpInstr(MachineInstr *MI,
return false;
// Attempt to optimize the comparison instruction.
if (TII->OptimizeCompareInstr(MI, SrcReg, CmpMask, CmpValue, MRI, NextIter)) {
if (TII->OptimizeCompareInstr(MI, SrcReg, CmpMask, CmpValue, MRI)) {
++NumEliminated;
return true;
}
@ -262,6 +258,9 @@ bool PeepholeOptimizer::OptimizeCmpInstr(MachineInstr *MI,
}
bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) {
if (DisablePeephole)
return false;
TM = &MF.getTarget();
TII = TM->getInstrInfo();
MRI = &MF.getRegInfo();
@ -276,17 +275,16 @@ bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) {
for (MachineBasicBlock::iterator
MII = I->begin(), MIE = I->end(); MII != MIE; ) {
MachineInstr *MI = &*MII;
MachineInstr *MI = &*MII++;
LocalMIs.insert(MI);
if (MI->getDesc().isCompare() &&
!MI->getDesc().hasUnmodeledSideEffects()) {
if (!DisablePeephole && OptimizeCmpInstr(MI, MBB, MII))
Changed = true;
else
++MII;
if (MI->getDesc().hasUnmodeledSideEffects())
continue;
if (MI->getDesc().isCompare()) {
Changed |= OptimizeCmpInstr(MI, MBB);
} else {
Changed |= OptimizeExtInstr(MI, MBB, LocalMIs);
++MII;
}
}
}

7
lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -1484,12 +1484,10 @@ static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
}
/// OptimizeCompareInstr - Convert the instruction supplying the argument to the
/// comparison into one that sets the zero bit in the flags register. Update the
/// iterator *only* if a transformation took place.
/// comparison into one that sets the zero bit in the flags register.
bool ARMBaseInstrInfo::
OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask,
int CmpValue, const MachineRegisterInfo *MRI,
MachineBasicBlock::iterator &MII) const {
int CmpValue, const MachineRegisterInfo *MRI) const {
if (CmpValue != 0)
return false;
@ -1561,7 +1559,6 @@ OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask,
MI->RemoveOperand(5);
MachineInstrBuilder(MI)
.addReg(ARM::CPSR, RegState::Define | RegState::Implicit);
MII = llvm::next(MachineBasicBlock::iterator(CmpInstr));
CmpInstr->eraseFromParent();
return true;
}

3
lib/Target/ARM/ARMBaseInstrInfo.h
View File

@ -344,8 +344,7 @@ public:
/// that we can remove a "comparison with zero".
virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
int CmpMask, int CmpValue,
const MachineRegisterInfo *MRI,
MachineBasicBlock::iterator &MII) const;
const MachineRegisterInfo *MRI) const;
virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
const MachineInstr *MI) const;