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Align store conditional address
In cases where the alignment of the datatype is smaller than expected by the instruction, the address is aligned. The aligned address is used for the load, but wasn't used for the store conditional, which resulted in a run-time alignment exception.
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@ -1239,7 +1239,8 @@ bool AtomicExpand::expandAtomicCmpXchg(AtomicCmpXchgInst *CI) {
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Value *NewValueInsert =
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insertMaskedValue(Builder, LoadedTryStore, CI->getNewValOperand(), PMV);
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Value *StoreSuccess =
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TLI->emitStoreConditional(Builder, NewValueInsert, Addr, MemOpOrder);
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TLI->emitStoreConditional(Builder, NewValueInsert, PMV.AlignedAddr,
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MemOpOrder);
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StoreSuccess = Builder.CreateICmpEQ(
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StoreSuccess, ConstantInt::get(Type::getInt32Ty(Ctx), 0), "success");
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BasicBlock *RetryBB = HasReleasedLoadBB ? ReleasedLoadBB : StartBB;
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18
test/CodeGen/Hexagon/atomic-store-byte.ll
Normal file
18
test/CodeGen/Hexagon/atomic-store-byte.ll
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@ -0,0 +1,18 @@
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; RUN: llc -mtriple=hexagon < %s | FileCheck %s
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; Test that the address for a store conditional for a byte is aligned
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; correctly to use the memw_locked instruction.
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; CHECK: [[REG:(r[0-9]+)]] = and(r{{[0-9]+}},#-4)
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; CHECK: = memw_locked([[REG]])
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; CHECK: memw_locked([[REG]],p{{[0-4]}}) =
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@foo.a00 = internal global i8 0, align 1
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; Function Attrs: nofree norecurse nounwind
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define dso_local void @foo() local_unnamed_addr #0 {
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entry:
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%0 = cmpxchg volatile i8* @foo.a00, i8 0, i8 1 seq_cst seq_cst
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ret void
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}
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