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R600: Simplify stream outputs intrinsic
Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 173296
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@ -386,39 +386,7 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
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Chain);
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}
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case AMDGPUIntrinsic::R600_store_stream_output : {
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MachineFunction &MF = DAG.getMachineFunction();
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R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
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int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
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int64_t BufIndex = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
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SDNode **OutputsMap = MFI->StreamOutputs[BufIndex];
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unsigned Inst;
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switch (cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue() ) {
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// STREAM3
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case 3:
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Inst = 4;
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break;
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// STREAM2
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case 2:
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Inst = 3;
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break;
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// STREAM1
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case 1:
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Inst = 2;
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break;
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// STREAM0
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case 0:
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Inst = 1;
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break;
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default:
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llvm_unreachable("Wrong buffer id for stream outputs !");
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}
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return InsertScalarToRegisterExport(DAG, Op.getDebugLoc(), OutputsMap,
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RegIndex / 4, RegIndex % 4, Inst, 0, Op.getOperand(2),
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Chain);
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}
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// default for switch(IntrinsicID)
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default: break;
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}
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@ -604,24 +604,24 @@ multiclass ExportPattern<Instruction ExportInst, bits<8> cf_inst> {
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multiclass SteamOutputExportPattern<Instruction ExportInst,
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bits<8> buf0inst, bits<8> buf1inst, bits<8> buf2inst, bits<8> buf3inst> {
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// Stream0
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def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 1),
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(i32 imm:$type), (i32 imm:$arraybase), (i32 imm:$mask)),
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(ExportInst R600_Reg128:$src, imm:$type, imm:$arraybase,
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def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
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(i32 imm:$arraybase), (i32 0), (i32 imm:$mask)),
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(ExportInst R600_Reg128:$src, 0, imm:$arraybase,
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4095, imm:$mask, buf0inst, 0)>;
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// Stream1
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def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 2),
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(i32 imm:$type), (i32 imm:$arraybase), (i32 imm:$mask)),
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(ExportInst R600_Reg128:$src, imm:$type, imm:$arraybase,
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def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
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(i32 imm:$arraybase), (i32 1), (i32 imm:$mask)),
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(ExportInst R600_Reg128:$src, 0, imm:$arraybase,
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4095, imm:$mask, buf1inst, 0)>;
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// Stream2
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def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 3),
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(i32 imm:$type), (i32 imm:$arraybase), (i32 imm:$mask)),
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(ExportInst R600_Reg128:$src, imm:$type, imm:$arraybase,
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def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
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(i32 imm:$arraybase), (i32 2), (i32 imm:$mask)),
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(ExportInst R600_Reg128:$src, 0, imm:$arraybase,
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4095, imm:$mask, buf2inst, 0)>;
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// Stream3
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def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 4),
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(i32 imm:$type), (i32 imm:$arraybase), (i32 imm:$mask)),
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(ExportInst R600_Reg128:$src, imm:$type, imm:$arraybase,
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def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
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(i32 imm:$arraybase), (i32 3), (i32 imm:$mask)),
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(ExportInst R600_Reg128:$src, 0, imm:$arraybase,
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4095, imm:$mask, buf3inst, 0)>;
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}
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@ -20,7 +20,7 @@ let TargetPrefix = "R600", isTarget = 1 in {
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def int_R600_load_input_linear :
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Intrinsic<[llvm_float_ty], [llvm_i32_ty], [IntrReadMem]>;
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def int_R600_store_stream_output :
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Intrinsic<[], [llvm_float_ty, llvm_i32_ty, llvm_i32_ty], []>;
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Intrinsic<[], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
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def int_R600_store_pixel_color :
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Intrinsic<[], [llvm_float_ty, llvm_i32_ty], []>;
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def int_R600_store_pixel_depth :
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@ -17,7 +17,6 @@ R600MachineFunctionInfo::R600MachineFunctionInfo(const MachineFunction &MF)
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HasLinearInterpolation(false),
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HasPerspectiveInterpolation(false) {
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memset(Outputs, 0, sizeof(Outputs));
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memset(StreamOutputs, 0, sizeof(StreamOutputs));
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}
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unsigned R600MachineFunctionInfo::GetIJPerspectiveIndex() const {
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@ -25,7 +25,6 @@ public:
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R600MachineFunctionInfo(const MachineFunction &MF);
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std::vector<unsigned> ReservedRegs;
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SDNode *Outputs[16];
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SDNode *StreamOutputs[64][4];
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bool HasLinearInterpolation;
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bool HasPerspectiveInterpolation;
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