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[SystemZ] Enable machine scheduler.

Browse Source 
The machine scheduler (before register allocation) is enabled by default for
SystemZ.

The SelectionDAG scheduling preference now becomes source order scheduling
(was regpressure).

Review: Ulrich Weigand
https://reviews.llvm.org/D37977

llvm-svn: 315063
This commit is contained in:
Jonas Paulsson 2017-10-06 13:59:28 +00:00
parent b8be700ed7
commit 4b6f06420e
46 changed files with 1338 additions and 9004 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
lib/Target/SystemZ/SystemZSubtarget.h
View File

@ -91,6 +91,11 @@ public:
return &TSInfo;
}
// True if the subtarget should run MachineScheduler after aggressive
// coalescing. This currently replaces the SelectionDAG scheduler with the
// "source" order scheduler.
bool enableMachineScheduler() const override { return true; }
// This is important for reducing register pressure in vector code.
bool useAA() const override { return true; }

10
test/CodeGen/SystemZ/alloca-01.ll
View File

@ -13,6 +13,10 @@ declare i64 @bar(i8 *%a, i8 *%b, i8 *%c, i8 *%d, i8 *%e, i64 %f, i64 %g)
; Allocate %length bytes and take addresses based on the result.
; There are two stack arguments, so an offset of 160 + 2 * 8 == 176
; is added to the copy of %r15.
;
; NOTE: 'la %r0, 177(%r1)' is actually an expected fail as it would
; be better (and possible) to load into %r3 directly.
;
define i64 @f1(i64 %length, i64 %index) {
; FIXME: a better sequence would be:
;
@ -29,12 +33,12 @@ define i64 @f1(i64 %length, i64 %index) {
; CHECK: lgr %r15, [[REG2]]
;
; CHECK-A-LABEL: f1:
; CHECK-A: lgr %r15, %r1
; CHECK-A: la %r2, 176(%r1)
; CHECK-A-DAG: lgr %r15, %r1
; CHECK-A-DAG: la %r2, 176(%r1)
;
; CHECK-B-LABEL: f1:
; CHECK-B: lgr %r15, %r1
; CHECK-B: la %r3, 177(%r1)
; CHECK-B: la %r0, 177(%r1)
;
; CHECK-C-LABEL: f1:
; CHECK-C: lgr %r15, %r1

14
test/CodeGen/SystemZ/alloca-02.ll
View File

@ -10,29 +10,29 @@ declare i64 @bar(i8 *%a)
define i64 @f1(i64 %length, i64 %index) {
; CHECK-A-LABEL: f1:
; CHECK-A: lgr %r15, [[ADDR:%r[1-5]]]
; CHECK-A: la %r2, 160([[ADDR]])
; CHECK-A-DAG: lgr %r15, [[ADDR:%r[1-5]]]
; CHECK-A-DAG: la %r2, 160([[ADDR]])
; CHECK-A: mvi 0(%r2), 0
;
; CHECK-B-LABEL: f1:
; CHECK-B: lgr %r15, [[ADDR:%r[1-5]]]
; CHECK-B: la %r2, 160([[ADDR]])
; CHECK-B-DAG: lgr %r15, [[ADDR:%r[1-5]]]
; CHECK-B-DAG: la %r2, 160([[ADDR]])
; CHECK-B: mvi 4095(%r2), 1
;
; CHECK-C-LABEL: f1:
; CHECK-C: lgr %r15, [[ADDR:%r[1-5]]]
; CHECK-C-DAG: lgr %r15, [[ADDR:%r[1-5]]]
; CHECK-C-DAG: la %r2, 160([[ADDR]])
; CHECK-C-DAG: lhi [[TMP:%r[0-5]]], 2
; CHECK-C: stc [[TMP]], 0({{%r3,%r2|%r2,%r3}})
;
; CHECK-D-LABEL: f1:
; CHECK-D: lgr %r15, [[ADDR:%r[1-5]]]
; CHECK-D-DAG: lgr %r15, [[ADDR:%r[1-5]]]
; CHECK-D-DAG: la %r2, 160([[ADDR]])
; CHECK-D-DAG: lhi [[TMP:%r[0-5]]], 3
; CHECK-D: stc [[TMP]], 4095({{%r3,%r2|%r2,%r3}})
;
; CHECK-E-LABEL: f1:
; CHECK-E: lgr %r15, [[ADDR:%r[1-5]]]
; CHECK-E-DAG: lgr %r15, [[ADDR:%r[1-5]]]
; CHECK-E-DAG: la %r2, 160([[ADDR]])
; CHECK-E-DAG: lhi [[TMP:%r[0-5]]], 4
; CHECK-E: stcy [[TMP]], 4096({{%r3,%r2|%r2,%r3}})

36
test/CodeGen/SystemZ/alloca-03.ll
View File

@ -15,13 +15,13 @@ define void @f0() {
; Allocate %len * 8, no need to align stack.
define void @f1(i64 %len) {
; CHECK-LABEL: f1:
; CHECK: sllg %r0, %r2, 3
; CHECK: lgr %r1, %r15
; CHECK-DAG: sllg %r0, %r2, 3
; CHECK-DAG: lgr %r1, %r15
; CHECK: sgr %r1, %r0
; CHECK-NOT: ngr
; CHECK: lgr %r15, %r1
; CHECK: la %r1, 160(%r1)
; CHECK: mvghi 0(%r1), 10
; CHECK-DAG: lgr %r15, %r1
; CHECK-DAG: la %r2, 160(%r1)
; CHECK: mvghi 0(%r2), 10
%x = alloca i64, i64 %len
store volatile i64 10, i64* %x
ret void
@ -31,10 +31,10 @@ define void @f1(i64 %len) {
define void @f2() {
; CHECK-LABEL: f2:
; CHECK: aghi %r1, -128
; CHECK: lgr %r15, %r1
; CHECK: la %r1, 280(%r1)
; CHECK: nill %r1, 65408
; CHECK: mvghi 0(%r1), 10
; CHECK-DAG: lgr %r15, %r1
; CHECK-DAG: la %r2, 280(%r1)
; CHECK-DAG: nill %r2, 65408
; CHECK: mvghi 0(%r2), 10
%x = alloca i64, i64 1, align 128
store volatile i64 10, i64* %x, align 128
ret void
@ -43,14 +43,14 @@ define void @f2() {
; Dynamic alloca, align 128.
define void @f3(i64 %len) {
; CHECK-LABEL: f3:
; CHECK: sllg %r1, %r2, 3
; CHECK: la %r0, 120(%r1)
; CHECK: lgr %r1, %r15
; CHECK-DAG: sllg %r2, %r2, 3
; CHECK-DAG: la %r0, 120(%r2)
; CHECK-DAG: lgr %r1, %r15
; CHECK: sgr %r1, %r0
; CHECK: la %r2, 280(%r1)
; CHECK: nill %r2, 65408
; CHECK: lgr %r15, %r1
; CHECK: la %r1, 280(%r1)
; CHECK: nill %r1, 65408
; CHECK: mvghi 0(%r1), 10
; CHECK: mvghi 0(%r2), 10
%x = alloca i64, i64 %len, align 128
store volatile i64 10, i64* %x, align 128
ret void
@ -73,10 +73,10 @@ define void @f5() {
; CHECK: lgr %r1, %r15
; CHECK: aghi %r1, -128
; CHECK: la %r2, 280(%r1)
; CHECK: nill %r2, 65408
; CHECK: lgr %r15, %r1
; CHECK: la %r1, 280(%r1)
; CHECK: nill %r1, 65408
; CHECK: mvhi 0(%r1), 10
; CHECK: mvhi 0(%r2), 10
%x = alloca i32, i64 1, align 128
store volatile i32 10, i32* %x
ret void

4
test/CodeGen/SystemZ/args-06.ll
View File

@ -5,12 +5,12 @@
define i8 @f1(i8 %a, i8 %b, i8 %c, i8 %d, i8 %e, i8 %f, i8 %g) {
; CHECK-LABEL: f1:
; CHECK: lb {{%r[0-5]}}, 175(%r15)
; CHECK: lb {{%r[0-5]}}, 167(%r15)
; CHECK: ar %r2, %r3
; CHECK: ar %r2, %r4
; CHECK: ar %r2, %r5
; CHECK: ar %r2, %r6
; CHECK: lb {{%r[0-5]}}, 167(%r15)
; CHECK: lb {{%r[0-5]}}, 175(%r15)
; CHECK: br %r14
%addb = add i8 %a, %b
%addc = add i8 %addb, %c

8
test/CodeGen/SystemZ/atomicrmw-add-01.ll
View File

@ -15,8 +15,8 @@
define i8 @f1(i8 *%src, i8 %b) {
; CHECK-LABEL: f1:
; CHECK: risbg %r1, %r2, 0, 189, 0{{$}}
; CHECK: sll [[SHIFT:%r[0-9]+]], 3
; CHECK: l [[OLD:%r[0-9]+]], 0(%r1)
; CHECK-DAG: sll [[SHIFT:%r[0-9]+]], 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0(%r1)
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
; CHECK: ar [[ROT]], %r3
@ -49,8 +49,8 @@ define i8 @f1(i8 *%src, i8 %b) {
define i8 @f2(i8 *%src) {
; CHECK-LABEL: f2:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: afi [[ROT]], -2147483648

8
test/CodeGen/SystemZ/atomicrmw-add-02.ll
View File

@ -15,8 +15,8 @@
define i16 @f1(i16 *%src, i16 %b) {
; CHECK-LABEL: f1:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: ar [[ROT]], %r3
@ -49,8 +49,8 @@ define i16 @f1(i16 *%src, i16 %b) {
define i16 @f2(i16 *%src) {
; CHECK-LABEL: f2:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: afi [[ROT]], -2147483648

4
test/CodeGen/SystemZ/atomicrmw-and-01.ll
View File

@ -49,8 +49,8 @@ define i8 @f1(i8 *%src, i8 %b) {
define i8 @f2(i8 *%src) {
; CHECK-LABEL: f2:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: nilh [[ROT]], 33023

8
test/CodeGen/SystemZ/atomicrmw-and-02.ll
View File

@ -15,8 +15,8 @@
define i16 @f1(i16 *%src, i16 %b) {
; CHECK-LABEL: f1:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: nr [[ROT]], %r3
@ -50,8 +50,8 @@ define i16 @f1(i16 *%src, i16 %b) {
define i16 @f2(i16 *%src) {
; CHECK-LABEL: f2:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: nilh [[ROT]], 32768

16
test/CodeGen/SystemZ/atomicrmw-minmax-01.ll
View File

@ -15,8 +15,8 @@
define i8 @f1(i8 *%src, i8 %b) {
; CHECK-LABEL: f1:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LOOP:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: crjle [[ROT]], %r3, [[KEEP:\..*]]
@ -51,8 +51,8 @@ define i8 @f1(i8 *%src, i8 %b) {
define i8 @f2(i8 *%src, i8 %b) {
; CHECK-LABEL: f2:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LOOP:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: crjhe [[ROT]], %r3, [[KEEP:\..*]]
@ -87,8 +87,8 @@ define i8 @f2(i8 *%src, i8 %b) {
define i8 @f3(i8 *%src, i8 %b) {
; CHECK-LABEL: f3:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LOOP:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: clrjle [[ROT]], %r3, [[KEEP:\..*]]
@ -123,8 +123,8 @@ define i8 @f3(i8 *%src, i8 %b) {
define i8 @f4(i8 *%src, i8 %b) {
; CHECK-LABEL: f4:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LOOP:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: clrjhe [[ROT]], %r3, [[KEEP:\..*]]

16
test/CodeGen/SystemZ/atomicrmw-minmax-02.ll
View File

@ -15,8 +15,8 @@
define i16 @f1(i16 *%src, i16 %b) {
; CHECK-LABEL: f1:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LOOP:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: crjle [[ROT]], %r3, [[KEEP:\..*]]
@ -51,8 +51,8 @@ define i16 @f1(i16 *%src, i16 %b) {
define i16 @f2(i16 *%src, i16 %b) {
; CHECK-LABEL: f2:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LOOP:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: crjhe [[ROT]], %r3, [[KEEP:\..*]]
@ -87,8 +87,8 @@ define i16 @f2(i16 *%src, i16 %b) {
define i16 @f3(i16 *%src, i16 %b) {
; CHECK-LABEL: f3:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LOOP:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: clrjle [[ROT]], %r3, [[KEEP:\..*]]
@ -123,8 +123,8 @@ define i16 @f3(i16 *%src, i16 %b) {
define i16 @f4(i16 *%src, i16 %b) {
; CHECK-LABEL: f4:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LOOP:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: clrjhe [[ROT]], %r3, [[KEEP:\..*]]

4
test/CodeGen/SystemZ/atomicrmw-minmax-04.ll
View File

@ -133,8 +133,8 @@ define i64 @f9(i64 %dummy, i64 %base, i64 %index, i64 %b) {
; Check that constants are handled.
define i64 @f10(i64 %dummy, i64 *%ptr) {
; CHECK-LABEL: f10:
; CHECK: lghi [[LIMIT:%r[0-9]+]], 42
; CHECK: lg %r2, 0(%r3)
; CHECK-DAG: lghi [[LIMIT:%r[0-9]+]], 42
; CHECK-DAG: lg %r2, 0(%r3)
; CHECK: j [[LOOP:\.[^:]*]]
; CHECK: [[BB1:\.[^:]*]]:
; CHECK: csg %r2, [[NEW:%r[0-9]+]], 0(%r3)

8
test/CodeGen/SystemZ/atomicrmw-nand-01.ll
View File

@ -15,8 +15,8 @@
define i8 @f1(i8 *%src, i8 %b) {
; CHECK-LABEL: f1:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: nr [[ROT]], %r3
@ -51,8 +51,8 @@ define i8 @f1(i8 *%src, i8 %b) {
define i8 @f2(i8 *%src) {
; CHECK-LABEL: f2:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: nilh [[ROT]], 33023

8
test/CodeGen/SystemZ/atomicrmw-nand-02.ll
View File

@ -15,8 +15,8 @@
define i16 @f1(i16 *%src, i16 %b) {
; CHECK-LABEL: f1:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: nr [[ROT]], %r3
@ -51,8 +51,8 @@ define i16 @f1(i16 *%src, i16 %b) {
define i16 @f2(i16 *%src) {
; CHECK-LABEL: f2:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: nilh [[ROT]], 32768

8
test/CodeGen/SystemZ/atomicrmw-or-01.ll
View File

@ -15,8 +15,8 @@
define i8 @f1(i8 *%src, i8 %b) {
; CHECK-LABEL: f1:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: or [[ROT]], %r3
@ -49,8 +49,8 @@ define i8 @f1(i8 *%src, i8 %b) {
define i8 @f2(i8 *%src) {
; CHECK-LABEL: f2:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: oilh [[ROT]], 32768

8
test/CodeGen/SystemZ/atomicrmw-or-02.ll
View File

@ -15,8 +15,8 @@
define i16 @f1(i16 *%src, i16 %b) {
; CHECK-LABEL: f1:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: or [[ROT]], %r3
@ -49,8 +49,8 @@ define i16 @f1(i16 *%src, i16 %b) {
define i16 @f2(i16 *%src) {
; CHECK-LABEL: f2:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: oilh [[ROT]], 32768

8
test/CodeGen/SystemZ/atomicrmw-sub-01.ll
View File

@ -15,8 +15,8 @@
define i8 @f1(i8 *%src, i8 %b) {
; CHECK-LABEL: f1:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: sr [[ROT]], %r3
@ -49,8 +49,8 @@ define i8 @f1(i8 *%src, i8 %b) {
define i8 @f2(i8 *%src) {
; CHECK-LABEL: f2:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: afi [[ROT]], -2147483648

8
test/CodeGen/SystemZ/atomicrmw-sub-02.ll
View File

@ -15,8 +15,8 @@
define i16 @f1(i16 *%src, i16 %b) {
; CHECK-LABEL: f1:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: sr [[ROT]], %r3
@ -49,8 +49,8 @@ define i16 @f1(i16 *%src, i16 %b) {
define i16 @f2(i16 *%src) {
; CHECK-LABEL: f2:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: afi [[ROT]], -2147483648

4
test/CodeGen/SystemZ/atomicrmw-xchg-01.ll
View File

@ -13,8 +13,8 @@
define i8 @f1(i8 *%src, i8 %b) {
; CHECK-LABEL: f1:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: risbg [[ROT]], %r3, 32, 39, 24

4
test/CodeGen/SystemZ/atomicrmw-xchg-02.ll
View File

@ -13,8 +13,8 @@
define i16 @f1(i16 *%src, i16 %b) {
; CHECK-LABEL: f1:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: risbg [[ROT]], %r3, 32, 47, 16

4
test/CodeGen/SystemZ/atomicrmw-xchg-03.ll
View File

@ -110,8 +110,8 @@ define i32 @f9(i32 %dummy, i64 %base, i64 %index, i32 %b) {
; use the sequence above.
define i32 @f10(i32 %dummy, i32 *%src) {
; CHECK-LABEL: f10:
; CHECK: llill [[VALUE:%r[0-9+]]], 40000
; CHECK: l %r2, 0(%r3)
; CHECK-DAG: llill [[VALUE:%r[0-9+]]], 40000
; CHECK-DAG: l %r2, 0(%r3)
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: cs %r2, [[VALUE]], 0(%r3)
; CHECK: jl [[LABEL]]

4
test/CodeGen/SystemZ/atomicrmw-xchg-04.ll
View File

@ -77,8 +77,8 @@ define i64 @f6(i64 %dummy, i64 %base, i64 %index, i64 %b) {
; use the sequence above.
define i64 @f7(i64 %dummy, i64 *%ptr) {
; CHECK-LABEL: f7:
; CHECK: llilf [[VALUE:%r[0-9+]]], 3000000000
; CHECK: lg %r2, 0(%r3)
; CHECK-DAG: llilf [[VALUE:%r[0-9+]]], 3000000000
; CHECK-DAG: lg %r2, 0(%r3)
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: csg %r2, [[VALUE]], 0(%r3)
; CHECK: jl [[LABEL]]

8
test/CodeGen/SystemZ/atomicrmw-xor-01.ll
View File

@ -15,8 +15,8 @@
define i8 @f1(i8 *%src, i8 %b) {
; CHECK-LABEL: f1:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: xr [[ROT]], %r3
@ -49,8 +49,8 @@ define i8 @f1(i8 *%src, i8 %b) {
define i8 @f2(i8 *%src) {
; CHECK-LABEL: f2:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: xilf [[ROT]], 2147483648

8
test/CodeGen/SystemZ/atomicrmw-xor-02.ll
View File

@ -15,8 +15,8 @@
define i16 @f1(i16 *%src, i16 %b) {
; CHECK-LABEL: f1:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: xr [[ROT]], %r3
@ -49,8 +49,8 @@ define i16 @f1(i16 *%src, i16 %b) {
define i16 @f2(i16 *%src) {
; CHECK-LABEL: f2:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: xilf [[ROT]], 2147483648

24
test/CodeGen/SystemZ/backchain.ll
View File

@ -60,18 +60,18 @@ define void @f5(i32 %count1, i32 %count2) "backchain" {
; CHECK: aghi %r15, -160
; CHECK: stg %r1, 0(%r15)
; CHECK: lgr %r11, %r15
; CHECK: lgr [[SAVESP:%r[0-9]+]], %r15
; CHECK: lg [[BC:%r[0-9]+]], 0(%r15)
; CHECK: lgr [[NEWSP:%r[0-9]+]], %r15
; CHECK: lgr %r15, [[NEWSP]]
; CHECK: stg [[BC]], 0([[NEWSP]])
; CHECK: lg [[BC2:%r[0-9]+]], 0(%r15)
; CHECK: lgr %r15, [[SAVESP]]
; CHECK: stg [[BC2]], 0([[SAVESP]])
; CHECK: lg [[BC3:%r[0-9]+]], 0(%r15)
; CHECK: lgr [[NEWSP2:%r[0-9]+]], %r15
; CHECK: lgr %r15, [[NEWSP2]]
; CHECK: stg [[BC3]], 0([[NEWSP2]])
; CHECK-DAG: lgr [[SAVESP:%r[0-9]+]], %r15
; CHECK-DAG: lg [[BC:%r[0-9]+]], 0(%r15)
; CHECK-DAG: lgr [[NEWSP:%r[0-9]+]], %r15
; CHECK-DAG: lgr %r15, [[NEWSP]]
; CHECK-DAG: stg [[BC]], 0([[NEWSP]])
; CHECK-DAG: lg [[BC2:%r[0-9]+]], 0(%r15)
; CHECK-DAG: lgr %r15, [[SAVESP]]
; CHECK-DAG: stg [[BC2]], 0([[SAVESP]])
; CHECK-DAG: lg [[BC3:%r[0-9]+]], 0(%r15)
; CHECK-DAG: lgr [[NEWSP2:%r[0-9]+]], %r15
; CHECK-DAG: lgr %r15, [[NEWSP2]]
; CHECK-DAG: stg [[BC3]], 0([[NEWSP2]])
; CHECK: lmg %r11, %r15, 248(%r11)
; CHECK: br %r14
%src = call i8 *@llvm.stacksave()

5
test/CodeGen/SystemZ/call-03.ll
View File

@ -62,13 +62,16 @@ define void @f4() {
; Check an indirect call. In this case the only acceptable choice for
; the target register is %r1.
;
; NOTE: the extra copy 'lgr %r1, %r0' is a coalescing failure.
define void @f5(void(i32, i32, i32, i32) *%foo) {
; CHECK-LABEL: f5:
; CHECK: lgr %r1, %r2
; CHECK: lgr %r0, %r2
; CHECK-DAG: lhi %r2, 1
; CHECK-DAG: lhi %r3, 2
; CHECK-DAG: lhi %r4, 3
; CHECK-DAG: lhi %r5, 4
; CHECK: lgr %r1, %r0
; CHECK: br %r1
tail call void %foo(i32 1, i32 2, i32 3, i32 4)
ret void

8
test/CodeGen/SystemZ/cmpxchg-01.ll
View File

@ -13,8 +13,8 @@
define i8 @f1(i8 %dummy, i8 *%src, i8 %cmp, i8 %swap) {
; CHECK-MAIN-LABEL: f1:
; CHECK-MAIN: risbg [[RISBG:%r[1-9]+]], %r3, 0, 189, 0{{$}}
; CHECK-MAIN: sll %r3, 3
; CHECK-MAIN: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-MAIN-DAG: sll %r3, 3
; CHECK-MAIN-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-MAIN: [[LOOP:\.[^ ]*]]:
; CHECK-MAIN: rll %r2, [[OLD]], 8(%r3)
; CHECK-MAIN: risbg %r4, %r2, 32, 55, 0
@ -60,8 +60,8 @@ define i8 @f2(i8 *%src) {
define i32 @f3(i8 %dummy, i8 *%src, i8 %cmp, i8 %swap) {
; CHECK-MAIN-LABEL: f3:
; CHECK-MAIN: risbg [[RISBG:%r[1-9]+]], %r3, 0, 189, 0{{$}}
; CHECK-MAIN: sll %r3, 3
; CHECK-MAIN: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-MAIN-DAG: sll %r3, 3
; CHECK-MAIN-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-MAIN: [[LOOP:\.[^ ]*]]:
; CHECK-MAIN: rll [[TMP:%r[0-9]+]], [[OLD]], 8(%r3)
; CHECK-MAIN: risbg %r4, [[TMP]], 32, 55, 0

8
test/CodeGen/SystemZ/cmpxchg-02.ll
View File

@ -13,8 +13,8 @@
define i16 @f1(i16 %dummy, i16 *%src, i16 %cmp, i16 %swap) {
; CHECK-MAIN-LABEL: f1:
; CHECK-MAIN: risbg [[RISBG:%r[1-9]+]], %r3, 0, 189, 0{{$}}
; CHECK-MAIN: sll %r3, 3
; CHECK-MAIN: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-MAIN-DAG: sll %r3, 3
; CHECK-MAIN-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-MAIN: [[LOOP:\.[^ ]*]]:
; CHECK-MAIN: rll %r2, [[OLD]], 16(%r3)
; CHECK-MAIN: risbg %r4, %r2, 32, 47, 0
@ -60,8 +60,8 @@ define i16 @f2(i16 *%src) {
define i32 @f3(i16 %dummy, i16 *%src, i16 %cmp, i16 %swap) {
; CHECK-MAIN-LABEL: f3:
; CHECK-MAIN: risbg [[RISBG:%r[1-9]+]], %r3, 0, 189, 0{{$}}
; CHECK-MAIN: sll %r3, 3
; CHECK-MAIN: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-MAIN-DAG: sll %r3, 3
; CHECK-MAIN-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-MAIN: [[LOOP:\.[^ ]*]]:
; CHECK-MAIN: rll [[TMP:%r[0-9]+]], [[OLD]], 16(%r3)
; CHECK-MAIN: risbg %r4, [[TMP]], 32, 47, 0

12
test/CodeGen/SystemZ/fp-add-03.ll
View File

@ -5,12 +5,12 @@
; There is no memory form of 128-bit addition.
define void @f1(fp128 *%ptr, float %f2) {
; CHECK-LABEL: f1:
; CHECK: lxebr %f0, %f0
; CHECK: ld %f1, 0(%r2)
; CHECK: ld %f3, 8(%r2)
; CHECK: axbr %f1, %f0
; CHECK: std %f1, 0(%r2)
; CHECK: std %f3, 8(%r2)
; CHECK-DAG: lxebr %f0, %f0
; CHECK-DAG: ld %f1, 0(%r2)
; CHECK-DAG: ld %f3, 8(%r2)
; CHECK: axbr %f0, %f1
; CHECK: std %f0, 0(%r2)
; CHECK: std %f2, 8(%r2)
; CHECK: br %r14
%f1 = load fp128 , fp128 *%ptr
%f2x = fpext float %f2 to fp128

6
test/CodeGen/SystemZ/fp-cmp-03.ll
View File

@ -6,9 +6,9 @@
; There is no memory form of 128-bit comparison.
define i64 @f1(i64 %a, i64 %b, fp128 *%ptr, float %f2) {
; CHECK-LABEL: f1:
; CHECK: lxebr %f0, %f0
; CHECK: ld %f1, 0(%r4)
; CHECK: ld %f3, 8(%r4)
; CHECK-DAG: lxebr %f0, %f0
; CHECK-DAG: ld %f1, 0(%r4)
; CHECK-DAG: ld %f3, 8(%r4)
; CHECK: cxbr %f1, %f0
; CHECK-NEXT: ber %r14
; CHECK: lgr %r2, %r3

4
test/CodeGen/SystemZ/fp-cmp-04.ll
View File

@ -208,8 +208,8 @@ define float @f11(float %a, float %b, float %c, float *%dest1, float *%dest2) {
; CHECK-LABEL: f11:
; CHECK: aebr %f0, %f2
; CHECK-NEXT: sebr %f4, %f0
; CHECK-NEXT: ste %f4, 0(%r2)
; CHECK-NEXT: ltebr %f0, %f0
; CHECK-DAG: ste %f4, 0(%r2)
; CHECK-DAG: ltebr %f0, %f0
; CHECK-NEXT: ber %r14
; CHECK: br %r14
entry:

80
test/CodeGen/SystemZ/fp-conv-02.ll
View File

@ -72,83 +72,3 @@ define double @f6(float *%base, i64 %index) {
ret double %res
}
; Test a case where we spill the source of at least one LDEBR. We want
; to use LDEB if possible.
define void @f7(double *%ptr1, float *%ptr2) {
; CHECK-LABEL: f7:
; CHECK-SCALAR: ldeb {{%f[0-9]+}}, 16{{[04]}}(%r15)
; CHECK: br %r14
%val0 = load volatile float , float *%ptr2
%val1 = load volatile float , float *%ptr2
%val2 = load volatile float , float *%ptr2
%val3 = load volatile float , float *%ptr2
%val4 = load volatile float , float *%ptr2
%val5 = load volatile float , float *%ptr2
%val6 = load volatile float , float *%ptr2
%val7 = load volatile float , float *%ptr2
%val8 = load volatile float , float *%ptr2
%val9 = load volatile float , float *%ptr2
%val10 = load volatile float , float *%ptr2
%val11 = load volatile float , float *%ptr2
%val12 = load volatile float , float *%ptr2
%val13 = load volatile float , float *%ptr2
%val14 = load volatile float , float *%ptr2
%val15 = load volatile float , float *%ptr2
%val16 = load volatile float , float *%ptr2
%ext0 = fpext float %val0 to double
%ext1 = fpext float %val1 to double
%ext2 = fpext float %val2 to double
%ext3 = fpext float %val3 to double
%ext4 = fpext float %val4 to double
%ext5 = fpext float %val5 to double
%ext6 = fpext float %val6 to double
%ext7 = fpext float %val7 to double
%ext8 = fpext float %val8 to double
%ext9 = fpext float %val9 to double
%ext10 = fpext float %val10 to double
%ext11 = fpext float %val11 to double
%ext12 = fpext float %val12 to double
%ext13 = fpext float %val13 to double
%ext14 = fpext float %val14 to double
%ext15 = fpext float %val15 to double
%ext16 = fpext float %val16 to double
store volatile float %val0, float *%ptr2
store volatile float %val1, float *%ptr2
store volatile float %val2, float *%ptr2
store volatile float %val3, float *%ptr2
store volatile float %val4, float *%ptr2
store volatile float %val5, float *%ptr2
store volatile float %val6, float *%ptr2
store volatile float %val7, float *%ptr2
store volatile float %val8, float *%ptr2
store volatile float %val9, float *%ptr2
store volatile float %val10, float *%ptr2
store volatile float %val11, float *%ptr2
store volatile float %val12, float *%ptr2
store volatile float %val13, float *%ptr2
store volatile float %val14, float *%ptr2
store volatile float %val15, float *%ptr2
store volatile float %val16, float *%ptr2
store volatile double %ext0, double *%ptr1
store volatile double %ext1, double *%ptr1
store volatile double %ext2, double *%ptr1
store volatile double %ext3, double *%ptr1
store volatile double %ext4, double *%ptr1
store volatile double %ext5, double *%ptr1
store volatile double %ext6, double *%ptr1
store volatile double %ext7, double *%ptr1
store volatile double %ext8, double *%ptr1
store volatile double %ext9, double *%ptr1
store volatile double %ext10, double *%ptr1
store volatile double %ext11, double *%ptr1
store volatile double %ext12, double *%ptr1
store volatile double %ext13, double *%ptr1
store volatile double %ext14, double *%ptr1
store volatile double %ext15, double *%ptr1
store volatile double %ext16, double *%ptr1
ret void
}

202
test/CodeGen/SystemZ/fp-conv-17.mir Normal file
View File

@ -0,0 +1,202 @@
# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z10 -start-before=greedy %s -o - \
# RUN: | FileCheck %s
--- |
define void @f0(double* %ptr1, float* %ptr2) {
%val0 = load volatile float, float* %ptr2
%val1 = load volatile float, float* %ptr2
%val2 = load volatile float, float* %ptr2
%val3 = load volatile float, float* %ptr2
%val4 = load volatile float, float* %ptr2
%val5 = load volatile float, float* %ptr2
%val6 = load volatile float, float* %ptr2
%val7 = load volatile float, float* %ptr2
%val8 = load volatile float, float* %ptr2
%val9 = load volatile float, float* %ptr2
%val10 = load volatile float, float* %ptr2
%val11 = load volatile float, float* %ptr2
%val12 = load volatile float, float* %ptr2
%val13 = load volatile float, float* %ptr2
%val14 = load volatile float, float* %ptr2
%val15 = load volatile float, float* %ptr2
%val16 = load volatile float, float* %ptr2
%ext0 = fpext float %val0 to double
%ext1 = fpext float %val1 to double
%ext2 = fpext float %val2 to double
%ext3 = fpext float %val3 to double
%ext4 = fpext float %val4 to double
%ext5 = fpext float %val5 to double
%ext6 = fpext float %val6 to double
%ext7 = fpext float %val7 to double
%ext8 = fpext float %val8 to double
%ext9 = fpext float %val9 to double
%ext10 = fpext float %val10 to double
%ext11 = fpext float %val11 to double
%ext12 = fpext float %val12 to double
%ext13 = fpext float %val13 to double
%ext14 = fpext float %val14 to double
%ext15 = fpext float %val15 to double
%ext16 = fpext float %val16 to double
store volatile float %val0, float* %ptr2
store volatile float %val1, float* %ptr2
store volatile float %val2, float* %ptr2
store volatile float %val3, float* %ptr2
store volatile float %val4, float* %ptr2
store volatile float %val5, float* %ptr2
store volatile float %val6, float* %ptr2
store volatile float %val7, float* %ptr2
store volatile float %val8, float* %ptr2
store volatile float %val9, float* %ptr2
store volatile float %val10, float* %ptr2
store volatile float %val11, float* %ptr2
store volatile float %val12, float* %ptr2
store volatile float %val13, float* %ptr2
store volatile float %val14, float* %ptr2
store volatile float %val15, float* %ptr2
store volatile float %val16, float* %ptr2
store volatile double %ext0, double* %ptr1
store volatile double %ext1, double* %ptr1
store volatile double %ext2, double* %ptr1
store volatile double %ext3, double* %ptr1
store volatile double %ext4, double* %ptr1
store volatile double %ext5, double* %ptr1
store volatile double %ext6, double* %ptr1
store volatile double %ext7, double* %ptr1
store volatile double %ext8, double* %ptr1
store volatile double %ext9, double* %ptr1
store volatile double %ext10, double* %ptr1
store volatile double %ext11, double* %ptr1
store volatile double %ext12, double* %ptr1
store volatile double %ext13, double* %ptr1
store volatile double %ext14, double* %ptr1
store volatile double %ext15, double* %ptr1
store volatile double %ext16, double* %ptr1
ret void
}
...
# CHECK-LABEL: f0:
# CHECK: ldeb {{%f[0-9]+}}, 16{{[04]}}(%r15)
# CHECK: br %r14
---
name: f0
alignment: 2
tracksRegLiveness: true
registers:
- { id: 0, class: addr64bit }
- { id: 1, class: addr64bit }
- { id: 2, class: fp32bit }
- { id: 3, class: fp32bit }
- { id: 4, class: fp32bit }
- { id: 5, class: fp32bit }
- { id: 6, class: fp32bit }
- { id: 7, class: fp32bit }
- { id: 8, class: fp32bit }
- { id: 9, class: fp32bit }
- { id: 10, class: fp32bit }
- { id: 11, class: fp32bit }
- { id: 12, class: fp32bit }
- { id: 13, class: fp32bit }
- { id: 14, class: fp32bit }
- { id: 15, class: fp32bit }
- { id: 16, class: fp32bit }
- { id: 17, class: fp32bit }
- { id: 18, class: fp32bit }
- { id: 19, class: fp64bit }
- { id: 20, class: fp64bit }
- { id: 21, class: fp64bit }
- { id: 22, class: fp64bit }
- { id: 23, class: fp64bit }
- { id: 24, class: fp64bit }
- { id: 25, class: fp64bit }
- { id: 26, class: fp64bit }
- { id: 27, class: fp64bit }
- { id: 28, class: fp64bit }
- { id: 29, class: fp64bit }
- { id: 30, class: fp64bit }
- { id: 31, class: fp64bit }
- { id: 32, class: fp64bit }
- { id: 33, class: fp64bit }
- { id: 34, class: fp64bit }
- { id: 35, class: fp64bit }
liveins:
- { reg: '%r2d', virtual-reg: '%0' }
- { reg: '%r3d', virtual-reg: '%1' }
body: |
bb.0 (%ir-block.0):
liveins: %r2d, %r3d
%1 = COPY %r3d
%0 = COPY %r2d
%2 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
%3 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
%4 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
%5 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
%6 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
%7 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
%8 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
%9 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
%10 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
%11 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
%12 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
%13 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
%14 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
%15 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
%16 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
%17 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
%18 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
STE %2, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
STE %3, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
STE %4, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
STE %5, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
STE %6, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
STE %7, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
STE %8, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
STE %9, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
STE %10, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
STE %11, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
STE %12, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
STE %13, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
STE %14, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
STE %15, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
STE %16, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
STE %17, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
STE %18, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
%19 = LDEBR %2
STD %19, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
%20 = LDEBR %3
STD %20, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
%21 = LDEBR %4
STD %21, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
%22 = LDEBR %5
STD %22, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
%23 = LDEBR %6
STD %23, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
%24 = LDEBR %7
STD %24, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
%25 = LDEBR %8
STD %25, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
%26 = LDEBR %9
STD %26, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
%27 = LDEBR %10
STD %27, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
%28 = LDEBR %11
STD %28, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
%29 = LDEBR %12
STD %29, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
%30 = LDEBR %13
STD %30, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
%31 = LDEBR %14
STD %31, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
%32 = LDEBR %15
STD %32, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
%33 = LDEBR %16
STD %33, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
%34 = LDEBR %17
STD %34, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
%35 = LDEBR %18
STD %35, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
Return
...

12
test/CodeGen/SystemZ/fp-copysign-02.ll
View File

@ -36,9 +36,9 @@ define void @f7(fp128 *%cptr, fp128 *%aptr, float %bf) {
; CHECK-LABEL: f7:
; CHECK: vl [[REG1:%v[0-7]+]], 0(%r3)
; CHECK: tmlh
; CHECK: wflnxb [[REG1]], [[REG1]]
; CHECK: wflpxb [[REG1]], [[REG1]]
; CHECK: vst [[REG1]], 0(%r2)
; CHECK: wflnxb [[REG2:%v[0-9]+]], [[REG1]]
; CHECK: wflpxb [[REG2]], [[REG1]]
; CHECK: vst [[REG2]], 0(%r2)
; CHECK: br %r14
%a = load volatile fp128, fp128 *%aptr
%b = fpext float %bf to fp128
@ -52,9 +52,9 @@ define void @f8(fp128 *%cptr, fp128 *%aptr, double %bd) {
; CHECK-LABEL: f8:
; CHECK: vl [[REG1:%v[0-7]+]], 0(%r3)
; CHECK: tmhh
; CHECK: wflnxb [[REG1]], [[REG1]]
; CHECK: wflpxb [[REG1]], [[REG1]]
; CHECK: vst [[REG1]], 0(%r2)
; CHECK: wflnxb [[REG2:%v[0-9]+]], [[REG1]]
; CHECK: wflpxb [[REG2]], [[REG1]]
; CHECK: vst [[REG2]], 0(%r2)
; CHECK: br %r14
%a = load volatile fp128, fp128 *%aptr
%b = fpext double %bd to fp128

6
test/CodeGen/SystemZ/fp-div-03.ll
View File

@ -5,9 +5,9 @@
; There is no memory form of 128-bit division.
define void @f1(fp128 *%ptr, float %f2) {
; CHECK-LABEL: f1:
; CHECK: lxebr %f0, %f0
; CHECK: ld %f1, 0(%r2)
; CHECK: ld %f3, 8(%r2)
; CHECK-DAG: lxebr %f0, %f0
; CHECK-DAG: ld %f1, 0(%r2)
; CHECK-DAG: ld %f3, 8(%r2)
; CHECK: dxbr %f1, %f0
; CHECK: std %f1, 0(%r2)
; CHECK: std %f3, 8(%r2)

12
test/CodeGen/SystemZ/fp-mul-05.ll
View File

@ -5,12 +5,12 @@
; There is no memory form of 128-bit multiplication.
define void @f1(fp128 *%ptr, float %f2) {
; CHECK-LABEL: f1:
; CHECK: lxebr %f0, %f0
; CHECK: ld %f1, 0(%r2)
; CHECK: ld %f3, 8(%r2)
; CHECK: mxbr %f1, %f0
; CHECK: std %f1, 0(%r2)
; CHECK: std %f3, 8(%r2)
; CHECK-DAG: lxebr %f0, %f0
; CHECK-DAG: ld %f1, 0(%r2)
; CHECK-DAG: ld %f3, 8(%r2)
; CHECK: mxbr %f0, %f1
; CHECK: std %f0, 0(%r2)
; CHECK: std %f2, 8(%r2)
; CHECK: br %r14
%f1 = load fp128 , fp128 *%ptr
%f2x = fpext float %f2 to fp128

6
test/CodeGen/SystemZ/fp-sub-03.ll
View File

@ -5,9 +5,9 @@
; There is no memory form of 128-bit subtraction.
define void @f1(fp128 *%ptr, float %f2) {
; CHECK-LABEL: f1:
; CHECK: lxebr %f0, %f0
; CHECK: ld %f1, 0(%r2)
; CHECK: ld %f3, 8(%r2)
; CHECK-DAG: lxebr %f0, %f0
; CHECK-DAG: ld %f1, 0(%r2)
; CHECK-DAG: ld %f3, 8(%r2)
; CHECK: sxbr %f1, %f0
; CHECK: std %f1, 0(%r2)
; CHECK: std %f3, 8(%r2)

4
test/CodeGen/SystemZ/pr32505.ll
View File

@ -6,9 +6,9 @@ target triple = "s390x-ibm-linux"
define <2 x float> @pr32505(<2 x i8> * %a) {
; CHECK-LABEL: pr32505:
; CHECK: # BB#0:
; CHECK-NEXT: lbh %r0, 0(%r2)
; CHECK-NEXT: ldgr %f0, %r0
; CHECK-NEXT: lbh %r0, 1(%r2)
; CHECK-NEXT: lbh %r1, 0(%r2)
; CHECK-NEXT: ldgr %f0, %r1
; CHECK-NEXT: ldgr %f2, %r0
; CHECK-NEXT: # kill: %F0S<def> %F0S<kill> %F0D<kill>
; CHECK-NEXT: # kill: %F2S<def> %F2S<kill> %F2D<kill>

6
test/CodeGen/SystemZ/swift-return.ll
View File

@ -8,9 +8,9 @@
; CHECK-LABEL: test:
; CHECK: st %r2
; CHECK: brasl %r14, gen
; CHECK-DAG: lhr %r2, %r2
; CHECK-DAG: lbr %[[REG1:r[0-9]+]], %r3
; CHECK: ar %r2, %[[REG1]]
; CHECK-DAG: lhr %{{r[0,2]+}}, %r2
; CHECK-DAG: lbr %{{r[0,2]+}}, %r3
; CHECK: ar %r2, %r0
; CHECK-O0-LABEL: test
; CHECK-O0: st %r2
; CHECK-O0: brasl %r14, gen

16
test/CodeGen/SystemZ/tdc-06.ll
View File

@ -10,30 +10,30 @@ declare fp128 @llvm.fabs.f128(fp128)
define i32 @fpc(double %x) {
entry:
; CHECK-LABEL: fpc
; CHECK: lhi %r2, 5
; CHECK: ltdbr %f0, %f0
; CHECK-DAG: lhi %r2, 5
; CHECK-DAG: ltdbr %f0, %f0
; CHECK: je [[RET:.L.*]]
%testeq = fcmp oeq double %x, 0.000000e+00
br i1 %testeq, label %ret, label %nonzero, !prof !1
nonzero:
; CHECK: lhi %r2, 1
; CHECK: cdbr %f0, %f0
; CHECK-DAG: lhi %r2, 1
; CHECK-DAG: cdbr %f0, %f0
; CHECK: jo [[RET]]
%testnan = fcmp uno double %x, 0.000000e+00
br i1 %testnan, label %ret, label %nonzeroord, !prof !1
nonzeroord:
; CHECK: lhi %r2, 2
; CHECK: tcdb %f0, 48
; CHECK-DAG: lhi %r2, 2
; CHECK-DAG: tcdb %f0, 48
; CHECK: jl [[RET]]
%abs = tail call double @llvm.fabs.f64(double %x)
%testinf = fcmp oeq double %abs, 0x7FF0000000000000
br i1 %testinf, label %ret, label %finite, !prof !1
finite:
; CHECK: lhi %r2, 3
; CHECK: tcdb %f0, 831
; CHECK-DAG: lhi %r2, 3
; CHECK-DAG: tcdb %f0, 831
; CHECK: blr %r14
; CHECK: lhi %r2, 4
%testnormal = fcmp uge double %abs, 0x10000000000000

4
test/CodeGen/SystemZ/tls-01.ll
View File

@ -14,8 +14,8 @@ define i32 *@foo() {
; CHECK-MAIN-LABEL: foo:
; CHECK-MAIN: ear [[HIGH:%r[0-5]]], %a0
; CHECK-MAIN: sllg %r2, [[HIGH]], 32
; CHECK-MAIN: ear %r2, %a1
; CHECK-MAIN: larl %r1, .LCP{{.*}}
; CHECK-MAIN-DAG: ear %r2, %a1
; CHECK-MAIN-DAG: larl %r1, .LCP{{.*}}
; CHECK-MAIN: ag %r2, 0(%r1)
; CHECK-MAIN: br %r14
ret i32 *@x

4
test/CodeGen/SystemZ/tls-02.ll
View File

@ -10,8 +10,8 @@ define i32 *@foo() {
; CHECK-MAIN-LABEL: foo:
; CHECK-MAIN: ear [[HIGH:%r[0-5]]], %a0
; CHECK-MAIN: sllg %r2, [[HIGH]], 32
; CHECK-MAIN: ear %r2, %a1
; CHECK-MAIN: larl %r1, x@INDNTPOFF
; CHECK-MAIN-DAG: ear %r2, %a1
; CHECK-MAIN-DAG: larl %r1, x@INDNTPOFF
; CHECK-MAIN: ag %r2, 0(%r1)
; CHECK-MAIN: br %r14
ret i32 *@x

6239
test/CodeGen/SystemZ/vec-cmp-cmp-logic-select.ll
View File

File diff suppressed because it is too large Load Diff

3422
test/CodeGen/SystemZ/vec-cmpsel.ll
View File

File diff suppressed because it is too large Load Diff

44
test/CodeGen/SystemZ/vec-div-01.ll
View File

@ -7,20 +7,20 @@
define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
; CHECK-LABEL: f1:
; CHECK: vlvgp [[REG:%v[0-9]+]],
; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 0
; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 1
; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 2
; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 3
; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 4
; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 5
; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 6
; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 8
; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 9
; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 10
; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 11
; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 12
; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 13
; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 14
; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 0
; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 1
; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 2
; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 3
; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 4
; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 5
; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 6
; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 8
; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 9
; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 10
; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 11
; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 12
; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 13
; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 14
; CHECK: br %r14
%ret = sdiv <16 x i8> %val1, %val2
ret <16 x i8> %ret
@ -30,12 +30,12 @@ define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
; CHECK-LABEL: f2:
; CHECK: vlvgp [[REG:%v[0-9]+]],
; CHECK-DAG: vlvgh [[REG]], {{%r[0-5]}}, 0
; CHECK-DAG: vlvgh [[REG]], {{%r[0-5]}}, 1
; CHECK-DAG: vlvgh [[REG]], {{%r[0-5]}}, 2
; CHECK-DAG: vlvgh [[REG]], {{%r[0-5]}}, 4
; CHECK-DAG: vlvgh [[REG]], {{%r[0-5]}}, 5
; CHECK-DAG: vlvgh [[REG]], {{%r[0-5]}}, 6
; CHECK-DAG: vlvgh [[REG]], {{%r[0-9]+}}, 0
; CHECK-DAG: vlvgh [[REG]], {{%r[0-9]+}}, 1
; CHECK-DAG: vlvgh [[REG]], {{%r[0-9]+}}, 2
; CHECK-DAG: vlvgh [[REG]], {{%r[0-9]+}}, 4
; CHECK-DAG: vlvgh [[REG]], {{%r[0-9]+}}, 5
; CHECK-DAG: vlvgh [[REG]], {{%r[0-9]+}}, 6
; CHECK: br %r14
%ret = sdiv <8 x i16> %val1, %val2
ret <8 x i16> %ret
@ -45,8 +45,8 @@ define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
; CHECK-LABEL: f3:
; CHECK: vlvgp [[REG:%v[0-9]+]],
; CHECK-DAG: vlvgf [[REG]], {{%r[0-5]}}, 0
; CHECK-DAG: vlvgf [[REG]], {{%r[0-5]}}, 2
; CHECK-DAG: vlvgf [[REG]], {{%r[0-9]+}}, 0
; CHECK-DAG: vlvgf [[REG]], {{%r[0-9]+}}, 2
; CHECK: br %r14
%ret = sdiv <4 x i32> %val1, %val2
ret <4 x i32> %ret

5
test/CodeGen/SystemZ/vec-sub-01.ll
View File

@ -52,12 +52,11 @@ define <4 x float> @f5(<4 x float> %val1, <4 x float> %val2) {
; CHECK-DAG: vrepf %v[[C2:[0-5]]], %v[[A2]], 2
; CHECK-DAG: vrepf %v[[D1:[0-5]]], %v[[A1]], 3
; CHECK-DAG: vrepf %v[[D2:[0-5]]], %v[[A2]], 3
; CHECK-DAG: ldr %f[[A1copy:[0-5]]], %f[[A1]]
; CHECK-DAG: sebr %f[[A1copy]], %f[[A2]]
; CHECK-DAG: sebr %f[[A1]], %f[[A2]]
; CHECK-DAG: sebr %f[[B1]], %f[[B2]]
; CHECK-DAG: sebr %f[[C1]], %f[[C2]]
; CHECK-DAG: sebr %f[[D1]], %f[[D2]]
; CHECK-DAG: vmrhf [[HIGH:%v[0-9]+]], %v[[A1copy]], %v[[B1]]
; CHECK-DAG: vmrhf [[HIGH:%v[0-9]+]], %v[[A1]], %v[[B1]]
; CHECK-DAG: vmrhf [[LOW:%v[0-9]+]], %v[[C1]], %v[[D1]]
; CHECK: vmrhg %v24, [[HIGH]], [[LOW]]
; CHECK: br %r14