RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 03:33:20 +01:00
Code Issues Projects Releases Wiki Activity

Jimptables working again on alpha.

Browse Source 
As a bonus, use the GOT node instead of the AlphaISD::GOT for internal stuff.

llvm-svn: 30873
This commit is contained in:
Andrew Lenharth 2006-10-11 04:29:42 +00:00
parent 95a8905db2
commit 4b783303e5
11 changed files with 28 additions and 34 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
include/llvm/CodeGen/SelectionDAGNodes.h
View File

@ -82,8 +82,8 @@ namespace ISD {
Constant, ConstantFP,
GlobalAddress, FrameIndex, JumpTable, ConstantPool, ExternalSymbol,
// The relocation value to add to the value loaded from a jump table
JumpTableRelocBase,
// The address of the GOT
GLOBAL_OFFSET_TABLE,
// TargetConstant* - Like Constant*, but the DAG does not do any folding or
// simplification of the constant.

2
lib/CodeGen/AsmPrinter.cpp
View File

@ -204,7 +204,7 @@ void AsmPrinter::EmitJumpTableInfo(MachineJumpTableInfo *MJTI,
TargetLowering *LoweringInfo = TM.getTargetLowering();
if (LoweringInfo && LoweringInfo->usesGlobalOffsetTable()) {
SwitchToDataSection(TAI->getJumpTableDataSection(), 0);
if (TD->getPointerSize() == 8)
if (TD->getPointerSize() == 8 && !JTEntryDirective)
JTEntryDirective = TAI->getData64bitsDirective();
} else {
// In PIC mode, we need to emit the jump table to the same section as the

12
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -534,6 +534,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
case ISD::SRCVALUE:
case ISD::STRING:
case ISD::CONDCODE:
case ISD::GLOBAL_OFFSET_TABLE:
// Primitives must all be legal.
assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) &&
"This must be legal!");
@ -558,17 +559,6 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
#endif
assert(0 && "Do not know how to legalize this operator!");
abort();
case ISD::JumpTableRelocBase:
switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
case TargetLowering::Custom:
Tmp1 = TLI.LowerOperation(Op, DAG);
if (Tmp1.Val) Result = Tmp1;
break;
default:
Result = LegalizeOp(Node->getOperand(0));
break;
}
break;
case ISD::GlobalAddress:
case ISD::ExternalSymbol:
case ISD::ConstantPool:

2
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -2454,7 +2454,7 @@ const char *SDNode::getOperationName(const SelectionDAG *G) const {
case ISD::GlobalAddress: return "GlobalAddress";
case ISD::FrameIndex: return "FrameIndex";
case ISD::JumpTable: return "JumpTable";
case ISD::JumpTableRelocBase: return "JumpTableRelocBase";
case ISD::GLOBAL_OFFSET_TABLE: return "GLOBAL_OFFSET_TABLE";
case ISD::ConstantPool: return "ConstantPool";
case ISD::ExternalSymbol: return "ExternalSymbol";
case ISD::INTRINSIC_WO_CHAIN: {

6
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -864,7 +864,11 @@ void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
// For Pic, the sequence is:
// BRIND(load(Jumptable + index) + RelocBase)
// RelocBase is the JumpTable on PPC and X86, GOT on Alpha
SDOperand Reloc = DAG.getNode(ISD::JumpTableRelocBase, PTy, TAB);
SDOperand Reloc;
if (TLI.usesGlobalOffsetTable())
Reloc = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PTy);
else
Reloc = TAB;
ADD = DAG.getNode(ISD::ADD, PTy,
((PTy != MVT::i32) ? DAG.getNode(ISD::SIGN_EXTEND, PTy, LD) : LD), Reloc);
DAG.setRoot(DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), ADD));

5
lib/Target/Alpha/AlphaISelDAGToDAG.cpp
View File

@ -99,7 +99,8 @@ namespace {
public:
AlphaDAGToDAGISel(TargetMachine &TM)
: SelectionDAGISel(AlphaLowering), AlphaLowering(TM)
: SelectionDAGISel(AlphaLowering),
AlphaLowering(*(AlphaTargetLowering*)(TM.getTargetLowering()))
{}
/// getI64Imm - Return a target constant with the specified value, of type
@ -201,7 +202,7 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
CurDAG->getTargetFrameIndex(FI, MVT::i32),
getI64Imm(0));
}
case AlphaISD::GlobalBaseReg: {
case ISD::GLOBAL_OFFSET_TABLE: {
SDOperand Result = getGlobalBaseReg();
ReplaceUses(Op, Result);
return NULL;

18
lib/Target/Alpha/AlphaISelLowering.cpp
View File

@ -132,7 +132,6 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
setOperationAction(ISD::JumpTable, MVT::i64, Custom);
setOperationAction(ISD::JumpTable, MVT::i32, Custom);
setOperationAction(ISD::JumpTableRelocBase, MVT::i64, Custom);
setStackPointerRegisterToSaveRestore(Alpha::R30);
@ -160,7 +159,6 @@ const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const {
case AlphaISD::GPRelHi: return "Alpha::GPRelHi";
case AlphaISD::GPRelLo: return "Alpha::GPRelLo";
case AlphaISD::RelLit: return "Alpha::RelLit";
case AlphaISD::GlobalBaseReg: return "Alpha::GlobalBaseReg";
case AlphaISD::GlobalRetAddr: return "Alpha::GlobalRetAddr";
case AlphaISD::CALL: return "Alpha::CALL";
case AlphaISD::DivCall: return "Alpha::DivCall";
@ -177,7 +175,7 @@ static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
const TargetMachine &TM = DAG.getTarget();
SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, JTI,
DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, JTI, Hi);
return Lo;
}
@ -414,8 +412,6 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
GP, RA);
case ISD::RET: return LowerRET(Op,DAG, getVRegRA());
case ISD::JumpTable: return LowerJumpTable(Op, DAG);
case ISD::JumpTableRelocBase:
return DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64);
case ISD::SINT_TO_FP: {
assert(MVT::i64 == Op.getOperand(0).getValueType() &&
@ -462,7 +458,7 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment());
SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, CPI,
DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, CPI, Hi);
return Lo;
}
@ -474,16 +470,18 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
// if (!GV->hasWeakLinkage() && !GV->isExternal() && !GV->hasLinkOnceLinkage()) {
if (GV->hasInternalLinkage()) {
SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA,
DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi);
return Lo;
} else
return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA, DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA,
DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
}
case ISD::ExternalSymbol: {
return DAG.getNode(AlphaISD::RelLit, MVT::i64,
DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)->getSymbol(), MVT::i64),
DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)
->getSymbol(), MVT::i64),
DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
}
case ISD::UREM:

3
lib/Target/Alpha/AlphaISelLowering.h
View File

@ -36,9 +36,6 @@ namespace llvm {
/// RetLit - Literal Relocation of a Global
RelLit,
/// GlobalBaseReg - used to restore the GOT ptr
GlobalBaseReg,
/// GlobalRetAddr - used to restore the return address
GlobalRetAddr,

3
lib/Target/Alpha/AlphaTargetMachine.cpp
View File

@ -58,7 +58,8 @@ AlphaTargetMachine::AlphaTargetMachine(const Module &M, const std::string &FS)
: DataLayout("e"),
FrameInfo(TargetFrameInfo::StackGrowsDown, 16, 0),
JITInfo(*this),
Subtarget(M, FS) {
Subtarget(M, FS),
TLInfo(*this) {
setRelocationModel(Reloc::PIC_);
}

5
lib/Target/Alpha/AlphaTargetMachine.h
View File

@ -19,6 +19,7 @@
#include "llvm/Target/TargetFrameInfo.h"
#include "AlphaInstrInfo.h"
#include "AlphaJITInfo.h"
#include "AlphaISelLowering.h"
#include "AlphaSubtarget.h"
namespace llvm {
@ -31,6 +32,7 @@ class AlphaTargetMachine : public LLVMTargetMachine {
TargetFrameInfo FrameInfo;
AlphaJITInfo JITInfo;
AlphaSubtarget Subtarget;
AlphaTargetLowering TLInfo;
protected:
virtual const TargetAsmInfo *createTargetAsmInfo() const;
@ -44,6 +46,9 @@ public:
virtual const MRegisterInfo *getRegisterInfo() const {
return &InstrInfo.getRegisterInfo();
}
virtual TargetLowering* getTargetLowering() const {
return const_cast<AlphaTargetLowering*>(&TLInfo);
}
virtual const TargetData *getTargetData() const { return &DataLayout; }
virtual TargetJITInfo* getJITInfo() {
return &JITInfo;

2
test/Regression/CodeGen/Alpha/jmp_table.ll
View File

@ -4,8 +4,6 @@
; RUN: llvm-as < %s | llc -march=alpha | grep 'ldl' &&
; RUN: llvm-as < %s | llc -march=alpha | grep 'rodata'
; XFAIL: *
target endian = little
target pointersize = 64
target triple = "alphaev67-unknown-linux-gnu"