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https://github.com/RPCS3/llvm-mirror.git
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[ARM][MVE] Enable masked gathers from vector of pointers
Adds a pass to the ARM backend that takes a v4i32 gather and transforms it into a call to MVE's masked gather intrinsics. Differential Revision: https://reviews.llvm.org/D71743
This commit is contained in:
Anna Welker
parent
4710b1b396
commit
4b7c61b6c9
@ -53,6 +53,7 @@ FunctionPass *createThumb2SizeReductionPass(
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InstructionSelector *
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createARMInstructionSelector(const ARMBaseTargetMachine &TM, const ARMSubtarget &STI,
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const ARMRegisterBankInfo &RBI);
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Pass *createMVEGatherScatterLoweringPass();
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void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
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ARMAsmPrinter &AP);
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@ -67,6 +68,7 @@ void initializeThumb2ITBlockPass(PassRegistry &);
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void initializeMVEVPTBlockPass(PassRegistry &);
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void initializeARMLowOverheadLoopsPass(PassRegistry &);
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void initializeMVETailPredicationPass(PassRegistry &);
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void initializeMVEGatherScatterLoweringPass(PassRegistry &);
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} // end namespace llvm
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@ -98,6 +98,7 @@ extern "C" void LLVMInitializeARMTarget() {
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initializeMVEVPTBlockPass(Registry);
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initializeMVETailPredicationPass(Registry);
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initializeARMLowOverheadLoopsPass(Registry);
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initializeMVEGatherScatterLoweringPass(Registry);
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}
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static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
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@ -404,6 +405,8 @@ void ARMPassConfig::addIRPasses() {
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return ST.hasAnyDataBarrier() && !ST.isThumb1Only();
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}));
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addPass(createMVEGatherScatterLoweringPass());
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TargetPassConfig::addIRPasses();
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// Run the parallel DSP pass.
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@ -22,6 +22,7 @@
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#include "llvm/IR/Instruction.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/IntrinsicInst.h"
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#include "llvm/IR/PatternMatch.h"
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#include "llvm/IR/Type.h"
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#include "llvm/MC/SubtargetFeature.h"
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#include "llvm/Support/Casting.h"
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@ -46,6 +47,8 @@ static cl::opt<bool> DisableLowOverheadLoops(
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extern cl::opt<bool> DisableTailPredication;
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extern cl::opt<bool> EnableMaskedGatherScatters;
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bool ARMTTIImpl::areInlineCompatible(const Function *Caller,
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const Function *Callee) const {
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const TargetMachine &TM = getTLI()->getTargetMachine();
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@ -514,6 +517,27 @@ bool ARMTTIImpl::isLegalMaskedLoad(Type *DataTy, MaybeAlign Alignment) {
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(EltWidth == 8);
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}
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bool ARMTTIImpl::isLegalMaskedGather(Type *Ty, MaybeAlign Alignment) {
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if (!EnableMaskedGatherScatters || !ST->hasMVEIntegerOps())
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return false;
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// This method is called in 2 places:
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// - from the vectorizer with a scalar type, in which case we need to get
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// this as good as we can with the limited info we have (and rely on the cost
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// model for the rest).
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// - from the masked intrinsic lowering pass with the actual vector type.
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// For MVE, we have a custom lowering pass that will already have custom
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// legalised any gathers that we can to MVE intrinsics, and want to expand all
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// the rest. The pass runs before the masked intrinsic lowering pass, so if we
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// are here, we know we want to expand.
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if (isa<VectorType>(Ty))
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return false;
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unsigned EltWidth = Ty->getScalarSizeInBits();
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return ((EltWidth == 32 && (!Alignment || Alignment >= 4)) ||
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(EltWidth == 16 && (!Alignment || Alignment >= 2)) || EltWidth == 8);
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}
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int ARMTTIImpl::getMemcpyCost(const Instruction *I) {
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const MemCpyInst *MI = dyn_cast<MemCpyInst>(I);
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assert(MI && "MemcpyInst expected");
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@ -159,7 +159,7 @@ public:
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return isLegalMaskedLoad(DataTy, Alignment);
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}
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bool isLegalMaskedGather(Type *Ty, MaybeAlign Alignment) { return false; }
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bool isLegalMaskedGather(Type *Ty, MaybeAlign Alignment);
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bool isLegalMaskedScatter(Type *Ty, MaybeAlign Alignment) { return false; }
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@ -51,6 +51,7 @@ add_llvm_target(ARMCodeGen
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ARMTargetObjectFile.cpp
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ARMTargetTransformInfo.cpp
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MLxExpansionPass.cpp
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MVEGatherScatterLowering.cpp
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MVETailPredication.cpp
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MVEVPTBlockPass.cpp
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Thumb1FrameLowering.cpp
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177
lib/Target/ARM/MVEGatherScatterLowering.cpp
Normal file
177
lib/Target/ARM/MVEGatherScatterLowering.cpp
Normal file
@ -0,0 +1,177 @@
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//===- ARMGatherScatterLowering.cpp - Gather/Scatter lowering -------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// This pass custom lowers llvm.gather and llvm.scatter instructions to
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/// arm.mve.gather and arm.mve.scatter intrinsics, optimising the code to
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/// produce a better final result as we go.
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//
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//===----------------------------------------------------------------------===//
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#include "ARM.h"
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#include "ARMBaseInstrInfo.h"
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#include "ARMSubtarget.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/TargetLowering.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/IR/BasicBlock.h"
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#include "llvm/IR/Constant.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/IRBuilder.h"
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#include "llvm/IR/InstrTypes.h"
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#include "llvm/IR/Instruction.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/IntrinsicInst.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/IR/IntrinsicsARM.h"
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#include "llvm/IR/PatternMatch.h"
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#include "llvm/IR/Type.h"
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#include "llvm/IR/Value.h"
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#include "llvm/InitializePasses.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/Casting.h"
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#include <algorithm>
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#include <cassert>
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using namespace llvm;
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#define DEBUG_TYPE "mve-gather-scatter-lowering"
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cl::opt<bool> EnableMaskedGatherScatters(
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"enable-arm-maskedgatscat", cl::Hidden, cl::init(false),
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cl::desc("Enable the generation of masked gathers and scatters"));
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namespace {
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class MVEGatherScatterLowering : public FunctionPass {
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public:
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static char ID; // Pass identification, replacement for typeid
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explicit MVEGatherScatterLowering() : FunctionPass(ID) {
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initializeMVEGatherScatterLoweringPass(*PassRegistry::getPassRegistry());
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}
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bool runOnFunction(Function &F) override;
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StringRef getPassName() const override {
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return "MVE gather/scatter lowering";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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AU.addRequired<TargetPassConfig>();
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FunctionPass::getAnalysisUsage(AU);
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}
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};
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} // end anonymous namespace
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char MVEGatherScatterLowering::ID = 0;
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INITIALIZE_PASS(MVEGatherScatterLowering, DEBUG_TYPE,
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"MVE gather/scattering lowering pass", false, false)
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Pass *llvm::createMVEGatherScatterLoweringPass() {
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return new MVEGatherScatterLowering();
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}
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static bool isLegalTypeAndAlignment(unsigned NumElements, unsigned ElemSize,
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unsigned Alignment) {
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// Do only allow non-extending v4i32 gathers for now
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return NumElements == 4 && ElemSize == 32 && Alignment >= 4;
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}
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static bool LowerGather(IntrinsicInst *I) {
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using namespace PatternMatch;
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LLVM_DEBUG(dbgs() << "masked gathers: checking transform preconditions\n");
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// @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0)
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// Attempt to turn the masked gather in I into a MVE intrinsic
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// Potentially optimising the addressing modes as we do so.
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Type *Ty = I->getType();
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Value *Ptr = I->getArgOperand(0);
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unsigned Alignment = cast<ConstantInt>(I->getArgOperand(1))->getZExtValue();
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Value *Mask = I->getArgOperand(2);
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Value *PassThru = I->getArgOperand(3);
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// Check this is a valid gather with correct alignment
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if (!isLegalTypeAndAlignment(Ty->getVectorNumElements(),
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Ty->getScalarSizeInBits(), Alignment)) {
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LLVM_DEBUG(dbgs() << "masked gathers: instruction does not have valid "
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<< "alignment or vector type \n");
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return false;
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}
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IRBuilder<> Builder(I->getContext());
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Builder.SetInsertPoint(I);
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Builder.SetCurrentDebugLocation(I->getDebugLoc());
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Value *Load = nullptr;
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// Look through bitcast instruction if #elements is the same
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if (auto *BitCast = dyn_cast<BitCastInst>(Ptr)) {
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Type *BCTy = BitCast->getType();
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Type *BCSrcTy = BitCast->getOperand(0)->getType();
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if (BCTy->getVectorNumElements() == BCSrcTy->getVectorNumElements()) {
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LLVM_DEBUG(dbgs() << "masked gathers: looking through bitcast\n");
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Ptr = BitCast->getOperand(0);
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}
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}
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assert(Ptr->getType()->isVectorTy() && "Unexpected pointer type");
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if (Ty->getVectorNumElements() != 4)
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// Can't build an intrinsic for this
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return false;
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if (match(Mask, m_One()))
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Load = Builder.CreateIntrinsic(Intrinsic::arm_mve_vldr_gather_base,
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{Ty, Ptr->getType()},
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{Ptr, Builder.getInt32(0)});
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else
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Load =
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Builder.CreateIntrinsic(Intrinsic::arm_mve_vldr_gather_base_predicated,
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{Ty, Ptr->getType(), Mask->getType()},
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{Ptr, Builder.getInt32(0), Mask});
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if (!isa<UndefValue>(PassThru) && !match(PassThru, m_Zero())) {
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LLVM_DEBUG(dbgs() << "masked gathers: found non-trivial passthru - "
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<< "creating select\n");
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Load = Builder.CreateSelect(Mask, Load, PassThru);
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}
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LLVM_DEBUG(dbgs() << "masked gathers: successfully built masked gather\n");
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I->replaceAllUsesWith(Load);
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I->eraseFromParent();
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return true;
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}
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bool MVEGatherScatterLowering::runOnFunction(Function &F) {
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if (!EnableMaskedGatherScatters)
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return false;
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auto &TPC = getAnalysis<TargetPassConfig>();
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auto &TM = TPC.getTM<TargetMachine>();
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auto *ST = &TM.getSubtarget<ARMSubtarget>(F);
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if (!ST->hasMVEIntegerOps())
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return false;
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SmallVector<IntrinsicInst *, 4> Gathers;
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for (BasicBlock &BB : F) {
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for (Instruction &I : BB) {
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IntrinsicInst *II = dyn_cast<IntrinsicInst>(&I);
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if (II && II->getIntrinsicID() == Intrinsic::masked_gather)
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Gathers.push_back(II);
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}
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}
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if (Gathers.empty())
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return false;
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for (IntrinsicInst *I : Gathers)
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LowerGather(I);
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return true;
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}
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@ -7,6 +7,7 @@
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; CHECK-NEXT: FunctionPass Manager
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; CHECK-NEXT: Expand Atomic instructions
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; CHECK-NEXT: Simplify the CFG
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; CHECK-NEXT: MVE gather/scatter lowering
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; CHECK-NEXT: Dominator Tree Construction
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; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)
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; CHECK-NEXT: Module Verifier
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461
test/CodeGen/Thumb2/mve-gather-ind32-scaled.ll
Normal file
461
test/CodeGen/Thumb2/mve-gather-ind32-scaled.ll
Normal file
@ -0,0 +1,461 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o 2>/dev/null - | FileCheck %s
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define arm_aapcs_vfpcc <4 x i32> @zext_scaled_i16_i32(i16* %base, <4 x i32>* %offptr) {
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; CHECK-LABEL: zext_scaled_i16_i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldrw.u32 q0, [r1]
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; CHECK-NEXT: vshl.i32 q0, q0, #1
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; CHECK-NEXT: vadd.i32 q0, q0, r0
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; CHECK-NEXT: vmov r2, s0
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; CHECK-NEXT: vmov r0, s1
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; CHECK-NEXT: vmov r3, s2
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; CHECK-NEXT: vmov r1, s3
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; CHECK-NEXT: ldrh r2, [r2]
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; CHECK-NEXT: ldrh r0, [r0]
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; CHECK-NEXT: vmov.32 q0[0], r2
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; CHECK-NEXT: ldrh r3, [r3]
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; CHECK-NEXT: vmov.32 q0[1], r0
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; CHECK-NEXT: ldrh r1, [r1]
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; CHECK-NEXT: vmov.32 q0[2], r3
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; CHECK-NEXT: vmov.32 q0[3], r1
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; CHECK-NEXT: vmovlb.u16 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%offs = load <4 x i32>, <4 x i32>* %offptr, align 4
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%ptrs = getelementptr inbounds i16, i16* %base, <4 x i32> %offs
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%gather = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> %ptrs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i16> undef)
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%gather.zext = zext <4 x i16> %gather to <4 x i32>
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ret <4 x i32> %gather.zext
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}
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define arm_aapcs_vfpcc <4 x i32> @sext_scaled_i16_i32(i16* %base, <4 x i32>* %offptr) {
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; CHECK-LABEL: sext_scaled_i16_i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldrw.u32 q0, [r1]
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; CHECK-NEXT: vshl.i32 q0, q0, #1
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; CHECK-NEXT: vadd.i32 q0, q0, r0
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; CHECK-NEXT: vmov r2, s0
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; CHECK-NEXT: vmov r0, s1
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; CHECK-NEXT: vmov r3, s2
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; CHECK-NEXT: vmov r1, s3
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; CHECK-NEXT: ldrh r2, [r2]
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; CHECK-NEXT: ldrh r0, [r0]
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; CHECK-NEXT: vmov.32 q0[0], r2
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; CHECK-NEXT: ldrh r3, [r3]
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; CHECK-NEXT: vmov.32 q0[1], r0
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; CHECK-NEXT: ldrh r1, [r1]
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; CHECK-NEXT: vmov.32 q0[2], r3
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; CHECK-NEXT: vmov.32 q0[3], r1
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; CHECK-NEXT: vmovlb.s16 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%offs = load <4 x i32>, <4 x i32>* %offptr, align 4
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%ptrs = getelementptr inbounds i16, i16* %base, <4 x i32> %offs
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%gather = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> %ptrs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i16> undef)
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%gather.sext = sext <4 x i16> %gather to <4 x i32>
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ret <4 x i32> %gather.sext
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}
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define arm_aapcs_vfpcc <4 x i32> @scaled_i32_i32(i32* %base, <4 x i32>* %offptr) {
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; CHECK-LABEL: scaled_i32_i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldrw.u32 q0, [r1]
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; CHECK-NEXT: vshl.i32 q0, q0, #2
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; CHECK-NEXT: vadd.i32 q1, q0, r0
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; CHECK-NEXT: vldrw.u32 q0, [q1]
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; CHECK-NEXT: bx lr
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entry:
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%offs = load <4 x i32>, <4 x i32>* %offptr, align 4
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%ptrs = getelementptr inbounds i32, i32* %base, <4 x i32> %offs
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%gather = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef)
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ret <4 x i32> %gather
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}
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; TODO: scaled_f16_i32
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define arm_aapcs_vfpcc <4 x float> @scaled_f32_i32(i32* %base, <4 x i32>* %offptr) {
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; CHECK-LABEL: scaled_f32_i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldrw.u32 q0, [r1]
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; CHECK-NEXT: vshl.i32 q0, q0, #2
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; CHECK-NEXT: vadd.i32 q1, q0, r0
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; CHECK-NEXT: vldrw.u32 q0, [q1]
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; CHECK-NEXT: bx lr
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entry:
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%offs = load <4 x i32>, <4 x i32>* %offptr, align 4
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%i32_ptrs = getelementptr inbounds i32, i32* %base, <4 x i32> %offs
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%ptrs = bitcast <4 x i32*> %i32_ptrs to <4 x float*>
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%gather = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x float> undef)
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ret <4 x float> %gather
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}
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define arm_aapcs_vfpcc <4 x i32> @unsigned_scaled_b_i32_i16(i32* %base, <4 x i16>* %offptr) {
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; CHECK-LABEL: unsigned_scaled_b_i32_i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldrh.u32 q0, [r1]
|
||||
; CHECK-NEXT: vshl.i32 q0, q0, #2
|
||||
; CHECK-NEXT: vadd.i32 q1, q0, r0
|
||||
; CHECK-NEXT: vldrw.u32 q0, [q1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i16>, <4 x i16>* %offptr, align 2
|
||||
%offs.zext = zext <4 x i16> %offs to <4 x i32>
|
||||
%ptrs = getelementptr inbounds i32, i32* %base, <4 x i32> %offs.zext
|
||||
%gather = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef)
|
||||
ret <4 x i32> %gather
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @signed_scaled_i32_i16(i32* %base, <4 x i16>* %offptr) {
|
||||
; CHECK-LABEL: signed_scaled_i32_i16:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.s32 q0, [r1]
|
||||
; CHECK-NEXT: vshl.i32 q0, q0, #2
|
||||
; CHECK-NEXT: vadd.i32 q1, q0, r0
|
||||
; CHECK-NEXT: vldrw.u32 q0, [q1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i16>, <4 x i16>* %offptr, align 2
|
||||
%offs.sext = sext <4 x i16> %offs to <4 x i32>
|
||||
%ptrs = getelementptr inbounds i32, i32* %base, <4 x i32> %offs.sext
|
||||
%gather = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef)
|
||||
ret <4 x i32> %gather
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x float> @a_unsigned_scaled_f32_i16(i32* %base, <4 x i16>* %offptr) {
|
||||
; CHECK-LABEL: a_unsigned_scaled_f32_i16:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.u32 q0, [r1]
|
||||
; CHECK-NEXT: vshl.i32 q0, q0, #2
|
||||
; CHECK-NEXT: vadd.i32 q1, q0, r0
|
||||
; CHECK-NEXT: vldrw.u32 q0, [q1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i16>, <4 x i16>* %offptr, align 2
|
||||
%offs.zext = zext <4 x i16> %offs to <4 x i32>
|
||||
%i32_ptrs = getelementptr inbounds i32, i32* %base, <4 x i32> %offs.zext
|
||||
%ptrs = bitcast <4 x i32*> %i32_ptrs to <4 x float*>
|
||||
%gather = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x float> undef)
|
||||
ret <4 x float> %gather
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x float> @b_signed_scaled_f32_i16(i32* %base, <4 x i16>* %offptr) {
|
||||
; CHECK-LABEL: b_signed_scaled_f32_i16:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.s32 q0, [r1]
|
||||
; CHECK-NEXT: vshl.i32 q0, q0, #2
|
||||
; CHECK-NEXT: vadd.i32 q1, q0, r0
|
||||
; CHECK-NEXT: vldrw.u32 q0, [q1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i16>, <4 x i16>* %offptr, align 2
|
||||
%offs.sext = sext <4 x i16> %offs to <4 x i32>
|
||||
%i32_ptrs = getelementptr inbounds i32, i32* %base, <4 x i32> %offs.sext
|
||||
%ptrs = bitcast <4 x i32*> %i32_ptrs to <4 x float*>
|
||||
%gather = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x float> undef)
|
||||
ret <4 x float> %gather
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @zext_signed_scaled_i16_i16(i16* %base, <4 x i16>* %offptr) {
|
||||
; CHECK-LABEL: zext_signed_scaled_i16_i16:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.s32 q0, [r1]
|
||||
; CHECK-NEXT: vshl.i32 q0, q0, #1
|
||||
; CHECK-NEXT: vadd.i32 q0, q0, r0
|
||||
; CHECK-NEXT: vmov r2, s0
|
||||
; CHECK-NEXT: vmov r0, s1
|
||||
; CHECK-NEXT: vmov r3, s2
|
||||
; CHECK-NEXT: vmov r1, s3
|
||||
; CHECK-NEXT: ldrh r2, [r2]
|
||||
; CHECK-NEXT: ldrh r0, [r0]
|
||||
; CHECK-NEXT: vmov.32 q0[0], r2
|
||||
; CHECK-NEXT: ldrh r3, [r3]
|
||||
; CHECK-NEXT: vmov.32 q0[1], r0
|
||||
; CHECK-NEXT: ldrh r1, [r1]
|
||||
; CHECK-NEXT: vmov.32 q0[2], r3
|
||||
; CHECK-NEXT: vmov.32 q0[3], r1
|
||||
; CHECK-NEXT: vmovlb.u16 q0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i16>, <4 x i16>* %offptr, align 2
|
||||
%offs.sext = sext <4 x i16> %offs to <4 x i32>
|
||||
%ptrs = getelementptr inbounds i16, i16* %base, <4 x i32> %offs.sext
|
||||
%gather = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> %ptrs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i16> undef)
|
||||
%gather.zext = zext <4 x i16> %gather to <4 x i32>
|
||||
ret <4 x i32> %gather.zext
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @sext_signed_scaled_i16_i16(i16* %base, <4 x i16>* %offptr) {
|
||||
; CHECK-LABEL: sext_signed_scaled_i16_i16:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.s32 q0, [r1]
|
||||
; CHECK-NEXT: vshl.i32 q0, q0, #1
|
||||
; CHECK-NEXT: vadd.i32 q0, q0, r0
|
||||
; CHECK-NEXT: vmov r2, s0
|
||||
; CHECK-NEXT: vmov r0, s1
|
||||
; CHECK-NEXT: vmov r3, s2
|
||||
; CHECK-NEXT: vmov r1, s3
|
||||
; CHECK-NEXT: ldrh r2, [r2]
|
||||
; CHECK-NEXT: ldrh r0, [r0]
|
||||
; CHECK-NEXT: vmov.32 q0[0], r2
|
||||
; CHECK-NEXT: ldrh r3, [r3]
|
||||
; CHECK-NEXT: vmov.32 q0[1], r0
|
||||
; CHECK-NEXT: ldrh r1, [r1]
|
||||
; CHECK-NEXT: vmov.32 q0[2], r3
|
||||
; CHECK-NEXT: vmov.32 q0[3], r1
|
||||
; CHECK-NEXT: vmovlb.s16 q0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i16>, <4 x i16>* %offptr, align 2
|
||||
%offs.sext = sext <4 x i16> %offs to <4 x i32>
|
||||
%ptrs = getelementptr inbounds i16, i16* %base, <4 x i32> %offs.sext
|
||||
%gather = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> %ptrs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i16> undef)
|
||||
%gather.sext = sext <4 x i16> %gather to <4 x i32>
|
||||
ret <4 x i32> %gather.sext
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @zext_unsigned_scaled_i16_i16(i16* %base, <4 x i16>* %offptr) {
|
||||
; CHECK-LABEL: zext_unsigned_scaled_i16_i16:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.u32 q0, [r1]
|
||||
; CHECK-NEXT: vshl.i32 q0, q0, #1
|
||||
; CHECK-NEXT: vadd.i32 q0, q0, r0
|
||||
; CHECK-NEXT: vmov r2, s0
|
||||
; CHECK-NEXT: vmov r0, s1
|
||||
; CHECK-NEXT: vmov r3, s2
|
||||
; CHECK-NEXT: vmov r1, s3
|
||||
; CHECK-NEXT: ldrh r2, [r2]
|
||||
; CHECK-NEXT: ldrh r0, [r0]
|
||||
; CHECK-NEXT: vmov.32 q0[0], r2
|
||||
; CHECK-NEXT: ldrh r3, [r3]
|
||||
; CHECK-NEXT: vmov.32 q0[1], r0
|
||||
; CHECK-NEXT: ldrh r1, [r1]
|
||||
; CHECK-NEXT: vmov.32 q0[2], r3
|
||||
; CHECK-NEXT: vmov.32 q0[3], r1
|
||||
; CHECK-NEXT: vmovlb.u16 q0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i16>, <4 x i16>* %offptr, align 2
|
||||
%offs.zext = zext <4 x i16> %offs to <4 x i32>
|
||||
%ptrs = getelementptr inbounds i16, i16* %base, <4 x i32> %offs.zext
|
||||
%gather = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> %ptrs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i16> undef)
|
||||
%gather.zext = zext <4 x i16> %gather to <4 x i32>
|
||||
ret <4 x i32> %gather.zext
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @sext_unsigned_scaled_i16_i16(i16* %base, <4 x i16>* %offptr) {
|
||||
; CHECK-LABEL: sext_unsigned_scaled_i16_i16:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.u32 q0, [r1]
|
||||
; CHECK-NEXT: vshl.i32 q0, q0, #1
|
||||
; CHECK-NEXT: vadd.i32 q0, q0, r0
|
||||
; CHECK-NEXT: vmov r2, s0
|
||||
; CHECK-NEXT: vmov r0, s1
|
||||
; CHECK-NEXT: vmov r3, s2
|
||||
; CHECK-NEXT: vmov r1, s3
|
||||
; CHECK-NEXT: ldrh r2, [r2]
|
||||
; CHECK-NEXT: ldrh r0, [r0]
|
||||
; CHECK-NEXT: vmov.32 q0[0], r2
|
||||
; CHECK-NEXT: ldrh r3, [r3]
|
||||
; CHECK-NEXT: vmov.32 q0[1], r0
|
||||
; CHECK-NEXT: ldrh r1, [r1]
|
||||
; CHECK-NEXT: vmov.32 q0[2], r3
|
||||
; CHECK-NEXT: vmov.32 q0[3], r1
|
||||
; CHECK-NEXT: vmovlb.s16 q0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i16>, <4 x i16>* %offptr, align 2
|
||||
%offs.zext = zext <4 x i16> %offs to <4 x i32>
|
||||
%ptrs = getelementptr inbounds i16, i16* %base, <4 x i32> %offs.zext
|
||||
%gather = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> %ptrs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i16> undef)
|
||||
%gather.sext = sext <4 x i16> %gather to <4 x i32>
|
||||
ret <4 x i32> %gather.sext
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @unsigned_scaled_b_i32_i8(i32* %base, <4 x i8>* %offptr) {
|
||||
; CHECK-LABEL: unsigned_scaled_b_i32_i8:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u32 q0, [r1]
|
||||
; CHECK-NEXT: vshl.i32 q0, q0, #2
|
||||
; CHECK-NEXT: vadd.i32 q1, q0, r0
|
||||
; CHECK-NEXT: vldrw.u32 q0, [q1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i8>, <4 x i8>* %offptr, align 1
|
||||
%offs.zext = zext <4 x i8> %offs to <4 x i32>
|
||||
%ptrs = getelementptr inbounds i32, i32* %base, <4 x i32> %offs.zext
|
||||
%gather = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef)
|
||||
ret <4 x i32> %gather
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @signed_scaled_i32_i8(i32* %base, <4 x i8>* %offptr) {
|
||||
; CHECK-LABEL: signed_scaled_i32_i8:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.s32 q0, [r1]
|
||||
; CHECK-NEXT: vshl.i32 q0, q0, #2
|
||||
; CHECK-NEXT: vadd.i32 q1, q0, r0
|
||||
; CHECK-NEXT: vldrw.u32 q0, [q1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i8>, <4 x i8>* %offptr, align 1
|
||||
%offs.sext = sext <4 x i8> %offs to <4 x i32>
|
||||
%ptrs = getelementptr inbounds i32, i32* %base, <4 x i32> %offs.sext
|
||||
%gather = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef)
|
||||
ret <4 x i32> %gather
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x float> @a_unsigned_scaled_f32_i8(i32* %base, <4 x i8>* %offptr) {
|
||||
; CHECK-LABEL: a_unsigned_scaled_f32_i8:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u32 q0, [r1]
|
||||
; CHECK-NEXT: vshl.i32 q0, q0, #2
|
||||
; CHECK-NEXT: vadd.i32 q1, q0, r0
|
||||
; CHECK-NEXT: vldrw.u32 q0, [q1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i8>, <4 x i8>* %offptr, align 1
|
||||
%offs.zext = zext <4 x i8> %offs to <4 x i32>
|
||||
%i32_ptrs = getelementptr inbounds i32, i32* %base, <4 x i32> %offs.zext
|
||||
%ptrs = bitcast <4 x i32*> %i32_ptrs to <4 x float*>
|
||||
%gather = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x float> undef)
|
||||
ret <4 x float> %gather
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x float> @b_signed_scaled_f32_i8(i32* %base, <4 x i8>* %offptr) {
|
||||
; CHECK-LABEL: b_signed_scaled_f32_i8:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.s32 q0, [r1]
|
||||
; CHECK-NEXT: vshl.i32 q0, q0, #2
|
||||
; CHECK-NEXT: vadd.i32 q1, q0, r0
|
||||
; CHECK-NEXT: vldrw.u32 q0, [q1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i8>, <4 x i8>* %offptr, align 1
|
||||
%offs.sext = sext <4 x i8> %offs to <4 x i32>
|
||||
%i32_ptrs = getelementptr inbounds i32, i32* %base, <4 x i32> %offs.sext
|
||||
%ptrs = bitcast <4 x i32*> %i32_ptrs to <4 x float*>
|
||||
%gather = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x float> undef)
|
||||
ret <4 x float> %gather
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @zext_signed_scaled_i16_i8(i16* %base, <4 x i8>* %offptr) {
|
||||
; CHECK-LABEL: zext_signed_scaled_i16_i8:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.s32 q0, [r1]
|
||||
; CHECK-NEXT: vshl.i32 q0, q0, #1
|
||||
; CHECK-NEXT: vadd.i32 q0, q0, r0
|
||||
; CHECK-NEXT: vmov r2, s0
|
||||
; CHECK-NEXT: vmov r0, s1
|
||||
; CHECK-NEXT: vmov r3, s2
|
||||
; CHECK-NEXT: vmov r1, s3
|
||||
; CHECK-NEXT: ldrh r2, [r2]
|
||||
; CHECK-NEXT: ldrh r0, [r0]
|
||||
; CHECK-NEXT: vmov.32 q0[0], r2
|
||||
; CHECK-NEXT: ldrh r3, [r3]
|
||||
; CHECK-NEXT: vmov.32 q0[1], r0
|
||||
; CHECK-NEXT: ldrh r1, [r1]
|
||||
; CHECK-NEXT: vmov.32 q0[2], r3
|
||||
; CHECK-NEXT: vmov.32 q0[3], r1
|
||||
; CHECK-NEXT: vmovlb.u16 q0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i8>, <4 x i8>* %offptr, align 1
|
||||
%offs.sext = sext <4 x i8> %offs to <4 x i32>
|
||||
%ptrs = getelementptr inbounds i16, i16* %base, <4 x i32> %offs.sext
|
||||
%gather = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> %ptrs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i16> undef)
|
||||
%gather.zext = zext <4 x i16> %gather to <4 x i32>
|
||||
ret <4 x i32> %gather.zext
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @sext_signed_scaled_i16_i8(i16* %base, <4 x i8>* %offptr) {
|
||||
; CHECK-LABEL: sext_signed_scaled_i16_i8:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.s32 q0, [r1]
|
||||
; CHECK-NEXT: vshl.i32 q0, q0, #1
|
||||
; CHECK-NEXT: vadd.i32 q0, q0, r0
|
||||
; CHECK-NEXT: vmov r2, s0
|
||||
; CHECK-NEXT: vmov r0, s1
|
||||
; CHECK-NEXT: vmov r3, s2
|
||||
; CHECK-NEXT: vmov r1, s3
|
||||
; CHECK-NEXT: ldrh r2, [r2]
|
||||
; CHECK-NEXT: ldrh r0, [r0]
|
||||
; CHECK-NEXT: vmov.32 q0[0], r2
|
||||
; CHECK-NEXT: ldrh r3, [r3]
|
||||
; CHECK-NEXT: vmov.32 q0[1], r0
|
||||
; CHECK-NEXT: ldrh r1, [r1]
|
||||
; CHECK-NEXT: vmov.32 q0[2], r3
|
||||
; CHECK-NEXT: vmov.32 q0[3], r1
|
||||
; CHECK-NEXT: vmovlb.s16 q0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i8>, <4 x i8>* %offptr, align 1
|
||||
%offs.sext = sext <4 x i8> %offs to <4 x i32>
|
||||
%ptrs = getelementptr inbounds i16, i16* %base, <4 x i32> %offs.sext
|
||||
%gather = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> %ptrs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i16> undef)
|
||||
%gather.sext = sext <4 x i16> %gather to <4 x i32>
|
||||
ret <4 x i32> %gather.sext
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @zext_unsigned_scaled_i16_i8(i16* %base, <4 x i8>* %offptr) {
|
||||
; CHECK-LABEL: zext_unsigned_scaled_i16_i8:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u32 q0, [r1]
|
||||
; CHECK-NEXT: vshl.i32 q0, q0, #1
|
||||
; CHECK-NEXT: vadd.i32 q0, q0, r0
|
||||
; CHECK-NEXT: vmov r2, s0
|
||||
; CHECK-NEXT: vmov r0, s1
|
||||
; CHECK-NEXT: vmov r3, s2
|
||||
; CHECK-NEXT: vmov r1, s3
|
||||
; CHECK-NEXT: ldrh r2, [r2]
|
||||
; CHECK-NEXT: ldrh r0, [r0]
|
||||
; CHECK-NEXT: vmov.32 q0[0], r2
|
||||
; CHECK-NEXT: ldrh r3, [r3]
|
||||
; CHECK-NEXT: vmov.32 q0[1], r0
|
||||
; CHECK-NEXT: ldrh r1, [r1]
|
||||
; CHECK-NEXT: vmov.32 q0[2], r3
|
||||
; CHECK-NEXT: vmov.32 q0[3], r1
|
||||
; CHECK-NEXT: vmovlb.u16 q0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i8>, <4 x i8>* %offptr, align 1
|
||||
%offs.zext = zext <4 x i8> %offs to <4 x i32>
|
||||
%ptrs = getelementptr inbounds i16, i16* %base, <4 x i32> %offs.zext
|
||||
%gather = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> %ptrs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i16> undef)
|
||||
%gather.zext = zext <4 x i16> %gather to <4 x i32>
|
||||
ret <4 x i32> %gather.zext
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @sext_unsigned_scaled_i16_i8(i16* %base, <4 x i8>* %offptr) {
|
||||
; CHECK-LABEL: sext_unsigned_scaled_i16_i8:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u32 q0, [r1]
|
||||
; CHECK-NEXT: vshl.i32 q0, q0, #1
|
||||
; CHECK-NEXT: vadd.i32 q0, q0, r0
|
||||
; CHECK-NEXT: vmov r2, s0
|
||||
; CHECK-NEXT: vmov r0, s1
|
||||
; CHECK-NEXT: vmov r3, s2
|
||||
; CHECK-NEXT: vmov r1, s3
|
||||
; CHECK-NEXT: ldrh r2, [r2]
|
||||
; CHECK-NEXT: ldrh r0, [r0]
|
||||
; CHECK-NEXT: vmov.32 q0[0], r2
|
||||
; CHECK-NEXT: ldrh r3, [r3]
|
||||
; CHECK-NEXT: vmov.32 q0[1], r0
|
||||
; CHECK-NEXT: ldrh r1, [r1]
|
||||
; CHECK-NEXT: vmov.32 q0[2], r3
|
||||
; CHECK-NEXT: vmov.32 q0[3], r1
|
||||
; CHECK-NEXT: vmovlb.s16 q0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i8>, <4 x i8>* %offptr, align 1
|
||||
%offs.zext = zext <4 x i8> %offs to <4 x i32>
|
||||
%ptrs = getelementptr inbounds i16, i16* %base, <4 x i32> %offs.zext
|
||||
%gather = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> %ptrs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i16> undef)
|
||||
%gather.sext = sext <4 x i16> %gather to <4 x i32>
|
||||
ret <4 x i32> %gather.sext
|
||||
}
|
||||
|
||||
declare <4 x i8> @llvm.masked.gather.v4i8.v4p0i8(<4 x i8*>, i32, <4 x i1>, <4 x i8>)
|
||||
declare <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*>, i32, <4 x i1>, <4 x i16>)
|
||||
declare <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*>, i32, <4 x i1>, <4 x i32>)
|
||||
declare <4 x half> @llvm.masked.gather.v4f16.v4p0f16(<4 x half*>, i32, <4 x i1>, <4 x half>)
|
||||
declare <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*>, i32, <4 x i1>, <4 x float>)
|
||||
742
test/CodeGen/Thumb2/mve-gather-ind32-unscaled.ll
Normal file
742
test/CodeGen/Thumb2/mve-gather-ind32-unscaled.ll
Normal file
@ -0,0 +1,742 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o 2>/dev/null - | FileCheck %s
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @zext_unscaled_i8_i32(i8* %base, <4 x i32>* %offptr) {
|
||||
; CHECK-LABEL: zext_unscaled_i8_i32:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r1]
|
||||
; CHECK-NEXT: vmov.i32 q1, #0xff
|
||||
; CHECK-NEXT: vadd.i32 q0, q0, r0
|
||||
; CHECK-NEXT: vmov r2, s0
|
||||
; CHECK-NEXT: vmov r1, s1
|
||||
; CHECK-NEXT: vmov r3, s2
|
||||
; CHECK-NEXT: vmov r0, s3
|
||||
; CHECK-NEXT: ldrb r2, [r2]
|
||||
; CHECK-NEXT: ldrb r1, [r1]
|
||||
; CHECK-NEXT: vmov.32 q0[0], r2
|
||||
; CHECK-NEXT: ldrb r3, [r3]
|
||||
; CHECK-NEXT: vmov.32 q0[1], r1
|
||||
; CHECK-NEXT: ldrb r0, [r0]
|
||||
; CHECK-NEXT: vmov.32 q0[2], r3
|
||||
; CHECK-NEXT: vmov.32 q0[3], r0
|
||||
; CHECK-NEXT: vand q0, q0, q1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i32>, <4 x i32>* %offptr, align 4
|
||||
%ptrs = getelementptr inbounds i8, i8* %base, <4 x i32> %offs
|
||||
%gather = call <4 x i8> @llvm.masked.gather.v4i8.v4p0i8(<4 x i8*> %ptrs, i32 1, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i8> undef)
|
||||
%gather.zext = zext <4 x i8> %gather to <4 x i32>
|
||||
ret <4 x i32> %gather.zext
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @sext_unscaled_i8_i32(i8* %base, <4 x i32>* %offptr) {
|
||||
; CHECK-LABEL: sext_unscaled_i8_i32:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r1]
|
||||
; CHECK-NEXT: vadd.i32 q0, q0, r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmov r3, s1
|
||||
; CHECK-NEXT: vmov r1, s2
|
||||
; CHECK-NEXT: vmov r2, s3
|
||||
; CHECK-NEXT: ldrb r0, [r0]
|
||||
; CHECK-NEXT: ldrb r3, [r3]
|
||||
; CHECK-NEXT: vmov.32 q0[0], r0
|
||||
; CHECK-NEXT: ldrb r1, [r1]
|
||||
; CHECK-NEXT: vmov.32 q0[1], r3
|
||||
; CHECK-NEXT: ldrb r2, [r2]
|
||||
; CHECK-NEXT: vmov.32 q0[2], r1
|
||||
; CHECK-NEXT: vmov.32 q0[3], r2
|
||||
; CHECK-NEXT: vmovlb.s8 q0, q0
|
||||
; CHECK-NEXT: vmovlb.s16 q0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i32>, <4 x i32>* %offptr, align 4
|
||||
%ptrs = getelementptr inbounds i8, i8* %base, <4 x i32> %offs
|
||||
%gather = call <4 x i8> @llvm.masked.gather.v4i8.v4p0i8(<4 x i8*> %ptrs, i32 1, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i8> undef)
|
||||
%gather.sext = sext <4 x i8> %gather to <4 x i32>
|
||||
ret <4 x i32> %gather.sext
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @zext_unscaled_i16_i32(i8* %base, <4 x i32>* %offptr) {
|
||||
; CHECK-LABEL: zext_unscaled_i16_i32:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r1]
|
||||
; CHECK-NEXT: vadd.i32 q0, q0, r0
|
||||
; CHECK-NEXT: vmov r2, s0
|
||||
; CHECK-NEXT: vmov r0, s1
|
||||
; CHECK-NEXT: vmov r3, s2
|
||||
; CHECK-NEXT: vmov r1, s3
|
||||
; CHECK-NEXT: ldrh r2, [r2]
|
||||
; CHECK-NEXT: ldrh r0, [r0]
|
||||
; CHECK-NEXT: vmov.32 q0[0], r2
|
||||
; CHECK-NEXT: ldrh r3, [r3]
|
||||
; CHECK-NEXT: vmov.32 q0[1], r0
|
||||
; CHECK-NEXT: ldrh r1, [r1]
|
||||
; CHECK-NEXT: vmov.32 q0[2], r3
|
||||
; CHECK-NEXT: vmov.32 q0[3], r1
|
||||
; CHECK-NEXT: vmovlb.u16 q0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i32>, <4 x i32>* %offptr, align 4
|
||||
%byte_ptrs = getelementptr inbounds i8, i8* %base, <4 x i32> %offs
|
||||
%ptrs = bitcast <4 x i8*> %byte_ptrs to <4 x i16*>
|
||||
%gather = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> %ptrs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i16> undef)
|
||||
%gather.zext = zext <4 x i16> %gather to <4 x i32>
|
||||
ret <4 x i32> %gather.zext
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @sext_unscaled_i16_i32(i8* %base, <4 x i32>* %offptr) {
|
||||
; CHECK-LABEL: sext_unscaled_i16_i32:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r1]
|
||||
; CHECK-NEXT: vadd.i32 q0, q0, r0
|
||||
; CHECK-NEXT: vmov r2, s0
|
||||
; CHECK-NEXT: vmov r0, s1
|
||||
; CHECK-NEXT: vmov r3, s2
|
||||
; CHECK-NEXT: vmov r1, s3
|
||||
; CHECK-NEXT: ldrh r2, [r2]
|
||||
; CHECK-NEXT: ldrh r0, [r0]
|
||||
; CHECK-NEXT: vmov.32 q0[0], r2
|
||||
; CHECK-NEXT: ldrh r3, [r3]
|
||||
; CHECK-NEXT: vmov.32 q0[1], r0
|
||||
; CHECK-NEXT: ldrh r1, [r1]
|
||||
; CHECK-NEXT: vmov.32 q0[2], r3
|
||||
; CHECK-NEXT: vmov.32 q0[3], r1
|
||||
; CHECK-NEXT: vmovlb.s16 q0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i32>, <4 x i32>* %offptr, align 4
|
||||
%byte_ptrs = getelementptr inbounds i8, i8* %base, <4 x i32> %offs
|
||||
%ptrs = bitcast <4 x i8*> %byte_ptrs to <4 x i16*>
|
||||
%gather = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> %ptrs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i16> undef)
|
||||
%gather.sext = sext <4 x i16> %gather to <4 x i32>
|
||||
ret <4 x i32> %gather.sext
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @unscaled_i32_i32(i8* %base, <4 x i32>* %offptr) {
|
||||
; CHECK-LABEL: unscaled_i32_i32:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r1]
|
||||
; CHECK-NEXT: vadd.i32 q1, q0, r0
|
||||
; CHECK-NEXT: vldrw.u32 q0, [q1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i32>, <4 x i32>* %offptr, align 4
|
||||
%byte_ptrs = getelementptr inbounds i8, i8* %base, <4 x i32> %offs
|
||||
%ptrs = bitcast <4 x i8*> %byte_ptrs to <4 x i32*>
|
||||
%gather = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef)
|
||||
ret <4 x i32> %gather
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x float> @unscaled_f32_i32(i8* %base, <4 x i32>* %offptr) {
|
||||
; CHECK-LABEL: unscaled_f32_i32:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r1]
|
||||
; CHECK-NEXT: vadd.i32 q1, q0, r0
|
||||
; CHECK-NEXT: vldrw.u32 q0, [q1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i32>, <4 x i32>* %offptr, align 4
|
||||
%byte_ptrs = getelementptr inbounds i8, i8* %base, <4 x i32> %offs
|
||||
%ptrs = bitcast <4 x i8*> %byte_ptrs to <4 x float*>
|
||||
%gather = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x float> undef)
|
||||
ret <4 x float> %gather
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @unsigned_unscaled_b_i32_i16(i8* %base, <4 x i16>* %offptr) {
|
||||
; CHECK-LABEL: unsigned_unscaled_b_i32_i16:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.u32 q0, [r1]
|
||||
; CHECK-NEXT: vadd.i32 q1, q0, r0
|
||||
; CHECK-NEXT: vldrw.u32 q0, [q1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i16>, <4 x i16>* %offptr, align 2
|
||||
%offs.zext = zext <4 x i16> %offs to <4 x i32>
|
||||
%byte_ptrs = getelementptr inbounds i8, i8* %base, <4 x i32> %offs.zext
|
||||
%ptrs = bitcast <4 x i8*> %byte_ptrs to <4 x i32*>
|
||||
%gather = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef)
|
||||
ret <4 x i32> %gather
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @signed_unscaled_i32_i16(i8* %base, <4 x i16>* %offptr) {
|
||||
; CHECK-LABEL: signed_unscaled_i32_i16:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.s32 q0, [r1]
|
||||
; CHECK-NEXT: vadd.i32 q1, q0, r0
|
||||
; CHECK-NEXT: vldrw.u32 q0, [q1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i16>, <4 x i16>* %offptr, align 2
|
||||
%offs.sext = sext <4 x i16> %offs to <4 x i32>
|
||||
%byte_ptrs = getelementptr inbounds i8, i8* %base, <4 x i32> %offs.sext
|
||||
%ptrs = bitcast <4 x i8*> %byte_ptrs to <4 x i32*>
|
||||
%gather = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef)
|
||||
ret <4 x i32> %gather
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x float> @a_unsigned_unscaled_f32_i16(i8* %base, <4 x i16>* %offptr) {
|
||||
; CHECK-LABEL: a_unsigned_unscaled_f32_i16:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.u32 q0, [r1]
|
||||
; CHECK-NEXT: vadd.i32 q1, q0, r0
|
||||
; CHECK-NEXT: vldrw.u32 q0, [q1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i16>, <4 x i16>* %offptr, align 2
|
||||
%offs.zext = zext <4 x i16> %offs to <4 x i32>
|
||||
%byte_ptrs = getelementptr inbounds i8, i8* %base, <4 x i32> %offs.zext
|
||||
%ptrs = bitcast <4 x i8*> %byte_ptrs to <4 x float*>
|
||||
%gather = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x float> undef)
|
||||
ret <4 x float> %gather
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x float> @b_signed_unscaled_f32_i16(i8* %base, <4 x i16>* %offptr) {
|
||||
; CHECK-LABEL: b_signed_unscaled_f32_i16:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.s32 q0, [r1]
|
||||
; CHECK-NEXT: vadd.i32 q1, q0, r0
|
||||
; CHECK-NEXT: vldrw.u32 q0, [q1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i16>, <4 x i16>* %offptr, align 2
|
||||
%offs.sext = sext <4 x i16> %offs to <4 x i32>
|
||||
%byte_ptrs = getelementptr inbounds i8, i8* %base, <4 x i32> %offs.sext
|
||||
%ptrs = bitcast <4 x i8*> %byte_ptrs to <4 x float*>
|
||||
%gather = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x float> undef)
|
||||
ret <4 x float> %gather
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @zext_signed_unscaled_i16_i16(i8* %base, <4 x i16>* %offptr) {
|
||||
; CHECK-LABEL: zext_signed_unscaled_i16_i16:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.s32 q0, [r1]
|
||||
; CHECK-NEXT: vadd.i32 q0, q0, r0
|
||||
; CHECK-NEXT: vmov r2, s0
|
||||
; CHECK-NEXT: vmov r0, s1
|
||||
; CHECK-NEXT: vmov r3, s2
|
||||
; CHECK-NEXT: vmov r1, s3
|
||||
; CHECK-NEXT: ldrh r2, [r2]
|
||||
; CHECK-NEXT: ldrh r0, [r0]
|
||||
; CHECK-NEXT: vmov.32 q0[0], r2
|
||||
; CHECK-NEXT: ldrh r3, [r3]
|
||||
; CHECK-NEXT: vmov.32 q0[1], r0
|
||||
; CHECK-NEXT: ldrh r1, [r1]
|
||||
; CHECK-NEXT: vmov.32 q0[2], r3
|
||||
; CHECK-NEXT: vmov.32 q0[3], r1
|
||||
; CHECK-NEXT: vmovlb.u16 q0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i16>, <4 x i16>* %offptr, align 2
|
||||
%offs.sext = sext <4 x i16> %offs to <4 x i32>
|
||||
%byte_ptrs = getelementptr inbounds i8, i8* %base, <4 x i32> %offs.sext
|
||||
%ptrs = bitcast <4 x i8*> %byte_ptrs to <4 x i16*>
|
||||
%gather = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> %ptrs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i16> undef)
|
||||
%gather.zext = zext <4 x i16> %gather to <4 x i32>
|
||||
ret <4 x i32> %gather.zext
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @sext_signed_unscaled_i16_i16(i8* %base, <4 x i16>* %offptr) {
|
||||
; CHECK-LABEL: sext_signed_unscaled_i16_i16:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.s32 q0, [r1]
|
||||
; CHECK-NEXT: vadd.i32 q0, q0, r0
|
||||
; CHECK-NEXT: vmov r2, s0
|
||||
; CHECK-NEXT: vmov r0, s1
|
||||
; CHECK-NEXT: vmov r3, s2
|
||||
; CHECK-NEXT: vmov r1, s3
|
||||
; CHECK-NEXT: ldrh r2, [r2]
|
||||
; CHECK-NEXT: ldrh r0, [r0]
|
||||
; CHECK-NEXT: vmov.32 q0[0], r2
|
||||
; CHECK-NEXT: ldrh r3, [r3]
|
||||
; CHECK-NEXT: vmov.32 q0[1], r0
|
||||
; CHECK-NEXT: ldrh r1, [r1]
|
||||
; CHECK-NEXT: vmov.32 q0[2], r3
|
||||
; CHECK-NEXT: vmov.32 q0[3], r1
|
||||
; CHECK-NEXT: vmovlb.s16 q0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i16>, <4 x i16>* %offptr, align 2
|
||||
%offs.sext = sext <4 x i16> %offs to <4 x i32>
|
||||
%byte_ptrs = getelementptr inbounds i8, i8* %base, <4 x i32> %offs.sext
|
||||
%ptrs = bitcast <4 x i8*> %byte_ptrs to <4 x i16*>
|
||||
%gather = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> %ptrs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i16> undef)
|
||||
%gather.sext = sext <4 x i16> %gather to <4 x i32>
|
||||
ret <4 x i32> %gather.sext
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @zext_unsigned_unscaled_i16_i16(i8* %base, <4 x i16>* %offptr) {
|
||||
; CHECK-LABEL: zext_unsigned_unscaled_i16_i16:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.u32 q0, [r1]
|
||||
; CHECK-NEXT: vadd.i32 q0, q0, r0
|
||||
; CHECK-NEXT: vmov r2, s0
|
||||
; CHECK-NEXT: vmov r0, s1
|
||||
; CHECK-NEXT: vmov r3, s2
|
||||
; CHECK-NEXT: vmov r1, s3
|
||||
; CHECK-NEXT: ldrh r2, [r2]
|
||||
; CHECK-NEXT: ldrh r0, [r0]
|
||||
; CHECK-NEXT: vmov.32 q0[0], r2
|
||||
; CHECK-NEXT: ldrh r3, [r3]
|
||||
; CHECK-NEXT: vmov.32 q0[1], r0
|
||||
; CHECK-NEXT: ldrh r1, [r1]
|
||||
; CHECK-NEXT: vmov.32 q0[2], r3
|
||||
; CHECK-NEXT: vmov.32 q0[3], r1
|
||||
; CHECK-NEXT: vmovlb.u16 q0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i16>, <4 x i16>* %offptr, align 2
|
||||
%offs.zext = zext <4 x i16> %offs to <4 x i32>
|
||||
%byte_ptrs = getelementptr inbounds i8, i8* %base, <4 x i32> %offs.zext
|
||||
%ptrs = bitcast <4 x i8*> %byte_ptrs to <4 x i16*>
|
||||
%gather = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> %ptrs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i16> undef)
|
||||
%gather.zext = zext <4 x i16> %gather to <4 x i32>
|
||||
ret <4 x i32> %gather.zext
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @sext_unsigned_unscaled_i16_i16(i8* %base, <4 x i16>* %offptr) {
|
||||
; CHECK-LABEL: sext_unsigned_unscaled_i16_i16:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.u32 q0, [r1]
|
||||
; CHECK-NEXT: vadd.i32 q0, q0, r0
|
||||
; CHECK-NEXT: vmov r2, s0
|
||||
; CHECK-NEXT: vmov r0, s1
|
||||
; CHECK-NEXT: vmov r3, s2
|
||||
; CHECK-NEXT: vmov r1, s3
|
||||
; CHECK-NEXT: ldrh r2, [r2]
|
||||
; CHECK-NEXT: ldrh r0, [r0]
|
||||
; CHECK-NEXT: vmov.32 q0[0], r2
|
||||
; CHECK-NEXT: ldrh r3, [r3]
|
||||
; CHECK-NEXT: vmov.32 q0[1], r0
|
||||
; CHECK-NEXT: ldrh r1, [r1]
|
||||
; CHECK-NEXT: vmov.32 q0[2], r3
|
||||
; CHECK-NEXT: vmov.32 q0[3], r1
|
||||
; CHECK-NEXT: vmovlb.s16 q0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i16>, <4 x i16>* %offptr, align 2
|
||||
%offs.zext = zext <4 x i16> %offs to <4 x i32>
|
||||
%byte_ptrs = getelementptr inbounds i8, i8* %base, <4 x i32> %offs.zext
|
||||
%ptrs = bitcast <4 x i8*> %byte_ptrs to <4 x i16*>
|
||||
%gather = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> %ptrs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i16> undef)
|
||||
%gather.sext = sext <4 x i16> %gather to <4 x i32>
|
||||
ret <4 x i32> %gather.sext
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @zext_signed_unscaled_i8_i16(i8* %base, <4 x i16>* %offptr) {
|
||||
; CHECK-LABEL: zext_signed_unscaled_i8_i16:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.s32 q0, [r1]
|
||||
; CHECK-NEXT: vmov.i32 q1, #0xff
|
||||
; CHECK-NEXT: vadd.i32 q0, q0, r0
|
||||
; CHECK-NEXT: vmov r2, s0
|
||||
; CHECK-NEXT: vmov r1, s1
|
||||
; CHECK-NEXT: vmov r3, s2
|
||||
; CHECK-NEXT: vmov r0, s3
|
||||
; CHECK-NEXT: ldrb r2, [r2]
|
||||
; CHECK-NEXT: ldrb r1, [r1]
|
||||
; CHECK-NEXT: vmov.32 q0[0], r2
|
||||
; CHECK-NEXT: ldrb r3, [r3]
|
||||
; CHECK-NEXT: vmov.32 q0[1], r1
|
||||
; CHECK-NEXT: ldrb r0, [r0]
|
||||
; CHECK-NEXT: vmov.32 q0[2], r3
|
||||
; CHECK-NEXT: vmov.32 q0[3], r0
|
||||
; CHECK-NEXT: vand q0, q0, q1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i16>, <4 x i16>* %offptr, align 2
|
||||
%offs.sext = sext <4 x i16> %offs to <4 x i32>
|
||||
%ptrs = getelementptr inbounds i8, i8* %base, <4 x i32> %offs.sext
|
||||
%gather = call <4 x i8> @llvm.masked.gather.v4i8.v4p0i8(<4 x i8*> %ptrs, i32 1, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i8> undef)
|
||||
%gather.zext = zext <4 x i8> %gather to <4 x i32>
|
||||
ret <4 x i32> %gather.zext
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @sext_signed_unscaled_i8_i16(i8* %base, <4 x i16>* %offptr) {
|
||||
; CHECK-LABEL: sext_signed_unscaled_i8_i16:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.s32 q0, [r1]
|
||||
; CHECK-NEXT: vadd.i32 q0, q0, r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmov r3, s1
|
||||
; CHECK-NEXT: vmov r1, s2
|
||||
; CHECK-NEXT: vmov r2, s3
|
||||
; CHECK-NEXT: ldrb r0, [r0]
|
||||
; CHECK-NEXT: ldrb r3, [r3]
|
||||
; CHECK-NEXT: vmov.32 q0[0], r0
|
||||
; CHECK-NEXT: ldrb r1, [r1]
|
||||
; CHECK-NEXT: vmov.32 q0[1], r3
|
||||
; CHECK-NEXT: ldrb r2, [r2]
|
||||
; CHECK-NEXT: vmov.32 q0[2], r1
|
||||
; CHECK-NEXT: vmov.32 q0[3], r2
|
||||
; CHECK-NEXT: vmovlb.s8 q0, q0
|
||||
; CHECK-NEXT: vmovlb.s16 q0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i16>, <4 x i16>* %offptr, align 2
|
||||
%offs.sext = sext <4 x i16> %offs to <4 x i32>
|
||||
%ptrs = getelementptr inbounds i8, i8* %base, <4 x i32> %offs.sext
|
||||
%gather = call <4 x i8> @llvm.masked.gather.v4i8.v4p0i8(<4 x i8*> %ptrs, i32 1, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i8> undef)
|
||||
%gather.sext = sext <4 x i8> %gather to <4 x i32>
|
||||
ret <4 x i32> %gather.sext
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @zext_unsigned_unscaled_i8_i16(i8* %base, <4 x i16>* %offptr) {
|
||||
; CHECK-LABEL: zext_unsigned_unscaled_i8_i16:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.u32 q0, [r1]
|
||||
; CHECK-NEXT: vmov.i32 q1, #0xff
|
||||
; CHECK-NEXT: vadd.i32 q0, q0, r0
|
||||
; CHECK-NEXT: vmov r2, s0
|
||||
; CHECK-NEXT: vmov r1, s1
|
||||
; CHECK-NEXT: vmov r3, s2
|
||||
; CHECK-NEXT: vmov r0, s3
|
||||
; CHECK-NEXT: ldrb r2, [r2]
|
||||
; CHECK-NEXT: ldrb r1, [r1]
|
||||
; CHECK-NEXT: vmov.32 q0[0], r2
|
||||
; CHECK-NEXT: ldrb r3, [r3]
|
||||
; CHECK-NEXT: vmov.32 q0[1], r1
|
||||
; CHECK-NEXT: ldrb r0, [r0]
|
||||
; CHECK-NEXT: vmov.32 q0[2], r3
|
||||
; CHECK-NEXT: vmov.32 q0[3], r0
|
||||
; CHECK-NEXT: vand q0, q0, q1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i16>, <4 x i16>* %offptr, align 2
|
||||
%offs.zext = zext <4 x i16> %offs to <4 x i32>
|
||||
%ptrs = getelementptr inbounds i8, i8* %base, <4 x i32> %offs.zext
|
||||
%gather = call <4 x i8> @llvm.masked.gather.v4i8.v4p0i8(<4 x i8*> %ptrs, i32 1, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i8> undef)
|
||||
%gather.zext = zext <4 x i8> %gather to <4 x i32>
|
||||
ret <4 x i32> %gather.zext
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @sext_unsigned_unscaled_i8_i16(i8* %base, <4 x i16>* %offptr) {
|
||||
; CHECK-LABEL: sext_unsigned_unscaled_i8_i16:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.u32 q0, [r1]
|
||||
; CHECK-NEXT: vadd.i32 q0, q0, r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmov r3, s1
|
||||
; CHECK-NEXT: vmov r1, s2
|
||||
; CHECK-NEXT: vmov r2, s3
|
||||
; CHECK-NEXT: ldrb r0, [r0]
|
||||
; CHECK-NEXT: ldrb r3, [r3]
|
||||
; CHECK-NEXT: vmov.32 q0[0], r0
|
||||
; CHECK-NEXT: ldrb r1, [r1]
|
||||
; CHECK-NEXT: vmov.32 q0[1], r3
|
||||
; CHECK-NEXT: ldrb r2, [r2]
|
||||
; CHECK-NEXT: vmov.32 q0[2], r1
|
||||
; CHECK-NEXT: vmov.32 q0[3], r2
|
||||
; CHECK-NEXT: vmovlb.s8 q0, q0
|
||||
; CHECK-NEXT: vmovlb.s16 q0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i16>, <4 x i16>* %offptr, align 2
|
||||
%offs.zext = zext <4 x i16> %offs to <4 x i32>
|
||||
%ptrs = getelementptr inbounds i8, i8* %base, <4 x i32> %offs.zext
|
||||
%gather = call <4 x i8> @llvm.masked.gather.v4i8.v4p0i8(<4 x i8*> %ptrs, i32 1, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i8> undef)
|
||||
%gather.sext = sext <4 x i8> %gather to <4 x i32>
|
||||
ret <4 x i32> %gather.sext
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @unsigned_unscaled_b_i32_i8(i8* %base, <4 x i8>* %offptr) {
|
||||
; CHECK-LABEL: unsigned_unscaled_b_i32_i8:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u32 q0, [r1]
|
||||
; CHECK-NEXT: vadd.i32 q1, q0, r0
|
||||
; CHECK-NEXT: vldrw.u32 q0, [q1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i8>, <4 x i8>* %offptr, align 1
|
||||
%offs.zext = zext <4 x i8> %offs to <4 x i32>
|
||||
%byte_ptrs = getelementptr inbounds i8, i8* %base, <4 x i32> %offs.zext
|
||||
%ptrs = bitcast <4 x i8*> %byte_ptrs to <4 x i32*>
|
||||
%gather = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef)
|
||||
ret <4 x i32> %gather
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @signed_unscaled_i32_i8(i8* %base, <4 x i8>* %offptr) {
|
||||
; CHECK-LABEL: signed_unscaled_i32_i8:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.s32 q0, [r1]
|
||||
; CHECK-NEXT: vadd.i32 q1, q0, r0
|
||||
; CHECK-NEXT: vldrw.u32 q0, [q1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i8>, <4 x i8>* %offptr, align 1
|
||||
%offs.sext = sext <4 x i8> %offs to <4 x i32>
|
||||
%byte_ptrs = getelementptr inbounds i8, i8* %base, <4 x i32> %offs.sext
|
||||
%ptrs = bitcast <4 x i8*> %byte_ptrs to <4 x i32*>
|
||||
%gather = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef)
|
||||
ret <4 x i32> %gather
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x float> @a_unsigned_unscaled_f32_i8(i8* %base, <4 x i8>* %offptr) {
|
||||
; CHECK-LABEL: a_unsigned_unscaled_f32_i8:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u32 q0, [r1]
|
||||
; CHECK-NEXT: vadd.i32 q1, q0, r0
|
||||
; CHECK-NEXT: vldrw.u32 q0, [q1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i8>, <4 x i8>* %offptr, align 1
|
||||
%offs.zext = zext <4 x i8> %offs to <4 x i32>
|
||||
%byte_ptrs = getelementptr inbounds i8, i8* %base, <4 x i32> %offs.zext
|
||||
%ptrs = bitcast <4 x i8*> %byte_ptrs to <4 x float*>
|
||||
%gather = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x float> undef)
|
||||
ret <4 x float> %gather
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x float> @b_signed_unscaled_f32_i8(i8* %base, <4 x i8>* %offptr) {
|
||||
; CHECK-LABEL: b_signed_unscaled_f32_i8:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.s32 q0, [r1]
|
||||
; CHECK-NEXT: vadd.i32 q1, q0, r0
|
||||
; CHECK-NEXT: vldrw.u32 q0, [q1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i8>, <4 x i8>* %offptr, align 1
|
||||
%offs.sext = sext <4 x i8> %offs to <4 x i32>
|
||||
%byte_ptrs = getelementptr inbounds i8, i8* %base, <4 x i32> %offs.sext
|
||||
%ptrs = bitcast <4 x i8*> %byte_ptrs to <4 x float*>
|
||||
%gather = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x float> undef)
|
||||
ret <4 x float> %gather
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @zext_signed_unscaled_i16_i8(i8* %base, <4 x i8>* %offptr) {
|
||||
; CHECK-LABEL: zext_signed_unscaled_i16_i8:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.s32 q0, [r1]
|
||||
; CHECK-NEXT: vadd.i32 q0, q0, r0
|
||||
; CHECK-NEXT: vmov r2, s0
|
||||
; CHECK-NEXT: vmov r0, s1
|
||||
; CHECK-NEXT: vmov r3, s2
|
||||
; CHECK-NEXT: vmov r1, s3
|
||||
; CHECK-NEXT: ldrh r2, [r2]
|
||||
; CHECK-NEXT: ldrh r0, [r0]
|
||||
; CHECK-NEXT: vmov.32 q0[0], r2
|
||||
; CHECK-NEXT: ldrh r3, [r3]
|
||||
; CHECK-NEXT: vmov.32 q0[1], r0
|
||||
; CHECK-NEXT: ldrh r1, [r1]
|
||||
; CHECK-NEXT: vmov.32 q0[2], r3
|
||||
; CHECK-NEXT: vmov.32 q0[3], r1
|
||||
; CHECK-NEXT: vmovlb.u16 q0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i8>, <4 x i8>* %offptr, align 1
|
||||
%offs.sext = sext <4 x i8> %offs to <4 x i32>
|
||||
%byte_ptrs = getelementptr inbounds i8, i8* %base, <4 x i32> %offs.sext
|
||||
%ptrs = bitcast <4 x i8*> %byte_ptrs to <4 x i16*>
|
||||
%gather = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> %ptrs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i16> undef)
|
||||
%gather.zext = zext <4 x i16> %gather to <4 x i32>
|
||||
ret <4 x i32> %gather.zext
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @sext_signed_unscaled_i16_i8(i8* %base, <4 x i8>* %offptr) {
|
||||
; CHECK-LABEL: sext_signed_unscaled_i16_i8:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.s32 q0, [r1]
|
||||
; CHECK-NEXT: vadd.i32 q0, q0, r0
|
||||
; CHECK-NEXT: vmov r2, s0
|
||||
; CHECK-NEXT: vmov r0, s1
|
||||
; CHECK-NEXT: vmov r3, s2
|
||||
; CHECK-NEXT: vmov r1, s3
|
||||
; CHECK-NEXT: ldrh r2, [r2]
|
||||
; CHECK-NEXT: ldrh r0, [r0]
|
||||
; CHECK-NEXT: vmov.32 q0[0], r2
|
||||
; CHECK-NEXT: ldrh r3, [r3]
|
||||
; CHECK-NEXT: vmov.32 q0[1], r0
|
||||
; CHECK-NEXT: ldrh r1, [r1]
|
||||
; CHECK-NEXT: vmov.32 q0[2], r3
|
||||
; CHECK-NEXT: vmov.32 q0[3], r1
|
||||
; CHECK-NEXT: vmovlb.s16 q0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i8>, <4 x i8>* %offptr, align 1
|
||||
%offs.sext = sext <4 x i8> %offs to <4 x i32>
|
||||
%byte_ptrs = getelementptr inbounds i8, i8* %base, <4 x i32> %offs.sext
|
||||
%ptrs = bitcast <4 x i8*> %byte_ptrs to <4 x i16*>
|
||||
%gather = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> %ptrs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i16> undef)
|
||||
%gather.sext = sext <4 x i16> %gather to <4 x i32>
|
||||
ret <4 x i32> %gather.sext
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @zext_unsigned_unscaled_i16_i8(i8* %base, <4 x i8>* %offptr) {
|
||||
; CHECK-LABEL: zext_unsigned_unscaled_i16_i8:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u32 q0, [r1]
|
||||
; CHECK-NEXT: vadd.i32 q0, q0, r0
|
||||
; CHECK-NEXT: vmov r2, s0
|
||||
; CHECK-NEXT: vmov r0, s1
|
||||
; CHECK-NEXT: vmov r3, s2
|
||||
; CHECK-NEXT: vmov r1, s3
|
||||
; CHECK-NEXT: ldrh r2, [r2]
|
||||
; CHECK-NEXT: ldrh r0, [r0]
|
||||
; CHECK-NEXT: vmov.32 q0[0], r2
|
||||
; CHECK-NEXT: ldrh r3, [r3]
|
||||
; CHECK-NEXT: vmov.32 q0[1], r0
|
||||
; CHECK-NEXT: ldrh r1, [r1]
|
||||
; CHECK-NEXT: vmov.32 q0[2], r3
|
||||
; CHECK-NEXT: vmov.32 q0[3], r1
|
||||
; CHECK-NEXT: vmovlb.u16 q0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i8>, <4 x i8>* %offptr, align 1
|
||||
%offs.zext = zext <4 x i8> %offs to <4 x i32>
|
||||
%byte_ptrs = getelementptr inbounds i8, i8* %base, <4 x i32> %offs.zext
|
||||
%ptrs = bitcast <4 x i8*> %byte_ptrs to <4 x i16*>
|
||||
%gather = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> %ptrs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i16> undef)
|
||||
%gather.zext = zext <4 x i16> %gather to <4 x i32>
|
||||
ret <4 x i32> %gather.zext
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @sext_unsigned_unscaled_i16_i8(i8* %base, <4 x i8>* %offptr) {
|
||||
; CHECK-LABEL: sext_unsigned_unscaled_i16_i8:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u32 q0, [r1]
|
||||
; CHECK-NEXT: vadd.i32 q0, q0, r0
|
||||
; CHECK-NEXT: vmov r2, s0
|
||||
; CHECK-NEXT: vmov r0, s1
|
||||
; CHECK-NEXT: vmov r3, s2
|
||||
; CHECK-NEXT: vmov r1, s3
|
||||
; CHECK-NEXT: ldrh r2, [r2]
|
||||
; CHECK-NEXT: ldrh r0, [r0]
|
||||
; CHECK-NEXT: vmov.32 q0[0], r2
|
||||
; CHECK-NEXT: ldrh r3, [r3]
|
||||
; CHECK-NEXT: vmov.32 q0[1], r0
|
||||
; CHECK-NEXT: ldrh r1, [r1]
|
||||
; CHECK-NEXT: vmov.32 q0[2], r3
|
||||
; CHECK-NEXT: vmov.32 q0[3], r1
|
||||
; CHECK-NEXT: vmovlb.s16 q0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i8>, <4 x i8>* %offptr, align 1
|
||||
%offs.zext = zext <4 x i8> %offs to <4 x i32>
|
||||
%byte_ptrs = getelementptr inbounds i8, i8* %base, <4 x i32> %offs.zext
|
||||
%ptrs = bitcast <4 x i8*> %byte_ptrs to <4 x i16*>
|
||||
%gather = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> %ptrs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i16> undef)
|
||||
%gather.sext = sext <4 x i16> %gather to <4 x i32>
|
||||
ret <4 x i32> %gather.sext
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @zext_signed_unscaled_i8_i8(i8* %base, <4 x i8>* %offptr) {
|
||||
; CHECK-LABEL: zext_signed_unscaled_i8_i8:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.s32 q0, [r1]
|
||||
; CHECK-NEXT: vmov.i32 q1, #0xff
|
||||
; CHECK-NEXT: vadd.i32 q0, q0, r0
|
||||
; CHECK-NEXT: vmov r2, s0
|
||||
; CHECK-NEXT: vmov r1, s1
|
||||
; CHECK-NEXT: vmov r3, s2
|
||||
; CHECK-NEXT: vmov r0, s3
|
||||
; CHECK-NEXT: ldrb r2, [r2]
|
||||
; CHECK-NEXT: ldrb r1, [r1]
|
||||
; CHECK-NEXT: vmov.32 q0[0], r2
|
||||
; CHECK-NEXT: ldrb r3, [r3]
|
||||
; CHECK-NEXT: vmov.32 q0[1], r1
|
||||
; CHECK-NEXT: ldrb r0, [r0]
|
||||
; CHECK-NEXT: vmov.32 q0[2], r3
|
||||
; CHECK-NEXT: vmov.32 q0[3], r0
|
||||
; CHECK-NEXT: vand q0, q0, q1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i8>, <4 x i8>* %offptr, align 1
|
||||
%offs.sext = sext <4 x i8> %offs to <4 x i32>
|
||||
%ptrs = getelementptr inbounds i8, i8* %base, <4 x i32> %offs.sext
|
||||
%gather = call <4 x i8> @llvm.masked.gather.v4i8.v4p0i8(<4 x i8*> %ptrs, i32 1, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i8> undef)
|
||||
%gather.zext = zext <4 x i8> %gather to <4 x i32>
|
||||
ret <4 x i32> %gather.zext
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @sext_signed_unscaled_i8_i8(i8* %base, <4 x i8>* %offptr) {
|
||||
; CHECK-LABEL: sext_signed_unscaled_i8_i8:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.s32 q0, [r1]
|
||||
; CHECK-NEXT: vadd.i32 q0, q0, r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmov r3, s1
|
||||
; CHECK-NEXT: vmov r1, s2
|
||||
; CHECK-NEXT: vmov r2, s3
|
||||
; CHECK-NEXT: ldrb r0, [r0]
|
||||
; CHECK-NEXT: ldrb r3, [r3]
|
||||
; CHECK-NEXT: vmov.32 q0[0], r0
|
||||
; CHECK-NEXT: ldrb r1, [r1]
|
||||
; CHECK-NEXT: vmov.32 q0[1], r3
|
||||
; CHECK-NEXT: ldrb r2, [r2]
|
||||
; CHECK-NEXT: vmov.32 q0[2], r1
|
||||
; CHECK-NEXT: vmov.32 q0[3], r2
|
||||
; CHECK-NEXT: vmovlb.s8 q0, q0
|
||||
; CHECK-NEXT: vmovlb.s16 q0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i8>, <4 x i8>* %offptr, align 1
|
||||
%offs.sext = sext <4 x i8> %offs to <4 x i32>
|
||||
%ptrs = getelementptr inbounds i8, i8* %base, <4 x i32> %offs.sext
|
||||
%gather = call <4 x i8> @llvm.masked.gather.v4i8.v4p0i8(<4 x i8*> %ptrs, i32 1, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i8> undef)
|
||||
%gather.sext = sext <4 x i8> %gather to <4 x i32>
|
||||
ret <4 x i32> %gather.sext
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @zext_unsigned_unscaled_i8_i8(i8* %base, <4 x i8>* %offptr) {
|
||||
; CHECK-LABEL: zext_unsigned_unscaled_i8_i8:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u32 q0, [r1]
|
||||
; CHECK-NEXT: vmov.i32 q1, #0xff
|
||||
; CHECK-NEXT: vadd.i32 q0, q0, r0
|
||||
; CHECK-NEXT: vmov r2, s0
|
||||
; CHECK-NEXT: vmov r1, s1
|
||||
; CHECK-NEXT: vmov r3, s2
|
||||
; CHECK-NEXT: vmov r0, s3
|
||||
; CHECK-NEXT: ldrb r2, [r2]
|
||||
; CHECK-NEXT: ldrb r1, [r1]
|
||||
; CHECK-NEXT: vmov.32 q0[0], r2
|
||||
; CHECK-NEXT: ldrb r3, [r3]
|
||||
; CHECK-NEXT: vmov.32 q0[1], r1
|
||||
; CHECK-NEXT: ldrb r0, [r0]
|
||||
; CHECK-NEXT: vmov.32 q0[2], r3
|
||||
; CHECK-NEXT: vmov.32 q0[3], r0
|
||||
; CHECK-NEXT: vand q0, q0, q1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i8>, <4 x i8>* %offptr, align 1
|
||||
%offs.zext = zext <4 x i8> %offs to <4 x i32>
|
||||
%ptrs = getelementptr inbounds i8, i8* %base, <4 x i32> %offs.zext
|
||||
%gather = call <4 x i8> @llvm.masked.gather.v4i8.v4p0i8(<4 x i8*> %ptrs, i32 1, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i8> undef)
|
||||
%gather.zext = zext <4 x i8> %gather to <4 x i32>
|
||||
ret <4 x i32> %gather.zext
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @sext_unsigned_unscaled_i8_i8(i8* %base, <4 x i8>* %offptr) {
|
||||
; CHECK-LABEL: sext_unsigned_unscaled_i8_i8:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u32 q0, [r1]
|
||||
; CHECK-NEXT: vadd.i32 q0, q0, r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmov r3, s1
|
||||
; CHECK-NEXT: vmov r1, s2
|
||||
; CHECK-NEXT: vmov r2, s3
|
||||
; CHECK-NEXT: ldrb r0, [r0]
|
||||
; CHECK-NEXT: ldrb r3, [r3]
|
||||
; CHECK-NEXT: vmov.32 q0[0], r0
|
||||
; CHECK-NEXT: ldrb r1, [r1]
|
||||
; CHECK-NEXT: vmov.32 q0[1], r3
|
||||
; CHECK-NEXT: ldrb r2, [r2]
|
||||
; CHECK-NEXT: vmov.32 q0[2], r1
|
||||
; CHECK-NEXT: vmov.32 q0[3], r2
|
||||
; CHECK-NEXT: vmovlb.s8 q0, q0
|
||||
; CHECK-NEXT: vmovlb.s16 q0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i8>, <4 x i8>* %offptr, align 1
|
||||
%offs.zext = zext <4 x i8> %offs to <4 x i32>
|
||||
%ptrs = getelementptr inbounds i8, i8* %base, <4 x i32> %offs.zext
|
||||
%gather = call <4 x i8> @llvm.masked.gather.v4i8.v4p0i8(<4 x i8*> %ptrs, i32 1, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i8> undef)
|
||||
%gather.sext = sext <4 x i8> %gather to <4 x i32>
|
||||
ret <4 x i32> %gather.sext
|
||||
}
|
||||
|
||||
declare <4 x i8> @llvm.masked.gather.v4i8.v4p0i8(<4 x i8*>, i32, <4 x i1>, <4 x i8>)
|
||||
declare <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*>, i32, <4 x i1>, <4 x i16>)
|
||||
declare <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*>, i32, <4 x i1>, <4 x i32>)
|
||||
declare <4 x half> @llvm.masked.gather.v4f16.v4p0f16(<4 x half*>, i32, <4 x i1>, <4 x half>)
|
||||
declare <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*>, i32, <4 x i1>, <4 x float>)
|
||||
850
test/CodeGen/Thumb2/mve-gather-ptrs.ll
Normal file
850
test/CodeGen/Thumb2/mve-gather-ptrs.ll
Normal file
@ -0,0 +1,850 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -enable-arm-maskedldst -enable-arm-maskedgatscat %s -o - | FileCheck %s
|
||||
|
||||
; i32
|
||||
|
||||
define arm_aapcs_vfpcc <2 x i32> @ptr_v2i32(<2 x i32*>* %offptr) {
|
||||
; CHECK-LABEL: ptr_v2i32:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: ldrd r1, r0, [r0]
|
||||
; CHECK-NEXT: ldr r0, [r0]
|
||||
; CHECK-NEXT: ldr r1, [r1]
|
||||
; CHECK-NEXT: vmov.32 q0[0], r1
|
||||
; CHECK-NEXT: vmov.32 q0[2], r0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <2 x i32*>, <2 x i32*>* %offptr, align 4
|
||||
%gather = call <2 x i32> @llvm.masked.gather.v2i32.v2p0i32(<2 x i32*> %offs, i32 4, <2 x i1> <i1 true, i1 true>, <2 x i32> undef)
|
||||
ret <2 x i32> %gather
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @ptr_v4i32(<4 x i32*>* %offptr) {
|
||||
; CHECK-LABEL: ptr_v4i32:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrw.u32 q1, [r0]
|
||||
; CHECK-NEXT: vldrw.u32 q0, [q1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i32*>, <4 x i32*>* %offptr, align 4
|
||||
%gather = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %offs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef)
|
||||
ret <4 x i32> %gather
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <8 x i32> @ptr_v8i32(<8 x i32*>* %offptr) {
|
||||
; CHECK-LABEL: ptr_v8i32:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .save {r4, r5, r7, lr}
|
||||
; CHECK-NEXT: push {r4, r5, r7, lr}
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r0]
|
||||
; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
|
||||
; CHECK-NEXT: vmov r1, s2
|
||||
; CHECK-NEXT: vmov r2, s3
|
||||
; CHECK-NEXT: vmov r3, s0
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmov r5, s1
|
||||
; CHECK-NEXT: vmov r4, s7
|
||||
; CHECK-NEXT: ldr.w r12, [r1]
|
||||
; CHECK-NEXT: vmov r1, s5
|
||||
; CHECK-NEXT: ldr.w lr, [r2]
|
||||
; CHECK-NEXT: vmov r2, s6
|
||||
; CHECK-NEXT: ldr r3, [r3]
|
||||
; CHECK-NEXT: ldr r0, [r0]
|
||||
; CHECK-NEXT: ldr r5, [r5]
|
||||
; CHECK-NEXT: vmov.32 q0[0], r3
|
||||
; CHECK-NEXT: vmov.32 q1[0], r0
|
||||
; CHECK-NEXT: ldr r4, [r4]
|
||||
; CHECK-NEXT: vmov.32 q0[1], r5
|
||||
; CHECK-NEXT: vmov.32 q0[2], r12
|
||||
; CHECK-NEXT: vmov.32 q0[3], lr
|
||||
; CHECK-NEXT: ldr r1, [r1]
|
||||
; CHECK-NEXT: ldr r2, [r2]
|
||||
; CHECK-NEXT: vmov.32 q1[1], r1
|
||||
; CHECK-NEXT: vmov.32 q1[2], r2
|
||||
; CHECK-NEXT: vmov.32 q1[3], r4
|
||||
; CHECK-NEXT: pop {r4, r5, r7, pc}
|
||||
entry:
|
||||
%offs = load <8 x i32*>, <8 x i32*>* %offptr, align 4
|
||||
%gather = call <8 x i32> @llvm.masked.gather.v8i32.v8p0i32(<8 x i32*> %offs, i32 4, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i32> undef)
|
||||
ret <8 x i32> %gather
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <16 x i32> @ptr_v16i32(<16 x i32*>* %offptr) {
|
||||
; CHECK-LABEL: ptr_v16i32:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .save {r4, r5, r6, lr}
|
||||
; CHECK-NEXT: push {r4, r5, r6, lr}
|
||||
; CHECK-NEXT: vldrw.u32 q2, [r0, #32]
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r0, #48]
|
||||
; CHECK-NEXT: vldrw.u32 q1, [r0]
|
||||
; CHECK-NEXT: vldrw.u32 q3, [r0, #16]
|
||||
; CHECK-NEXT: vmov r1, s10
|
||||
; CHECK-NEXT: vmov r5, s4
|
||||
; CHECK-NEXT: vmov r2, s3
|
||||
; CHECK-NEXT: vmov r0, s12
|
||||
; CHECK-NEXT: vmov r6, s7
|
||||
; CHECK-NEXT: vmov r4, s11
|
||||
; CHECK-NEXT: ldr.w r12, [r1]
|
||||
; CHECK-NEXT: vmov r1, s0
|
||||
; CHECK-NEXT: ldr r5, [r5]
|
||||
; CHECK-NEXT: ldr r2, [r2]
|
||||
; CHECK-NEXT: ldr r0, [r0]
|
||||
; CHECK-NEXT: ldr r6, [r6]
|
||||
; CHECK-NEXT: ldr r4, [r4]
|
||||
; CHECK-NEXT: ldr.w lr, [r1]
|
||||
; CHECK-NEXT: vmov r1, s1
|
||||
; CHECK-NEXT: ldr r3, [r1]
|
||||
; CHECK-NEXT: vmov r1, s2
|
||||
; CHECK-NEXT: vmov.32 q0[0], r5
|
||||
; CHECK-NEXT: vmov r5, s5
|
||||
; CHECK-NEXT: ldr r1, [r1]
|
||||
; CHECK-NEXT: ldr r5, [r5]
|
||||
; CHECK-NEXT: vmov.32 q0[1], r5
|
||||
; CHECK-NEXT: vmov r5, s6
|
||||
; CHECK-NEXT: vmov.32 q1[0], r0
|
||||
; CHECK-NEXT: vmov r0, s13
|
||||
; CHECK-NEXT: ldr r5, [r5]
|
||||
; CHECK-NEXT: ldr r0, [r0]
|
||||
; CHECK-NEXT: vmov.32 q0[2], r5
|
||||
; CHECK-NEXT: vmov r5, s8
|
||||
; CHECK-NEXT: vmov.32 q1[1], r0
|
||||
; CHECK-NEXT: vmov r0, s14
|
||||
; CHECK-NEXT: vmov.32 q0[3], r6
|
||||
; CHECK-NEXT: ldr r5, [r5]
|
||||
; CHECK-NEXT: ldr r0, [r0]
|
||||
; CHECK-NEXT: vmov.32 q1[2], r0
|
||||
; CHECK-NEXT: vmov r0, s15
|
||||
; CHECK-NEXT: vmov.32 q3[0], lr
|
||||
; CHECK-NEXT: vmov.32 q3[1], r3
|
||||
; CHECK-NEXT: vmov.32 q3[2], r1
|
||||
; CHECK-NEXT: vmov.32 q3[3], r2
|
||||
; CHECK-NEXT: ldr r0, [r0]
|
||||
; CHECK-NEXT: vmov.32 q1[3], r0
|
||||
; CHECK-NEXT: vmov r0, s9
|
||||
; CHECK-NEXT: vmov.32 q2[0], r5
|
||||
; CHECK-NEXT: ldr r0, [r0]
|
||||
; CHECK-NEXT: vmov.32 q2[1], r0
|
||||
; CHECK-NEXT: vmov.32 q2[2], r12
|
||||
; CHECK-NEXT: vmov.32 q2[3], r4
|
||||
; CHECK-NEXT: pop {r4, r5, r6, pc}
|
||||
entry:
|
||||
%offs = load <16 x i32*>, <16 x i32*>* %offptr, align 4
|
||||
%gather = call <16 x i32> @llvm.masked.gather.v16i32.v16p0i32(<16 x i32*> %offs, i32 4, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <16 x i32> undef)
|
||||
ret <16 x i32> %gather
|
||||
}
|
||||
|
||||
; f32
|
||||
|
||||
define arm_aapcs_vfpcc <2 x float> @ptr_v2f32(<2 x float*>* %offptr) {
|
||||
; CHECK-LABEL: ptr_v2f32:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: ldrd r1, r0, [r0]
|
||||
; CHECK-NEXT: vldr s1, [r0]
|
||||
; CHECK-NEXT: vldr s0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <2 x float*>, <2 x float*>* %offptr, align 4
|
||||
%gather = call <2 x float> @llvm.masked.gather.v2f32.v2p0f32(<2 x float*> %offs, i32 4, <2 x i1> <i1 true, i1 true>, <2 x float> undef)
|
||||
ret <2 x float> %gather
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x float> @ptr_v4f32(<4 x float*>* %offptr) {
|
||||
; CHECK-LABEL: ptr_v4f32:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrw.u32 q1, [r0]
|
||||
; CHECK-NEXT: vldrw.u32 q0, [q1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x float*>, <4 x float*>* %offptr, align 4
|
||||
%gather = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> %offs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x float> undef)
|
||||
ret <4 x float> %gather
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <8 x float> @ptr_v8f32(<8 x float*>* %offptr) {
|
||||
; CHECK-LABEL: ptr_v8f32:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrw.u32 q1, [r0]
|
||||
; CHECK-NEXT: vldrw.u32 q2, [r0, #16]
|
||||
; CHECK-NEXT: vmov r1, s7
|
||||
; CHECK-NEXT: vmov r0, s11
|
||||
; CHECK-NEXT: vldr s3, [r1]
|
||||
; CHECK-NEXT: vmov r1, s6
|
||||
; CHECK-NEXT: vldr s2, [r1]
|
||||
; CHECK-NEXT: vmov r1, s5
|
||||
; CHECK-NEXT: vldr s1, [r1]
|
||||
; CHECK-NEXT: vmov r1, s4
|
||||
; CHECK-NEXT: vldr s7, [r0]
|
||||
; CHECK-NEXT: vmov r0, s10
|
||||
; CHECK-NEXT: vldr s0, [r1]
|
||||
; CHECK-NEXT: vldr s6, [r0]
|
||||
; CHECK-NEXT: vmov r0, s9
|
||||
; CHECK-NEXT: vldr s5, [r0]
|
||||
; CHECK-NEXT: vmov r0, s8
|
||||
; CHECK-NEXT: vldr s4, [r0]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <8 x float*>, <8 x float*>* %offptr, align 4
|
||||
%gather = call <8 x float> @llvm.masked.gather.v8f32.v8p0f32(<8 x float*> %offs, i32 4, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x float> undef)
|
||||
ret <8 x float> %gather
|
||||
}
|
||||
|
||||
; i16
|
||||
|
||||
define arm_aapcs_vfpcc <8 x i16> @ptr_i16(<8 x i16*>* %offptr) {
|
||||
; CHECK-LABEL: ptr_i16:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .save {r4, r5, r7, lr}
|
||||
; CHECK-NEXT: push {r4, r5, r7, lr}
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r0]
|
||||
; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
|
||||
; CHECK-NEXT: vmov r1, s2
|
||||
; CHECK-NEXT: vmov r2, s3
|
||||
; CHECK-NEXT: vmov r3, s0
|
||||
; CHECK-NEXT: vmov r5, s1
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmov r4, s7
|
||||
; CHECK-NEXT: ldrh.w r12, [r1]
|
||||
; CHECK-NEXT: vmov r1, s5
|
||||
; CHECK-NEXT: ldrh.w lr, [r2]
|
||||
; CHECK-NEXT: vmov r2, s6
|
||||
; CHECK-NEXT: ldrh r3, [r3]
|
||||
; CHECK-NEXT: ldrh r5, [r5]
|
||||
; CHECK-NEXT: vmov.16 q0[0], r3
|
||||
; CHECK-NEXT: ldrh r0, [r0]
|
||||
; CHECK-NEXT: vmov.16 q0[1], r5
|
||||
; CHECK-NEXT: ldrh r4, [r4]
|
||||
; CHECK-NEXT: vmov.16 q0[2], r12
|
||||
; CHECK-NEXT: vmov.16 q0[3], lr
|
||||
; CHECK-NEXT: vmov.16 q0[4], r0
|
||||
; CHECK-NEXT: ldrh r1, [r1]
|
||||
; CHECK-NEXT: ldrh r2, [r2]
|
||||
; CHECK-NEXT: vmov.16 q0[5], r1
|
||||
; CHECK-NEXT: vmov.16 q0[6], r2
|
||||
; CHECK-NEXT: vmov.16 q0[7], r4
|
||||
; CHECK-NEXT: pop {r4, r5, r7, pc}
|
||||
entry:
|
||||
%offs = load <8 x i16*>, <8 x i16*>* %offptr, align 4
|
||||
%gather = call <8 x i16> @llvm.masked.gather.v8i16.v8p0i16(<8 x i16*> %offs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i16> undef)
|
||||
ret <8 x i16> %gather
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <2 x i32> @ptr_v2i16_sext(<2 x i16*>* %offptr) {
|
||||
; CHECK-LABEL: ptr_v2i16_sext:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: ldrd r1, r0, [r0]
|
||||
; CHECK-NEXT: ldrsh.w r0, [r0]
|
||||
; CHECK-NEXT: ldrsh.w r1, [r1]
|
||||
; CHECK-NEXT: asrs r2, r0, #31
|
||||
; CHECK-NEXT: vmov.32 q0[0], r1
|
||||
; CHECK-NEXT: asrs r1, r1, #31
|
||||
; CHECK-NEXT: vmov.32 q0[1], r1
|
||||
; CHECK-NEXT: vmov.32 q0[2], r0
|
||||
; CHECK-NEXT: vmov.32 q0[3], r2
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <2 x i16*>, <2 x i16*>* %offptr, align 4
|
||||
%gather = call <2 x i16> @llvm.masked.gather.v2i16.v2p0i16(<2 x i16*> %offs, i32 2, <2 x i1> <i1 true, i1 true>, <2 x i16> undef)
|
||||
%ext = sext <2 x i16> %gather to <2 x i32>
|
||||
ret <2 x i32> %ext
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <2 x i32> @ptr_v2i16_zext(<2 x i16*>* %offptr) {
|
||||
; CHECK-LABEL: ptr_v2i16_zext:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: ldrd r1, r0, [r0]
|
||||
; CHECK-NEXT: adr r2, .LCPI9_0
|
||||
; CHECK-NEXT: ldrh r0, [r0]
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r2]
|
||||
; CHECK-NEXT: ldrh r1, [r1]
|
||||
; CHECK-NEXT: vmov.32 q1[0], r1
|
||||
; CHECK-NEXT: vmov.32 q1[2], r0
|
||||
; CHECK-NEXT: vand q0, q1, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
; CHECK-NEXT: .p2align 4
|
||||
; CHECK-NEXT: @ %bb.1:
|
||||
; CHECK-NEXT: .LCPI9_0:
|
||||
; CHECK-NEXT: .long 65535 @ 0xffff
|
||||
; CHECK-NEXT: .long 0 @ 0x0
|
||||
; CHECK-NEXT: .long 65535 @ 0xffff
|
||||
; CHECK-NEXT: .long 0 @ 0x0
|
||||
entry:
|
||||
%offs = load <2 x i16*>, <2 x i16*>* %offptr, align 4
|
||||
%gather = call <2 x i16> @llvm.masked.gather.v2i16.v2p0i16(<2 x i16*> %offs, i32 2, <2 x i1> <i1 true, i1 true>, <2 x i16> undef)
|
||||
%ext = zext <2 x i16> %gather to <2 x i32>
|
||||
ret <2 x i32> %ext
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @ptr_v4i16_sext(<4 x i16*>* %offptr) {
|
||||
; CHECK-LABEL: ptr_v4i16_sext:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r0]
|
||||
; CHECK-NEXT: vmov r2, s0
|
||||
; CHECK-NEXT: vmov r0, s1
|
||||
; CHECK-NEXT: vmov r3, s2
|
||||
; CHECK-NEXT: vmov r1, s3
|
||||
; CHECK-NEXT: ldrh r2, [r2]
|
||||
; CHECK-NEXT: ldrh r0, [r0]
|
||||
; CHECK-NEXT: vmov.32 q0[0], r2
|
||||
; CHECK-NEXT: ldrh r3, [r3]
|
||||
; CHECK-NEXT: vmov.32 q0[1], r0
|
||||
; CHECK-NEXT: ldrh r1, [r1]
|
||||
; CHECK-NEXT: vmov.32 q0[2], r3
|
||||
; CHECK-NEXT: vmov.32 q0[3], r1
|
||||
; CHECK-NEXT: vmovlb.s16 q0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i16*>, <4 x i16*>* %offptr, align 4
|
||||
%gather = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> %offs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i16> undef)
|
||||
%ext = sext <4 x i16> %gather to <4 x i32>
|
||||
ret <4 x i32> %ext
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @ptr_v4i16_zext(<4 x i16*>* %offptr) {
|
||||
; CHECK-LABEL: ptr_v4i16_zext:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r0]
|
||||
; CHECK-NEXT: vmov r2, s0
|
||||
; CHECK-NEXT: vmov r0, s1
|
||||
; CHECK-NEXT: vmov r3, s2
|
||||
; CHECK-NEXT: vmov r1, s3
|
||||
; CHECK-NEXT: ldrh r2, [r2]
|
||||
; CHECK-NEXT: ldrh r0, [r0]
|
||||
; CHECK-NEXT: vmov.32 q0[0], r2
|
||||
; CHECK-NEXT: ldrh r3, [r3]
|
||||
; CHECK-NEXT: vmov.32 q0[1], r0
|
||||
; CHECK-NEXT: ldrh r1, [r1]
|
||||
; CHECK-NEXT: vmov.32 q0[2], r3
|
||||
; CHECK-NEXT: vmov.32 q0[3], r1
|
||||
; CHECK-NEXT: vmovlb.u16 q0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i16*>, <4 x i16*>* %offptr, align 4
|
||||
%gather = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> %offs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i16> undef)
|
||||
%ext = zext <4 x i16> %gather to <4 x i32>
|
||||
ret <4 x i32> %ext
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <8 x i32> @ptr_v8i16_sext(<8 x i16*>* %offptr) {
|
||||
; CHECK-LABEL: ptr_v8i16_sext:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .save {r4, r5, r7, lr}
|
||||
; CHECK-NEXT: push {r4, r5, r7, lr}
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r0]
|
||||
; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
|
||||
; CHECK-NEXT: vmov r1, s2
|
||||
; CHECK-NEXT: vmov r2, s3
|
||||
; CHECK-NEXT: vmov r3, s0
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmov r5, s1
|
||||
; CHECK-NEXT: vmov r4, s7
|
||||
; CHECK-NEXT: ldrh.w r12, [r1]
|
||||
; CHECK-NEXT: vmov r1, s5
|
||||
; CHECK-NEXT: ldrh.w lr, [r2]
|
||||
; CHECK-NEXT: vmov r2, s6
|
||||
; CHECK-NEXT: ldrh r3, [r3]
|
||||
; CHECK-NEXT: ldrh r0, [r0]
|
||||
; CHECK-NEXT: ldrh r5, [r5]
|
||||
; CHECK-NEXT: vmov.32 q0[0], r3
|
||||
; CHECK-NEXT: vmov.32 q1[0], r0
|
||||
; CHECK-NEXT: ldrh r4, [r4]
|
||||
; CHECK-NEXT: vmov.32 q0[1], r5
|
||||
; CHECK-NEXT: vmov.32 q0[2], r12
|
||||
; CHECK-NEXT: vmov.32 q0[3], lr
|
||||
; CHECK-NEXT: vmovlb.s16 q0, q0
|
||||
; CHECK-NEXT: ldrh r1, [r1]
|
||||
; CHECK-NEXT: ldrh r2, [r2]
|
||||
; CHECK-NEXT: vmov.32 q1[1], r1
|
||||
; CHECK-NEXT: vmov.32 q1[2], r2
|
||||
; CHECK-NEXT: vmov.32 q1[3], r4
|
||||
; CHECK-NEXT: vmovlb.s16 q1, q1
|
||||
; CHECK-NEXT: pop {r4, r5, r7, pc}
|
||||
entry:
|
||||
%offs = load <8 x i16*>, <8 x i16*>* %offptr, align 4
|
||||
%gather = call <8 x i16> @llvm.masked.gather.v8i16.v8p0i16(<8 x i16*> %offs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i16> undef)
|
||||
%ext = sext <8 x i16> %gather to <8 x i32>
|
||||
ret <8 x i32> %ext
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <8 x i32> @ptr_v8i16_zext(<8 x i16*>* %offptr) {
|
||||
; CHECK-LABEL: ptr_v8i16_zext:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .save {r4, r5, r7, lr}
|
||||
; CHECK-NEXT: push {r4, r5, r7, lr}
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r0]
|
||||
; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
|
||||
; CHECK-NEXT: vmov r1, s2
|
||||
; CHECK-NEXT: vmov r2, s3
|
||||
; CHECK-NEXT: vmov r3, s0
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmov r5, s1
|
||||
; CHECK-NEXT: vmov r4, s7
|
||||
; CHECK-NEXT: ldrh.w r12, [r1]
|
||||
; CHECK-NEXT: vmov r1, s5
|
||||
; CHECK-NEXT: ldrh.w lr, [r2]
|
||||
; CHECK-NEXT: vmov r2, s6
|
||||
; CHECK-NEXT: ldrh r3, [r3]
|
||||
; CHECK-NEXT: ldrh r0, [r0]
|
||||
; CHECK-NEXT: ldrh r5, [r5]
|
||||
; CHECK-NEXT: vmov.32 q0[0], r3
|
||||
; CHECK-NEXT: vmov.32 q1[0], r0
|
||||
; CHECK-NEXT: ldrh r4, [r4]
|
||||
; CHECK-NEXT: vmov.32 q0[1], r5
|
||||
; CHECK-NEXT: vmov.32 q0[2], r12
|
||||
; CHECK-NEXT: vmov.32 q0[3], lr
|
||||
; CHECK-NEXT: vmovlb.u16 q0, q0
|
||||
; CHECK-NEXT: ldrh r1, [r1]
|
||||
; CHECK-NEXT: ldrh r2, [r2]
|
||||
; CHECK-NEXT: vmov.32 q1[1], r1
|
||||
; CHECK-NEXT: vmov.32 q1[2], r2
|
||||
; CHECK-NEXT: vmov.32 q1[3], r4
|
||||
; CHECK-NEXT: vmovlb.u16 q1, q1
|
||||
; CHECK-NEXT: pop {r4, r5, r7, pc}
|
||||
entry:
|
||||
%offs = load <8 x i16*>, <8 x i16*>* %offptr, align 4
|
||||
%gather = call <8 x i16> @llvm.masked.gather.v8i16.v8p0i16(<8 x i16*> %offs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i16> undef)
|
||||
%ext = zext <8 x i16> %gather to <8 x i32>
|
||||
ret <8 x i32> %ext
|
||||
}
|
||||
|
||||
; f16
|
||||
|
||||
define arm_aapcs_vfpcc <8 x half> @ptr_f16(<8 x half*>* %offptr) {
|
||||
; CHECK-LABEL: ptr_f16:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrw.u32 q1, [r0]
|
||||
; CHECK-NEXT: vmov r1, s5
|
||||
; CHECK-NEXT: vldr.16 s0, [r1]
|
||||
; CHECK-NEXT: vmov r2, s4
|
||||
; CHECK-NEXT: vmov r1, s0
|
||||
; CHECK-NEXT: vldr.16 s0, [r2]
|
||||
; CHECK-NEXT: vmov r2, s0
|
||||
; CHECK-NEXT: vmov.16 q0[0], r2
|
||||
; CHECK-NEXT: vmov.16 q0[1], r1
|
||||
; CHECK-NEXT: vmov r1, s6
|
||||
; CHECK-NEXT: vldr.16 s8, [r1]
|
||||
; CHECK-NEXT: vmov r1, s8
|
||||
; CHECK-NEXT: vmov.16 q0[2], r1
|
||||
; CHECK-NEXT: vmov r1, s7
|
||||
; CHECK-NEXT: vldr.16 s4, [r1]
|
||||
; CHECK-NEXT: vmov r1, s4
|
||||
; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
|
||||
; CHECK-NEXT: vmov.16 q0[3], r1
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vldr.16 s8, [r0]
|
||||
; CHECK-NEXT: vmov r0, s8
|
||||
; CHECK-NEXT: vmov.16 q0[4], r0
|
||||
; CHECK-NEXT: vmov r0, s5
|
||||
; CHECK-NEXT: vldr.16 s8, [r0]
|
||||
; CHECK-NEXT: vmov r0, s8
|
||||
; CHECK-NEXT: vmov.16 q0[5], r0
|
||||
; CHECK-NEXT: vmov r0, s6
|
||||
; CHECK-NEXT: vldr.16 s8, [r0]
|
||||
; CHECK-NEXT: vmov r0, s8
|
||||
; CHECK-NEXT: vmov.16 q0[6], r0
|
||||
; CHECK-NEXT: vmov r0, s7
|
||||
; CHECK-NEXT: vldr.16 s4, [r0]
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmov.16 q0[7], r0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <8 x half*>, <8 x half*>* %offptr, align 4
|
||||
%gather = call <8 x half> @llvm.masked.gather.v8f16.v8p0f16(<8 x half*> %offs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x half> undef)
|
||||
ret <8 x half> %gather
|
||||
}
|
||||
|
||||
; i8
|
||||
|
||||
define arm_aapcs_vfpcc <16 x i8> @ptr_i8(<16 x i8*>* %offptr) {
|
||||
; CHECK-LABEL: ptr_i8:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .save {r4, r5, r6, lr}
|
||||
; CHECK-NEXT: push {r4, r5, r6, lr}
|
||||
; CHECK-NEXT: vldrw.u32 q1, [r0, #32]
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r0, #48]
|
||||
; CHECK-NEXT: vldrw.u32 q2, [r0]
|
||||
; CHECK-NEXT: vmov r1, s6
|
||||
; CHECK-NEXT: vmov r5, s8
|
||||
; CHECK-NEXT: vmov r2, s3
|
||||
; CHECK-NEXT: vmov r6, s11
|
||||
; CHECK-NEXT: vmov r4, s7
|
||||
; CHECK-NEXT: ldrb.w r12, [r1]
|
||||
; CHECK-NEXT: vmov r1, s0
|
||||
; CHECK-NEXT: ldrb r5, [r5]
|
||||
; CHECK-NEXT: ldrb r2, [r2]
|
||||
; CHECK-NEXT: ldrb r6, [r6]
|
||||
; CHECK-NEXT: ldrb r4, [r4]
|
||||
; CHECK-NEXT: ldrb.w lr, [r1]
|
||||
; CHECK-NEXT: vmov r1, s1
|
||||
; CHECK-NEXT: ldrb r3, [r1]
|
||||
; CHECK-NEXT: vmov r1, s2
|
||||
; CHECK-NEXT: vmov.8 q0[0], r5
|
||||
; CHECK-NEXT: vmov r5, s9
|
||||
; CHECK-NEXT: ldrb r1, [r1]
|
||||
; CHECK-NEXT: ldrb r5, [r5]
|
||||
; CHECK-NEXT: vmov.8 q0[1], r5
|
||||
; CHECK-NEXT: vmov r5, s10
|
||||
; CHECK-NEXT: vldrw.u32 q2, [r0, #16]
|
||||
; CHECK-NEXT: vmov r0, s8
|
||||
; CHECK-NEXT: ldrb r5, [r5]
|
||||
; CHECK-NEXT: vmov.8 q0[2], r5
|
||||
; CHECK-NEXT: vmov r5, s4
|
||||
; CHECK-NEXT: ldrb r0, [r0]
|
||||
; CHECK-NEXT: vmov.8 q0[3], r6
|
||||
; CHECK-NEXT: vmov.8 q0[4], r0
|
||||
; CHECK-NEXT: vmov r0, s9
|
||||
; CHECK-NEXT: ldrb r5, [r5]
|
||||
; CHECK-NEXT: ldrb r0, [r0]
|
||||
; CHECK-NEXT: vmov.8 q0[5], r0
|
||||
; CHECK-NEXT: vmov r0, s10
|
||||
; CHECK-NEXT: ldrb r0, [r0]
|
||||
; CHECK-NEXT: vmov.8 q0[6], r0
|
||||
; CHECK-NEXT: vmov r0, s11
|
||||
; CHECK-NEXT: ldrb r0, [r0]
|
||||
; CHECK-NEXT: vmov.8 q0[7], r0
|
||||
; CHECK-NEXT: vmov r0, s5
|
||||
; CHECK-NEXT: vmov.8 q0[8], r5
|
||||
; CHECK-NEXT: ldrb r0, [r0]
|
||||
; CHECK-NEXT: vmov.8 q0[9], r0
|
||||
; CHECK-NEXT: vmov.8 q0[10], r12
|
||||
; CHECK-NEXT: vmov.8 q0[11], r4
|
||||
; CHECK-NEXT: vmov.8 q0[12], lr
|
||||
; CHECK-NEXT: vmov.8 q0[13], r3
|
||||
; CHECK-NEXT: vmov.8 q0[14], r1
|
||||
; CHECK-NEXT: vmov.8 q0[15], r2
|
||||
; CHECK-NEXT: pop {r4, r5, r6, pc}
|
||||
entry:
|
||||
%offs = load <16 x i8*>, <16 x i8*>* %offptr, align 4
|
||||
%gather = call <16 x i8> @llvm.masked.gather.v16i8.v16p0i8(<16 x i8*> %offs, i32 2, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <16 x i8> undef)
|
||||
ret <16 x i8> %gather
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <8 x i16> @ptr_v8i8_sext16(<8 x i8*>* %offptr) {
|
||||
; CHECK-LABEL: ptr_v8i8_sext16:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .save {r4, r5, r7, lr}
|
||||
; CHECK-NEXT: push {r4, r5, r7, lr}
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r0]
|
||||
; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
|
||||
; CHECK-NEXT: vmov r2, s3
|
||||
; CHECK-NEXT: vmov r1, s1
|
||||
; CHECK-NEXT: vmov r5, s0
|
||||
; CHECK-NEXT: vmov r3, s2
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmov r4, s7
|
||||
; CHECK-NEXT: ldrb.w r12, [r2]
|
||||
; CHECK-NEXT: vmov r2, s5
|
||||
; CHECK-NEXT: ldrb.w lr, [r1]
|
||||
; CHECK-NEXT: vmov r1, s6
|
||||
; CHECK-NEXT: ldrb r5, [r5]
|
||||
; CHECK-NEXT: ldrb r3, [r3]
|
||||
; CHECK-NEXT: vmov.16 q0[0], r5
|
||||
; CHECK-NEXT: ldrb r0, [r0]
|
||||
; CHECK-NEXT: vmov.16 q0[1], lr
|
||||
; CHECK-NEXT: ldrb r4, [r4]
|
||||
; CHECK-NEXT: vmov.16 q0[2], r3
|
||||
; CHECK-NEXT: vmov.16 q0[3], r12
|
||||
; CHECK-NEXT: vmov.16 q0[4], r0
|
||||
; CHECK-NEXT: ldrb r2, [r2]
|
||||
; CHECK-NEXT: ldrb r1, [r1]
|
||||
; CHECK-NEXT: vmov.16 q0[5], r2
|
||||
; CHECK-NEXT: vmov.16 q0[6], r1
|
||||
; CHECK-NEXT: vmov.16 q0[7], r4
|
||||
; CHECK-NEXT: vmovlb.s8 q0, q0
|
||||
; CHECK-NEXT: pop {r4, r5, r7, pc}
|
||||
entry:
|
||||
%offs = load <8 x i8*>, <8 x i8*>* %offptr, align 4
|
||||
%gather = call <8 x i8> @llvm.masked.gather.v8i8.v8p0i8(<8 x i8*> %offs, i32 1, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i8> undef)
|
||||
%ext = sext <8 x i8> %gather to <8 x i16>
|
||||
ret <8 x i16> %ext
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <8 x i16> @ptr_v8i8_zext16(<8 x i8*>* %offptr) {
|
||||
; CHECK-LABEL: ptr_v8i8_zext16:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .save {r4, r5, r7, lr}
|
||||
; CHECK-NEXT: push {r4, r5, r7, lr}
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r0]
|
||||
; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
|
||||
; CHECK-NEXT: vmov r2, s3
|
||||
; CHECK-NEXT: vmov r1, s1
|
||||
; CHECK-NEXT: vmov r5, s0
|
||||
; CHECK-NEXT: vmov r3, s2
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmov r4, s7
|
||||
; CHECK-NEXT: ldrb.w r12, [r2]
|
||||
; CHECK-NEXT: vmov r2, s5
|
||||
; CHECK-NEXT: ldrb.w lr, [r1]
|
||||
; CHECK-NEXT: vmov r1, s6
|
||||
; CHECK-NEXT: ldrb r5, [r5]
|
||||
; CHECK-NEXT: ldrb r3, [r3]
|
||||
; CHECK-NEXT: vmov.16 q0[0], r5
|
||||
; CHECK-NEXT: ldrb r0, [r0]
|
||||
; CHECK-NEXT: vmov.16 q0[1], lr
|
||||
; CHECK-NEXT: ldrb r4, [r4]
|
||||
; CHECK-NEXT: vmov.16 q0[2], r3
|
||||
; CHECK-NEXT: vmov.16 q0[3], r12
|
||||
; CHECK-NEXT: vmov.16 q0[4], r0
|
||||
; CHECK-NEXT: ldrb r2, [r2]
|
||||
; CHECK-NEXT: ldrb r1, [r1]
|
||||
; CHECK-NEXT: vmov.16 q0[5], r2
|
||||
; CHECK-NEXT: vmov.16 q0[6], r1
|
||||
; CHECK-NEXT: vmov.16 q0[7], r4
|
||||
; CHECK-NEXT: vmovlb.u8 q0, q0
|
||||
; CHECK-NEXT: pop {r4, r5, r7, pc}
|
||||
entry:
|
||||
%offs = load <8 x i8*>, <8 x i8*>* %offptr, align 4
|
||||
%gather = call <8 x i8> @llvm.masked.gather.v8i8.v8p0i8(<8 x i8*> %offs, i32 1, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i8> undef)
|
||||
%ext = zext <8 x i8> %gather to <8 x i16>
|
||||
ret <8 x i16> %ext
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @ptr_v4i8_sext32(<4 x i8*>* %offptr) {
|
||||
; CHECK-LABEL: ptr_v4i8_sext32:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r0]
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmov r3, s1
|
||||
; CHECK-NEXT: vmov r1, s2
|
||||
; CHECK-NEXT: vmov r2, s3
|
||||
; CHECK-NEXT: ldrb r0, [r0]
|
||||
; CHECK-NEXT: ldrb r3, [r3]
|
||||
; CHECK-NEXT: vmov.32 q0[0], r0
|
||||
; CHECK-NEXT: ldrb r1, [r1]
|
||||
; CHECK-NEXT: vmov.32 q0[1], r3
|
||||
; CHECK-NEXT: ldrb r2, [r2]
|
||||
; CHECK-NEXT: vmov.32 q0[2], r1
|
||||
; CHECK-NEXT: vmov.32 q0[3], r2
|
||||
; CHECK-NEXT: vmovlb.s8 q0, q0
|
||||
; CHECK-NEXT: vmovlb.s16 q0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i8*>, <4 x i8*>* %offptr, align 4
|
||||
%gather = call <4 x i8> @llvm.masked.gather.v4i8.v4p0i8(<4 x i8*> %offs, i32 1, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i8> undef)
|
||||
%ext = sext <4 x i8> %gather to <4 x i32>
|
||||
ret <4 x i32> %ext
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @ptr_v4i8_zext32(<4 x i8*>* %offptr) {
|
||||
; CHECK-LABEL: ptr_v4i8_zext32:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r0]
|
||||
; CHECK-NEXT: vmov.i32 q1, #0xff
|
||||
; CHECK-NEXT: vmov r2, s0
|
||||
; CHECK-NEXT: vmov r1, s1
|
||||
; CHECK-NEXT: vmov r3, s2
|
||||
; CHECK-NEXT: vmov r0, s3
|
||||
; CHECK-NEXT: ldrb r2, [r2]
|
||||
; CHECK-NEXT: ldrb r1, [r1]
|
||||
; CHECK-NEXT: vmov.32 q0[0], r2
|
||||
; CHECK-NEXT: ldrb r3, [r3]
|
||||
; CHECK-NEXT: vmov.32 q0[1], r1
|
||||
; CHECK-NEXT: ldrb r0, [r0]
|
||||
; CHECK-NEXT: vmov.32 q0[2], r3
|
||||
; CHECK-NEXT: vmov.32 q0[3], r0
|
||||
; CHECK-NEXT: vand q0, q0, q1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%offs = load <4 x i8*>, <4 x i8*>* %offptr, align 4
|
||||
%gather = call <4 x i8> @llvm.masked.gather.v4i8.v4p0i8(<4 x i8*> %offs, i32 1, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i8> undef)
|
||||
%ext = zext <4 x i8> %gather to <4 x i32>
|
||||
ret <4 x i32> %ext
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <8 x i32> @ptr_v8i8_sext32(<8 x i8*>* %offptr) {
|
||||
; CHECK-LABEL: ptr_v8i8_sext32:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .save {r4, r5, r7, lr}
|
||||
; CHECK-NEXT: push {r4, r5, r7, lr}
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r0]
|
||||
; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
|
||||
; CHECK-NEXT: vmov r1, s2
|
||||
; CHECK-NEXT: vmov r2, s3
|
||||
; CHECK-NEXT: vmov r3, s0
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmov r5, s1
|
||||
; CHECK-NEXT: vmov r4, s7
|
||||
; CHECK-NEXT: ldrb.w r12, [r1]
|
||||
; CHECK-NEXT: vmov r1, s5
|
||||
; CHECK-NEXT: ldrb.w lr, [r2]
|
||||
; CHECK-NEXT: vmov r2, s6
|
||||
; CHECK-NEXT: ldrb r3, [r3]
|
||||
; CHECK-NEXT: ldrb r0, [r0]
|
||||
; CHECK-NEXT: ldrb r5, [r5]
|
||||
; CHECK-NEXT: vmov.32 q0[0], r3
|
||||
; CHECK-NEXT: vmov.32 q1[0], r0
|
||||
; CHECK-NEXT: ldrb r4, [r4]
|
||||
; CHECK-NEXT: vmov.32 q0[1], r5
|
||||
; CHECK-NEXT: vmov.32 q0[2], r12
|
||||
; CHECK-NEXT: vmov.32 q0[3], lr
|
||||
; CHECK-NEXT: vmovlb.s8 q0, q0
|
||||
; CHECK-NEXT: vmovlb.s16 q0, q0
|
||||
; CHECK-NEXT: ldrb r1, [r1]
|
||||
; CHECK-NEXT: ldrb r2, [r2]
|
||||
; CHECK-NEXT: vmov.32 q1[1], r1
|
||||
; CHECK-NEXT: vmov.32 q1[2], r2
|
||||
; CHECK-NEXT: vmov.32 q1[3], r4
|
||||
; CHECK-NEXT: vmovlb.s8 q1, q1
|
||||
; CHECK-NEXT: vmovlb.s16 q1, q1
|
||||
; CHECK-NEXT: pop {r4, r5, r7, pc}
|
||||
entry:
|
||||
%offs = load <8 x i8*>, <8 x i8*>* %offptr, align 4
|
||||
%gather = call <8 x i8> @llvm.masked.gather.v8i8.v8p0i8(<8 x i8*> %offs, i32 1, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i8> undef)
|
||||
%ext = sext <8 x i8> %gather to <8 x i32>
|
||||
ret <8 x i32> %ext
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <8 x i32> @ptr_v8i8_zext32(<8 x i8*>* %offptr) {
|
||||
; CHECK-LABEL: ptr_v8i8_zext32:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .save {r4, r5, r7, lr}
|
||||
; CHECK-NEXT: push {r4, r5, r7, lr}
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r0]
|
||||
; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
|
||||
; CHECK-NEXT: vmov r1, s2
|
||||
; CHECK-NEXT: vmov r2, s3
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmov r4, s0
|
||||
; CHECK-NEXT: vmov r3, s5
|
||||
; CHECK-NEXT: vmov r5, s1
|
||||
; CHECK-NEXT: ldrb.w r12, [r1]
|
||||
; CHECK-NEXT: vmov r1, s6
|
||||
; CHECK-NEXT: ldrb.w lr, [r2]
|
||||
; CHECK-NEXT: vmov r2, s7
|
||||
; CHECK-NEXT: ldrb r0, [r0]
|
||||
; CHECK-NEXT: vmov.i32 q1, #0xff
|
||||
; CHECK-NEXT: ldrb r4, [r4]
|
||||
; CHECK-NEXT: ldrb r3, [r3]
|
||||
; CHECK-NEXT: vmov.32 q2[0], r0
|
||||
; CHECK-NEXT: ldrb r5, [r5]
|
||||
; CHECK-NEXT: vmov.32 q0[0], r4
|
||||
; CHECK-NEXT: vmov.32 q2[1], r3
|
||||
; CHECK-NEXT: vmov.32 q0[1], r5
|
||||
; CHECK-NEXT: vmov.32 q0[2], r12
|
||||
; CHECK-NEXT: vmov.32 q0[3], lr
|
||||
; CHECK-NEXT: vand q0, q0, q1
|
||||
; CHECK-NEXT: ldrb r1, [r1]
|
||||
; CHECK-NEXT: ldrb r2, [r2]
|
||||
; CHECK-NEXT: vmov.32 q2[2], r1
|
||||
; CHECK-NEXT: vmov.32 q2[3], r2
|
||||
; CHECK-NEXT: vand q1, q2, q1
|
||||
; CHECK-NEXT: pop {r4, r5, r7, pc}
|
||||
entry:
|
||||
%offs = load <8 x i8*>, <8 x i8*>* %offptr, align 4
|
||||
%gather = call <8 x i8> @llvm.masked.gather.v8i8.v8p0i8(<8 x i8*> %offs, i32 1, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i8> undef)
|
||||
%ext = zext <8 x i8> %gather to <8 x i32>
|
||||
ret <8 x i32> %ext
|
||||
}
|
||||
|
||||
; loops
|
||||
|
||||
define void @foo_ptr_p_int32_t(i32* %dest, i32** %src, i32 %n) {
|
||||
; CHECK-LABEL: foo_ptr_p_int32_t:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .save {r7, lr}
|
||||
; CHECK-NEXT: push {r7, lr}
|
||||
; CHECK-NEXT: bic r2, r2, #15
|
||||
; CHECK-NEXT: cmp r2, #1
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: poplt {r7, pc}
|
||||
; CHECK-NEXT: subs r2, #4
|
||||
; CHECK-NEXT: movs r3, #1
|
||||
; CHECK-NEXT: subs r1, #16
|
||||
; CHECK-NEXT: add.w lr, r3, r2, lsr #2
|
||||
; CHECK-NEXT: dls lr, lr
|
||||
; CHECK-NEXT: .LBB22_1: @ %vector.body
|
||||
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r1, #16]!
|
||||
; CHECK-NEXT: vptt.i32 ne, q0, zr
|
||||
; CHECK-NEXT: vldrwt.u32 q1, [q0]
|
||||
; CHECK-NEXT: vstrwt.32 q1, [r0], #16
|
||||
; CHECK-NEXT: le lr, .LBB22_1
|
||||
; CHECK-NEXT: @ %bb.2: @ %for.end
|
||||
; CHECK-NEXT: pop {r7, pc}
|
||||
entry:
|
||||
%and = and i32 %n, -16
|
||||
%cmp11 = icmp sgt i32 %and, 0
|
||||
br i1 %cmp11, label %vector.body, label %for.end
|
||||
|
||||
vector.body: ; preds = %entry, %vector.body
|
||||
%index = phi i32 [ %index.next, %vector.body ], [ 0, %entry ]
|
||||
%0 = getelementptr inbounds i32*, i32** %src, i32 %index
|
||||
%1 = bitcast i32** %0 to <4 x i32*>*
|
||||
%wide.load = load <4 x i32*>, <4 x i32*>* %1, align 4
|
||||
%2 = icmp ne <4 x i32*> %wide.load, zeroinitializer
|
||||
%wide.masked.gather = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %wide.load, i32 4, <4 x i1> %2, <4 x i32> undef)
|
||||
%3 = getelementptr inbounds i32, i32* %dest, i32 %index
|
||||
%4 = bitcast i32* %3 to <4 x i32>*
|
||||
call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %wide.masked.gather, <4 x i32>* %4, i32 4, <4 x i1> %2)
|
||||
%index.next = add i32 %index, 4
|
||||
%5 = icmp eq i32 %index.next, %and
|
||||
br i1 %5, label %for.end, label %vector.body
|
||||
|
||||
for.end: ; preds = %vector.body, %entry
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @foo_ptr_p_float(float* %dest, float** %src, i32 %n) {
|
||||
; CHECK-LABEL: foo_ptr_p_float:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .save {r7, lr}
|
||||
; CHECK-NEXT: push {r7, lr}
|
||||
; CHECK-NEXT: bic r2, r2, #15
|
||||
; CHECK-NEXT: cmp r2, #1
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: poplt {r7, pc}
|
||||
; CHECK-NEXT: subs r2, #4
|
||||
; CHECK-NEXT: movs r3, #1
|
||||
; CHECK-NEXT: subs r1, #16
|
||||
; CHECK-NEXT: add.w lr, r3, r2, lsr #2
|
||||
; CHECK-NEXT: dls lr, lr
|
||||
; CHECK-NEXT: .LBB23_1: @ %vector.body
|
||||
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r1, #16]!
|
||||
; CHECK-NEXT: vptt.i32 ne, q0, zr
|
||||
; CHECK-NEXT: vldrwt.u32 q1, [q0]
|
||||
; CHECK-NEXT: vstrwt.32 q1, [r0], #16
|
||||
; CHECK-NEXT: le lr, .LBB23_1
|
||||
; CHECK-NEXT: @ %bb.2: @ %for.end
|
||||
; CHECK-NEXT: pop {r7, pc}
|
||||
entry:
|
||||
%and = and i32 %n, -16
|
||||
%cmp11 = icmp sgt i32 %and, 0
|
||||
br i1 %cmp11, label %vector.body, label %for.end
|
||||
|
||||
vector.body: ; preds = %entry, %vector.body
|
||||
%index = phi i32 [ %index.next, %vector.body ], [ 0, %entry ]
|
||||
%0 = getelementptr inbounds float*, float** %src, i32 %index
|
||||
%1 = bitcast float** %0 to <4 x float*>*
|
||||
%wide.load = load <4 x float*>, <4 x float*>* %1, align 4
|
||||
%2 = icmp ne <4 x float*> %wide.load, zeroinitializer
|
||||
%3 = bitcast <4 x float*> %wide.load to <4 x i32*>
|
||||
%wide.masked.gather = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %3, i32 4, <4 x i1> %2, <4 x i32> undef)
|
||||
%4 = getelementptr inbounds float, float* %dest, i32 %index
|
||||
%5 = bitcast float* %4 to <4 x i32>*
|
||||
call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %wide.masked.gather, <4 x i32>* %5, i32 4, <4 x i1> %2)
|
||||
%index.next = add i32 %index, 4
|
||||
%6 = icmp eq i32 %index.next, %and
|
||||
br i1 %6, label %for.end, label %vector.body
|
||||
|
||||
for.end: ; preds = %vector.body, %entry
|
||||
ret void
|
||||
}
|
||||
|
||||
declare <2 x i32> @llvm.masked.gather.v2i32.v2p0i32(<2 x i32*>, i32, <2 x i1>, <2 x i32>)
|
||||
declare <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*>, i32, <4 x i1>, <4 x i32>)
|
||||
declare <8 x i32> @llvm.masked.gather.v8i32.v8p0i32(<8 x i32*>, i32, <8 x i1>, <8 x i32>)
|
||||
declare <16 x i32> @llvm.masked.gather.v16i32.v16p0i32(<16 x i32*>, i32, <16 x i1>, <16 x i32>)
|
||||
declare <2 x float> @llvm.masked.gather.v2f32.v2p0f32(<2 x float*>, i32, <2 x i1>, <2 x float>)
|
||||
declare <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*>, i32, <4 x i1>, <4 x float>)
|
||||
declare <8 x float> @llvm.masked.gather.v8f32.v8p0f32(<8 x float*>, i32, <8 x i1>, <8 x float>)
|
||||
declare <2 x i16> @llvm.masked.gather.v2i16.v2p0i16(<2 x i16*>, i32, <2 x i1>, <2 x i16>)
|
||||
declare <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*>, i32, <4 x i1>, <4 x i16>)
|
||||
declare <8 x i16> @llvm.masked.gather.v8i16.v8p0i16(<8 x i16*>, i32, <8 x i1>, <8 x i16>)
|
||||
declare <16 x i16> @llvm.masked.gather.v16i16.v16p0i16(<16 x i16*>, i32, <16 x i1>, <16 x i16>)
|
||||
declare <4 x half> @llvm.masked.gather.v4f16.v4p0f16(<4 x half*>, i32, <4 x i1>, <4 x half>)
|
||||
declare <8 x half> @llvm.masked.gather.v8f16.v8p0f16(<8 x half*>, i32, <8 x i1>, <8 x half>)
|
||||
declare <16 x half> @llvm.masked.gather.v16f16.v16p0f16(<16 x half*>, i32, <16 x i1>, <16 x half>)
|
||||
declare <4 x i8> @llvm.masked.gather.v4i8.v4p0i8(<4 x i8*>, i32, <4 x i1>, <4 x i8>)
|
||||
declare <8 x i8> @llvm.masked.gather.v8i8.v8p0i8(<8 x i8*>, i32, <8 x i1>, <8 x i8>)
|
||||
declare <16 x i8> @llvm.masked.gather.v16i8.v16p0i8(<16 x i8*>, i32, <16 x i1>, <16 x i8>)
|
||||
declare <32 x i8> @llvm.masked.gather.v32i8.v32p0i8(<32 x i8*>, i32, <32 x i1>, <32 x i8>)
|
||||
declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32, <4 x i1>)
|
||||
44
test/CodeGen/Thumb2/mve-gather-scatter-opt.ll
Normal file
44
test/CodeGen/Thumb2/mve-gather-scatter-opt.ll
Normal file
@ -0,0 +1,44 @@
|
||||
; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp %s -o 2>/dev/null - | FileCheck --check-prefix NOGATSCAT %s
|
||||
; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=-mve -enable-arm-maskedgatscat %s -o 2>/dev/null - | FileCheck --check-prefix NOMVE %s
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @unscaled_i32_i32(i8* %base, <4 x i32>* %offptr) {
|
||||
; NOGATSCAT-LABEL: unscaled_i32_i32:
|
||||
; NOGATSCAT: @ %bb.0: @ %entry
|
||||
; NOGATSCAT-NEXT: vldrw.u32 q0, [r1]
|
||||
; NOGATSCAT-NEXT: vadd.i32 q0, q0, r0
|
||||
; NOGATSCAT-NEXT: vmov r0, s0
|
||||
; NOGATSCAT-NEXT: vmov r3, s1
|
||||
; NOGATSCAT-NEXT: vmov r1, s2
|
||||
; NOGATSCAT-NEXT: vmov r2, s3
|
||||
; NOGATSCAT-NEXT: ldr r0, [r0]
|
||||
; NOGATSCAT-NEXT: ldr r3, [r3]
|
||||
; NOGATSCAT-NEXT: vmov.32 q0[0], r0
|
||||
; NOGATSCAT-NEXT: ldr r1, [r1]
|
||||
; NOGATSCAT-NEXT: vmov.32 q0[1], r3
|
||||
; NOGATSCAT-NEXT: ldr r2, [r2]
|
||||
; NOGATSCAT-NEXT: vmov.32 q0[2], r1
|
||||
; NOGATSCAT-NEXT: vmov.32 q0[3], r2
|
||||
; NOGATSCAT-NEXT: bx lr
|
||||
|
||||
; NOMVE-LABEL: unscaled_i32_i32:
|
||||
; NOMVE: @ %bb.0: @ %entry
|
||||
; NOMVE-NEXT: .save {r4, lr}
|
||||
; NOMVE-NEXT: push {r4, lr}
|
||||
; NOMVE-NEXT: ldm.w r1, {r2, r3, lr}
|
||||
; NOMVE-NEXT: ldr r4, [r1, #12]
|
||||
; NOMVE-NEXT: ldr.w r12, [r0, r2]
|
||||
; NOMVE-NEXT: ldr r1, [r0, r3]
|
||||
; NOMVE-NEXT: ldr.w r2, [r0, lr]
|
||||
; NOMVE-NEXT: ldr r3, [r0, r4]
|
||||
; NOMVE-NEXT: mov r0, r12
|
||||
; NOMVE-NEXT: pop {r4, pc}
|
||||
|
||||
entry:
|
||||
%offs = load <4 x i32>, <4 x i32>* %offptr, align 4
|
||||
%byte_ptrs = getelementptr inbounds i8, i8* %base, <4 x i32> %offs
|
||||
%ptrs = bitcast <4 x i8*> %byte_ptrs to <4 x i32*>
|
||||
%gather = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef)
|
||||
ret <4 x i32> %gather
|
||||
}
|
||||
|
||||
declare <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*>, i32, <4 x i1>, <4 x i32>)
|
||||
Loading…
Reference in New Issue
Block a user