RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-25 04:02:41 +01:00
Code Issues Projects Releases Wiki Activity

Add support for the "Y" register, used by MUL & DIV.

Browse Source 
llvm-svn: 12734
This commit is contained in:
Brian Gaeke 2004-04-07 04:01:11 +00:00
parent 8651efab54
commit 4b90f62e6d
1 changed files with 9 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
lib/Target/SparcV8/SparcV8RegisterInfo.td
View File

@ -24,6 +24,15 @@ class Rf<bits<5> num> : Register {
class Rd<bits<5> num> : Register { class Rd<bits<5> num> : Register {
field bits<5> Num = num; field bits<5> Num = num;
} }
// Rs - Special "ancillary state registers"
class Rs<bits<5> num> : Register {
field bits<5> Num = num;
}
// Special register used for multiplies and divides
let Namespace = "V8" in {
def Y : Rs<0>;
}
let Namespace = "V8" in { let Namespace = "V8" in {
def G0 : Ri< 0>; def G1 : Ri< 1>; def G2 : Ri< 2>; def G3 : Ri< 3>; def G0 : Ri< 0>; def G1 : Ri< 1>; def G2 : Ri< 2>; def G3 : Ri< 3>;