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Minor changes based on post commit review:

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Contributer: Vladimir Medic
llvm-svn: 165350
This commit is contained in:
Jack Carter 2012-10-06 00:53:28 +00:00
parent 62dbd17b39
commit 4bcd79c34a
1 changed files with 30 additions and 29 deletions
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59
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
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@ -95,9 +95,9 @@ class MipsAsmParser : public MCTargetAsmParser {
bool needsExpansion(MCInst &Inst); bool needsExpansion(MCInst &Inst);
void expandInstruction(MCInst &Inst, SMLoc IDLoc, void expandInstruction(MCInst &Inst, SMLoc IDLoc,
SmallVectorImpl<MCInst*> &Instructions); SmallVectorImpl<MCInst> &Instructions);
void expandLoadImm(MCInst &Inst, SMLoc IDLoc, void expandLoadImm(MCInst &Inst, SMLoc IDLoc,
SmallVectorImpl<MCInst*> &Instructions); SmallVectorImpl<MCInst> &Instructions);
bool reportParseError(StringRef ErrorMsg); bool reportParseError(StringRef ErrorMsg);
bool parseMemOffset(const MCExpr *&Res); bool parseMemOffset(const MCExpr *&Res);
@ -310,59 +310,61 @@ bool MipsAsmParser::needsExpansion(MCInst &Inst) {
return false; return false;
} }
} }
void MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc, void MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
SmallVectorImpl<MCInst*> &Instructions){ SmallVectorImpl<MCInst> &Instructions){
switch(Inst.getOpcode()) { switch(Inst.getOpcode()) {
case Mips::LoadImm32Reg: case Mips::LoadImm32Reg:
return expandLoadImm(Inst, IDLoc, Instructions); return expandLoadImm(Inst, IDLoc, Instructions);
} }
return;
} }
void MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc, void MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc,
SmallVectorImpl<MCInst*> &Instructions){ SmallVectorImpl<MCInst> &Instructions){
MCInst *tmpInst = new MCInst(); MCInst tmpInst;
const MCOperand &ImmOp = Inst.getOperand(1); const MCOperand &ImmOp = Inst.getOperand(1);
assert(ImmOp.isImm() && "expected imediate operand kind"); assert(ImmOp.isImm() && "expected imediate operand kind");
const MCOperand &RegOp = Inst.getOperand(0); const MCOperand &RegOp = Inst.getOperand(0);
assert(RegOp.isReg() && "expected register operand kind"); assert(RegOp.isReg() && "expected register operand kind");
int ImmValue = ImmOp.getImm(); int ImmValue = ImmOp.getImm();
tmpInst->setLoc(IDLoc); tmpInst.setLoc(IDLoc);
if ( 0 <= ImmValue && ImmValue <= 65535) { if ( 0 <= ImmValue && ImmValue <= 65535) {
// for 0 = j = 65535. // for 0 <= j <= 65535.
// li d,j => ori d,$zero,j // li d,j => ori d,$zero,j
tmpInst->setOpcode(isMips64() ? Mips::ORi64 : Mips::ORi); tmpInst.setOpcode(isMips64() ? Mips::ORi64 : Mips::ORi);
tmpInst->addOperand(MCOperand::CreateReg(RegOp.getReg())); tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
tmpInst->addOperand( tmpInst.addOperand(
MCOperand::CreateReg(isMips64() ? Mips::ZERO_64 : Mips::ZERO)); MCOperand::CreateReg(isMips64() ? Mips::ZERO_64 : Mips::ZERO));
tmpInst->addOperand(MCOperand::CreateImm(ImmValue)); tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
Instructions.push_back(tmpInst); Instructions.push_back(tmpInst);
} else if ( ImmValue < 0 && ImmValue >= -32768) { } else if ( ImmValue < 0 && ImmValue >= -32768) {
// for -32768 = j < 0. // for -32768 <= j < 0.
// li d,j => addiu d,$zero,j // li d,j => addiu d,$zero,j
tmpInst->setOpcode(Mips::ADDiu); //TODO:no ADDiu64 in td files? tmpInst.setOpcode(Mips::ADDiu); //TODO:no ADDiu64 in td files?
tmpInst->addOperand(MCOperand::CreateReg(RegOp.getReg())); tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
tmpInst->addOperand( tmpInst.addOperand(
MCOperand::CreateReg(isMips64() ? Mips::ZERO_64 : Mips::ZERO)); MCOperand::CreateReg(isMips64() ? Mips::ZERO_64 : Mips::ZERO));
tmpInst->addOperand(MCOperand::CreateImm(ImmValue)); tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
Instructions.push_back(tmpInst); Instructions.push_back(tmpInst);
} else { } else {
// for any other value of j that is representable as a 32-bit integer. // for any other value of j that is representable as a 32-bit integer.
// li d,j => lui d,hi16(j) // li d,j => lui d,hi16(j)
// ori d,d,lo16(j) // ori d,d,lo16(j)
tmpInst->setOpcode(isMips64() ? Mips::LUi64 : Mips::LUi); tmpInst.setOpcode(isMips64() ? Mips::LUi64 : Mips::LUi);
tmpInst->addOperand(MCOperand::CreateReg(RegOp.getReg())); tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
tmpInst->addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16)); tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
Instructions.push_back(tmpInst); Instructions.push_back(tmpInst);
tmpInst = new MCInst(); tmpInst.clear();
tmpInst->setOpcode(isMips64() ? Mips::ORi64 : Mips::ORi); tmpInst.setOpcode(isMips64() ? Mips::ORi64 : Mips::ORi);
tmpInst->addOperand(MCOperand::CreateReg(RegOp.getReg())); tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
tmpInst->addOperand(MCOperand::CreateReg(RegOp.getReg())); tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
tmpInst->addOperand(MCOperand::CreateImm(ImmValue & 0xffff)); tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
tmpInst->setLoc(IDLoc); tmpInst.setLoc(IDLoc);
Instructions.push_back(tmpInst); Instructions.push_back(tmpInst);
} }
} }
bool MipsAsmParser:: bool MipsAsmParser::
MatchAndEmitInstruction(SMLoc IDLoc, MatchAndEmitInstruction(SMLoc IDLoc,
SmallVectorImpl<MCParsedAsmOperand*> &Operands, SmallVectorImpl<MCParsedAsmOperand*> &Operands,
@ -379,11 +381,10 @@ MatchAndEmitInstruction(SMLoc IDLoc,
default: break; default: break;
case Match_Success: { case Match_Success: {
if (needsExpansion(Inst)) { if (needsExpansion(Inst)) {
SmallVector<MCInst*, 4> Instructions; SmallVector<MCInst, 4> Instructions;
expandInstruction(Inst, IDLoc, Instructions); expandInstruction(Inst, IDLoc, Instructions);
for(unsigned i =0; i < Instructions.size(); i++){ for(unsigned i =0; i < Instructions.size(); i++){
Inst = *(Instructions[i]); Out.EmitInstruction(Instructions[i]);
Out.EmitInstruction(Inst);
} }
} else { } else {
Inst.setLoc(IDLoc); Inst.setLoc(IDLoc);