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[SVE][CodeGen] Fix bug in DAGCombiner::reduceBuildVecToShuffle

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When trying to reduce a BUILD_VECTOR to a SHUFFLE_VECTOR it's
important that we carefully check the vector types that led to
that BUILD_VECTOR. In the test I have attached to this commit
there is a case where the results of two SVE faddv instructions
are being stored to consecutive memory locations. With my fix,
as part of merging those stores we discover that each BUILD_VECTOR
element came from an extract of a SVE vector element and
therefore bail out.

Differential Revision: https://reviews.llvm.org/D82564
This commit is contained in:
David Sherwood 2020-06-25 14:46:16 +01:00
parent 986143ca63
commit 4bd32c5a01
2 changed files with 35 additions and 0 deletions
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3
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -18287,6 +18287,9 @@ SDValue DAGCombiner::reduceBuildVecToShuffle(SDNode *N) {
return SDValue();
SDValue ExtractedFromVec = Op.getOperand(0);
if (ExtractedFromVec.getValueType().isScalableVector())
return SDValue();
const APInt &ExtractIdx = Op.getConstantOperandAPInt(1);
if (ExtractIdx.uge(ExtractedFromVec.getValueType().getVectorNumElements()))
return SDValue();

32
test/CodeGen/AArch64/sve-merging-stores.ll Normal file
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@ -0,0 +1,32 @@
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
%complex = type { { double, double } }
; Function Attrs: argmemonly nounwind readonly
declare <vscale x 2 x double> @llvm.aarch64.sve.tuple.get.nxv2f64.nxv4f64(<vscale x 4 x double>, i32 immarg) #3
; Function Attrs: argmemonly nounwind readonly
declare <vscale x 4 x double> @llvm.aarch64.sve.ld2.nxv4f64.nxv2i1(<vscale x 2 x i1>, double*) #3
; Function Attrs: nounwind readnone
declare double @llvm.aarch64.sve.faddv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #2
define void @foo1(%complex* %outval, <vscale x 2 x i1> %pred, double *%inptr) {
; CHECK-LABEL: foo1:
; CHECK: ld2d { z0.d, z1.d }, p0/z, [x1]
; CHECK-NEXT: faddv d2, p0, z0.d
; CHECK-NEXT: faddv d0, p0, z1.d
; CHECK-NEXT: mov v2.d[1], v0.d[0]
; CHECK-NEXT: str q2, [x0]
%realp = getelementptr inbounds %complex, %complex* %outval, i64 0, i32 0, i32 0
%imagp = getelementptr inbounds %complex, %complex* %outval, i64 0, i32 0, i32 1
%1 = call <vscale x 4 x double> @llvm.aarch64.sve.ld2.nxv4f64.nxv2i1(<vscale x 2 x i1> %pred, double* nonnull %inptr)
%2 = call <vscale x 2 x double> @llvm.aarch64.sve.tuple.get.nxv2f64.nxv4f64(<vscale x 4 x double> %1, i32 0)
%3 = call double @llvm.aarch64.sve.faddv.nxv2f64(<vscale x 2 x i1> %pred, <vscale x 2 x double> %2)
%4 = call <vscale x 2 x double> @llvm.aarch64.sve.tuple.get.nxv2f64.nxv4f64(<vscale x 4 x double> %1, i32 1)
%5 = call double @llvm.aarch64.sve.faddv.nxv2f64(<vscale x 2 x i1> %pred, <vscale x 2 x double> %4)
store double %3, double* %realp, align 8
store double %5, double* %imagp, align 8
ret void
}