From 4bf7d5872e09e0ce45e225073c89c6278f35eaec Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 20 Nov 2020 10:52:27 -0500 Subject: [PATCH] OpaquePtr: Bulk update tests to use typed byval Upgrade of the IR text tests should be the only thing blocking making typed byval mandatory. Partially done through regex and partially manual. --- test/Analysis/BasicAA/2008-04-15-Byval.ll | 4 +- test/Analysis/BasicAA/byval.ll | 2 +- test/Analysis/BasicAA/dereferenceable.ll | 8 +- test/Analysis/BasicAA/tail-byval.ll | 6 +- .../DivergenceAnalysis/AMDGPU/kernel-args.ll | 2 +- .../AMDGPU/kernel-args.ll | 2 +- test/Analysis/Lint/noalias-byval.ll | 6 +- test/Analysis/Lint/tail-call-byval.ll | 6 +- test/Analysis/StackSafetyAnalysis/local.ll | 12 +- .../ValueTracking/memory-dereferenceable.ll | 6 +- test/Assembler/2008-01-11-VarargAttrs.ll | 2 +- test/Assembler/byval-type-attr.ll | 4 +- test/Assembler/invalid-immarg.ll | 2 +- test/Bitcode/attributes-3.3.ll | 2 +- test/Bitcode/attributes.ll | 2 +- test/Bitcode/compatibility-3.6.ll | 2 +- test/Bitcode/compatibility-3.7.ll | 2 +- test/Bitcode/compatibility-3.8.ll | 2 +- test/Bitcode/compatibility-3.9.ll | 2 +- test/Bitcode/compatibility-4.0.ll | 2 +- test/Bitcode/compatibility-5.0.ll | 2 +- test/Bitcode/compatibility-6.0.ll | 2 +- test/Bitcode/compatibility.ll | 2 +- test/Bitcode/highLevelStructure.3.2.ll | 4 +- .../GlobalISel/call-translator-tail-call.ll | 2 +- test/CodeGen/AArch64/big-callframe.ll | 4 +- test/CodeGen/AArch64/byval-type.ll | 8 +- test/CodeGen/AArch64/func-argpassing.ll | 6 +- test/CodeGen/AArch64/func-calls.ll | 4 +- .../AArch64/statepoint-call-lowering.ll | 6 +- .../GlobalISel/irtranslator-call-sret.ll | 2 +- .../AMDGPU/GlobalISel/irtranslator-call.ll | 6 +- .../GlobalISel/irtranslator-function-args.ll | 6 +- test/CodeGen/AMDGPU/byval-frame-setup.ll | 2 +- test/CodeGen/AMDGPU/call-argument-types.ll | 12 +- test/CodeGen/AMDGPU/callee-frame-setup.ll | 4 +- .../AMDGPU/callee-special-input-vgprs.ll | 2 +- test/CodeGen/AMDGPU/enqueue-kernel.ll | 10 +- .../CodeGen/AMDGPU/frame-index-elimination.ll | 6 +- test/CodeGen/AMDGPU/function-args.ll | 6 +- .../AMDGPU/gfx-callable-argument-types.ll | 8 +- test/CodeGen/AMDGPU/load-hi16.ll | 16 +- test/CodeGen/AMDGPU/load-lo16.ll | 10 +- test/CodeGen/AMDGPU/rewrite-out-arguments.ll | 8 +- test/CodeGen/AMDGPU/sibling-call.ll | 8 +- test/CodeGen/AMDGPU/stack-realign.ll | 2 +- test/CodeGen/AMDGPU/store-hi16.ll | 2 +- test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll | 2 +- test/CodeGen/ARM/2011-06-09-TailCallByVal.ll | 4 +- test/CodeGen/ARM/2011-06-16-TailCallByVal.ll | 2 +- .../ARM/2012-10-04-AAPCS-byval-align8.ll | 6 +- .../ARM/2012-10-04-FixedFrame-vs-byval.ll | 2 +- .../ARM/2012-10-04-LDRB_POST_IMM-Crash.ll | 4 +- .../2012-10-18-PR14099-ByvalFrameAddress.ll | 6 +- .../2013-04-05-Small-ByVal-Structs-PR15293.ll | 8 +- .../CodeGen/ARM/2013-04-16-AAPCS-C5-vs-VFP.ll | 4 +- ...013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll | 8 +- ...13-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll | 10 +- .../ARM/2013-05-13-AAPCS-byval-padding.ll | 2 +- .../ARM/2013-05-13-AAPCS-byval-padding2.ll | 4 +- test/CodeGen/ARM/2013-06-03-ByVal-2Kbytes.ll | 8 +- .../2014-02-21-byval-reg-split-alignment.ll | 12 +- .../CodeGen/ARM/GlobalISel/arm-unsupported.ll | 4 +- test/CodeGen/ARM/align-sp-adjustment.ll | 4 +- test/CodeGen/ARM/alloca-align.ll | 4 +- test/CodeGen/ARM/byval-align.ll | 8 +- test/CodeGen/ARM/byval_load_align.ll | 4 +- test/CodeGen/ARM/copy-by-struct-i32.ll | 2 +- test/CodeGen/ARM/ssp-data-layout.ll | 18 +-- test/CodeGen/ARM/struct-byval-frame-index.ll | 2 +- test/CodeGen/ARM/struct_byval.ll | 24 +-- test/CodeGen/ARM/struct_byval_arm_t1_t2.ll | 152 +++++++++--------- test/CodeGen/BPF/byval.ll | 4 +- test/CodeGen/Generic/2010-11-04-BigByval.ll | 6 +- test/CodeGen/Hexagon/bit-skip-byval.ll | 2 +- test/CodeGen/Hexagon/calling-conv.ll | 6 +- test/CodeGen/Hexagon/cext-opt-negative-fi.mir | 2 +- test/CodeGen/Hexagon/inline-asm-error.ll | 2 +- test/CodeGen/Hexagon/struct_args_large.ll | 4 +- test/CodeGen/Hexagon/tail-dup-subreg-map.ll | 2 +- test/CodeGen/Hexagon/v6vect-locals1.ll | 4 +- test/CodeGen/Hexagon/vararg.ll | 2 +- test/CodeGen/Hexagon/vararg_align_check.ll | 4 +- test/CodeGen/Hexagon/vararg_double_onstack.ll | 2 +- test/CodeGen/Hexagon/vararg_named.ll | 4 +- test/CodeGen/MIR/X86/fixed-stack-di.mir | 2 +- test/CodeGen/MSP430/byval.ll | 4 +- test/CodeGen/MSP430/spill-to-stack.ll | 2 +- test/CodeGen/Mips/cconv/byval.ll | 6 +- test/CodeGen/Mips/cprestore.ll | 4 +- test/CodeGen/Mips/fastcc_byval.ll | 6 +- test/CodeGen/Mips/largeimmprinting.ll | 4 +- test/CodeGen/Mips/load-store-left-right.ll | 4 +- test/CodeGen/Mips/o32_cc_byval.ll | 24 +-- test/CodeGen/Mips/tailcall/tailcall.ll | 10 +- test/CodeGen/Mips/unalignedload.ll | 8 +- test/CodeGen/NVPTX/bug21465.ll | 2 +- test/CodeGen/NVPTX/lower-kernel-ptr-arg.ll | 4 +- test/CodeGen/NVPTX/param-align.ll | 12 +- test/CodeGen/PowerPC/MMO-flags-assertion.ll | 8 +- test/CodeGen/PowerPC/a2-fp-basic.ll | 2 +- test/CodeGen/PowerPC/anon_aggr.ll | 6 +- test/CodeGen/PowerPC/byval-agg-info.ll | 2 +- test/CodeGen/PowerPC/byval-aliased.ll | 16 +- test/CodeGen/PowerPC/dyn-alloca-aligned.ll | 2 +- test/CodeGen/PowerPC/emptystruct.ll | 8 +- test/CodeGen/PowerPC/f128-aggregates.ll | 4 +- test/CodeGen/PowerPC/fastcc_stacksize.ll | 12 +- test/CodeGen/PowerPC/glob-comp-aa-crash.ll | 4 +- test/CodeGen/PowerPC/jaggedstructs.ll | 6 +- test/CodeGen/PowerPC/ppc440-fp-basic.ll | 2 +- .../PowerPC/ppc64-align-long-double.ll | 2 +- test/CodeGen/PowerPC/ppc64-byval-align.ll | 12 +- test/CodeGen/PowerPC/ppc64-crash.ll | 2 +- test/CodeGen/PowerPC/ppc64-sibcall.ll | 4 +- test/CodeGen/PowerPC/ppc64-smallarg.ll | 6 +- test/CodeGen/PowerPC/ppc64le-smallarg.ll | 8 +- test/CodeGen/PowerPC/pr13891.ll | 2 +- test/CodeGen/PowerPC/reloc-align.ll | 4 +- test/CodeGen/PowerPC/resolvefi-basereg.ll | 12 +- test/CodeGen/PowerPC/resolvefi-disp.ll | 2 +- test/CodeGen/PowerPC/stack-realign.ll | 6 +- test/CodeGen/PowerPC/structsinmem.ll | 8 +- test/CodeGen/PowerPC/structsinregs.ll | 8 +- test/CodeGen/PowerPC/vec-abi-align.ll | 4 +- test/CodeGen/RISCV/byval.ll | 4 +- ...calling-conv-ilp32-ilp32f-ilp32d-common.ll | 4 +- .../calling-conv-lp64-lp64f-lp64d-common.ll | 4 +- test/CodeGen/RISCV/tail-calls.ll | 4 +- test/CodeGen/SPARC/2011-01-21-ByValArgs.ll | 4 +- .../CodeGen/SPARC/LeonFixAllFDIVSQRTPassUT.ll | 4 +- test/CodeGen/SPARC/LeonItinerariesUT.ll | 56 +++---- test/CodeGen/SPARC/fp128.ll | 14 +- test/CodeGen/SPARC/setjmp.ll | 2 +- test/CodeGen/SPARC/zerostructcall.ll | 12 +- test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll | 2 +- test/CodeGen/Thumb/PR17309.ll | 12 +- test/CodeGen/Thumb/emergency-spill-slot.ll | 10 +- test/CodeGen/Thumb/frame-access.ll | 12 +- test/CodeGen/WebAssembly/byval.ll | 28 ++-- test/CodeGen/WebAssembly/indirect-import.ll | 2 +- test/CodeGen/WebAssembly/tailcall.ll | 4 +- test/CodeGen/X86/2008-04-24-MemCpyBug.ll | 4 +- test/CodeGen/X86/2009-04-14-IllegalRegs.ll | 4 +- .../X86/2009-11-13-VirtRegRewriterBug.ll | 2 +- test/CodeGen/X86/2010-01-18-DbgValue.ll | 2 +- .../X86/2010-04-30-LocalAlloc-LandingPad.ll | 2 +- .../X86/2011-03-30-CreateFixedObjCrash.ll | 2 +- .../CodeGen/X86/GlobalISel/x86_64-fallback.ll | 6 +- test/CodeGen/X86/aligned-variadic.ll | 2 +- test/CodeGen/X86/arg-copy-elide.ll | 2 +- test/CodeGen/X86/avoid-sfb.ll | 2 +- test/CodeGen/X86/byval-align.ll | 4 +- test/CodeGen/X86/byval.ll | 2 +- test/CodeGen/X86/byval2.ll | 6 +- test/CodeGen/X86/byval3.ll | 6 +- test/CodeGen/X86/byval4.ll | 6 +- test/CodeGen/X86/byval5.ll | 6 +- test/CodeGen/X86/byval6.ll | 4 +- test/CodeGen/X86/byval7.ll | 4 +- test/CodeGen/X86/crash.ll | 8 +- test/CodeGen/X86/dbg-baseptr.ll | 6 +- test/CodeGen/X86/dynamic-allocas-VLAs.ll | 6 +- test/CodeGen/X86/extract-extract.ll | 2 +- test/CodeGen/X86/fast-isel-args-fail2.ll | 2 +- test/CodeGen/X86/fast-isel-call.ll | 4 +- test/CodeGen/X86/fast-isel-x86.ll | 2 +- test/CodeGen/X86/fastcc-byval.ll | 10 +- test/CodeGen/X86/fixed-stack-di-mir.ll | 2 +- test/CodeGen/X86/fp-stack-retcopy.ll | 2 +- test/CodeGen/X86/fp128-i128.ll | 2 +- .../X86/frame-lowering-debug-intrinsic.ll | 4 +- .../X86/inline-asm-sp-clobber-memcpy.ll | 4 +- test/CodeGen/X86/mcu-abi.ll | 2 +- test/CodeGen/X86/memcpy-inline-fsrm.ll | 4 +- test/CodeGen/X86/memcpy-struct-by-value.ll | 10 +- test/CodeGen/X86/misched-aa-colored.ll | 4 +- test/CodeGen/X86/movtopush.ll | 76 ++++----- test/CodeGen/X86/movtopush.mir | 4 +- test/CodeGen/X86/negate-add-zero.ll | 2 +- test/CodeGen/X86/nomovtopush.ll | 4 +- test/CodeGen/X86/pr2656.ll | 2 +- test/CodeGen/X86/pr30290.ll | 6 +- test/CodeGen/X86/pr38865.ll | 4 +- test/CodeGen/X86/sibcall-byval.ll | 12 +- test/CodeGen/X86/sibcall.ll | 10 +- test/CodeGen/X86/sjlj-baseptr.ll | 2 +- test/CodeGen/X86/ssp-data-layout.ll | 16 +- test/CodeGen/X86/stack-align-memcpy.ll | 8 +- test/CodeGen/X86/stack-align.ll | 4 +- test/CodeGen/X86/statepoint-call-lowering.ll | 6 +- .../CodeGen/X86/statepoint-stackmap-format.ll | 2 +- test/CodeGen/X86/tailcallbyval.ll | 6 +- test/CodeGen/X86/tailcallbyval64.ll | 8 +- test/CodeGen/X86/tailccbyval.ll | 6 +- test/CodeGen/X86/tailccbyval64.ll | 8 +- test/CodeGen/X86/win64-byval.ll | 12 +- test/CodeGen/X86/x86-big-ret.ll | 4 +- test/CodeGen/XCore/byVal.ll | 8 +- test/DebugInfo/Generic/2010-10-01-crash.ll | 2 +- test/DebugInfo/X86/byvalstruct.ll | 2 +- test/DebugInfo/X86/dbg-byval-parameter.ll | 2 +- test/DebugInfo/X86/double-declare.ll | 2 +- test/DebugInfo/X86/pieces-2.ll | 2 +- test/DebugInfo/X86/safestack-byval.ll | 2 +- test/DebugInfo/X86/sroasplit-1.ll | 2 +- test/DebugInfo/X86/sroasplit-4.ll | 4 +- .../stack-poisoning-byval-args.ll | 4 +- test/Instrumentation/BoundsChecking/simple.ll | 4 +- .../MemorySanitizer/PowerPC/vararg-ppc64.ll | 4 +- .../MemorySanitizer/PowerPC/vararg-ppc64le.ll | 4 +- .../MemorySanitizer/byval-alignment.ll | 4 +- .../MemorySanitizer/check_access_address.ll | 4 +- .../MemorySanitizer/msan_basic.ll | 6 +- test/Linker/func-attrs-a.ll | 6 +- test/Linker/func-attrs-b.ll | 2 +- test/Transforms/ArgumentPromotion/attrs.ll | 8 +- test/Transforms/ArgumentPromotion/byval-2.ll | 8 +- test/Transforms/ArgumentPromotion/byval.ll | 8 +- test/Transforms/ArgumentPromotion/dbg.ll | 2 +- test/Transforms/ArgumentPromotion/fp80.ll | 20 +-- test/Transforms/ArgumentPromotion/tail.ll | 8 +- test/Transforms/ArgumentPromotion/variadic.ll | 4 +- .../Attributor/ArgumentPromotion/attrs.ll | 12 +- .../Attributor/ArgumentPromotion/byval-2.ll | 6 +- .../Attributor/ArgumentPromotion/byval.ll | 24 +-- .../Attributor/ArgumentPromotion/dbg.ll | 2 +- .../Attributor/ArgumentPromotion/fp80.ll | 14 +- .../Attributor/ArgumentPromotion/tail.ll | 14 +- .../Attributor/ArgumentPromotion/variadic.ll | 4 +- .../IPConstantProp/2009-09-24-byval-ptr.ll | 28 ++-- test/Transforms/Attributor/readattrs.ll | 26 +-- test/Transforms/Attributor/value-simplify.ll | 6 +- .../DeadArgElim/2007-12-20-ParamAttrs.ll | 2 +- .../2008-01-16-VarargsParamAttrs.ll | 10 +- .../Transforms/DeadArgElim/variadic_safety.ll | 8 +- .../DeadStoreElimination/MSSA/fence-todo.ll | 2 +- .../DeadStoreElimination/MSSA/simple.ll | 10 +- .../DeadStoreElimination/MSSA/tail-byval.ll | 10 +- .../MemDepAnalysis/fence.ll | 2 +- .../MemDepAnalysis/simple.ll | 10 +- .../MemDepAnalysis/tail-byval.ll | 10 +- test/Transforms/GVN/pr17852.ll | 2 +- .../IndVarSimplify/loop_evaluate9.ll | 8 +- test/Transforms/Inline/alloca-merge-align.ll | 16 +- test/Transforms/Inline/byval-tail-call.ll | 22 +-- test/Transforms/Inline/byval.ll | 30 ++-- test/Transforms/Inline/byval_lifetime.ll | 4 +- test/Transforms/Inline/inline-byval-bonus.ll | 4 +- test/Transforms/Inline/inline-tail.ll | 20 +-- test/Transforms/Inline/inline-varargs.ll | 4 +- .../InstCombine/2008-04-22-ByValBitcast.ll | 2 +- .../InstCombine/2009-01-08-AlignAlloca.ll | 4 +- .../InstCombine/call-cast-target.ll | 2 +- test/Transforms/InstCombine/crash.ll | 2 +- .../InstCombine/memcpy-from-global.ll | 10 +- test/Transforms/MemCpyOpt/memcpy.ll | 36 ++--- test/Transforms/MemCpyOpt/smaller.ll | 6 +- test/Transforms/MemCpyOpt/sret.ll | 8 +- .../MergeFunc/mismatching-attr-crash.ll | 4 +- test/Transforms/MergeICmps/X86/pr41917.ll | 2 +- test/Transforms/NewGVN/pr17852.ll | 2 +- .../indirect_call_promotion_byval.ll | 2 +- test/Transforms/SCCP/2009-09-24-byval-ptr.ll | 8 +- .../X86/reverse_extract_elements.ll | 2 +- test/Transforms/SafeStack/X86/byval.ll | 8 +- test/Transforms/SafeStack/X86/debug-loc.ll | 2 +- test/Transforms/TailCallElim/basic.ll | 16 +- test/Verifier/amdgpu-cc.ll | 16 +- test/Verifier/byval-4.ll | 2 +- test/Verifier/inalloca1.ll | 2 +- test/Verifier/musttail-invalid.ll | 8 +- 272 files changed, 957 insertions(+), 957 deletions(-) diff --git a/test/Analysis/BasicAA/2008-04-15-Byval.ll b/test/Analysis/BasicAA/2008-04-15-Byval.ll index 9d4fd148318..e5d260c54f2 100644 --- a/test/Analysis/BasicAA/2008-04-15-Byval.ll +++ b/test/Analysis/BasicAA/2008-04-15-Byval.ll @@ -4,13 +4,13 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3 target triple = "i386-apple-darwin8" %struct.x = type { [4 x i32] } -define void @foo(%struct.x* byval align 4 %X) nounwind { +define void @foo(%struct.x* byval(%struct.x) align 4 %X) nounwind { ; CHECK: store i32 2, i32* %tmp1 entry: %tmp = getelementptr %struct.x, %struct.x* %X, i32 0, i32 0 ; <[4 x i32]*> [#uses=1] %tmp1 = getelementptr [4 x i32], [4 x i32]* %tmp, i32 0, i32 3 ; [#uses=1] store i32 2, i32* %tmp1, align 4 - %tmp2 = call i32 (...) @bar( %struct.x* byval align 4 %X ) nounwind ; [#uses=0] + %tmp2 = call i32 (...) @bar(%struct.x* byval(%struct.x) align 4 %X ) nounwind ; [#uses=0] br label %return return: ; preds = %entry ret void diff --git a/test/Analysis/BasicAA/byval.ll b/test/Analysis/BasicAA/byval.ll index 0699436a8a0..91d7ad9ee28 100644 --- a/test/Analysis/BasicAA/byval.ll +++ b/test/Analysis/BasicAA/byval.ll @@ -4,7 +4,7 @@ target triple = "i686-apple-darwin8" %struct.x = type { i32, i32, i32, i32 } @g = weak global i32 0 ; [#uses=1] -define i32 @foo(%struct.x* byval %a) nounwind { +define i32 @foo(%struct.x* byval(%struct.x) %a) nounwind { ; CHECK: ret i32 1 %tmp1 = tail call i32 (...) @bar( %struct.x* %a ) nounwind ; [#uses=0] %tmp2 = getelementptr %struct.x, %struct.x* %a, i32 0, i32 0 ; [#uses=2] diff --git a/test/Analysis/BasicAA/dereferenceable.ll b/test/Analysis/BasicAA/dereferenceable.ll index fcceb50b2c5..438114d8ac4 100644 --- a/test/Analysis/BasicAA/dereferenceable.ll +++ b/test/Analysis/BasicAA/dereferenceable.ll @@ -24,7 +24,7 @@ bb: ret i32 %tmp } -define i32 @byval_and_deref_arg_1(i32* byval %obj, i64* dereferenceable(8) %arg) { +define i32 @byval_and_deref_arg_1(i32* byval(i32) %obj, i64* dereferenceable(8) %arg) { ; CHECK: Function: byval_and_deref_arg_1: 2 pointers, 0 call sites ; CHECK-NEXT: NoAlias: i32* %obj, i64* %arg bb: @@ -34,7 +34,7 @@ bb: ret i32 %tmp } -define i32 @byval_and_deref_arg_2(i32* byval %obj, i32* dereferenceable(8) %arg) { +define i32 @byval_and_deref_arg_2(i32* byval(i32) %obj, i32* dereferenceable(8) %arg) { ; CHECK: Function: byval_and_deref_arg_2: 2 pointers, 0 call sites ; CHECK-NEXT: NoAlias: i32* %arg, i32* %obj bb: @@ -98,7 +98,7 @@ bb: ret i32 %tmp } -define i32 @byval_and_deref_arg_non_deref_1(i32* byval %obj, i64* dereferenceable(2) %arg) { +define i32 @byval_and_deref_arg_non_deref_1(i32* byval(i32) %obj, i64* dereferenceable(2) %arg) { ; CHECK: Function: byval_and_deref_arg_non_deref_1: 2 pointers, 0 call sites ; CHECK-NEXT: NoAlias: i32* %obj, i64* %arg bb: @@ -108,7 +108,7 @@ bb: ret i32 %tmp } -define i32 @byval_and_deref_arg_non_deref_2(i32* byval %obj, i32* dereferenceable(2) %arg) { +define i32 @byval_and_deref_arg_non_deref_2(i32* byval(i32) %obj, i32* dereferenceable(2) %arg) { ; CHECK: Function: byval_and_deref_arg_non_deref_2: 2 pointers, 0 call sites ; CHECK-NEXT: NoAlias: i32* %arg, i32* %obj bb: diff --git a/test/Analysis/BasicAA/tail-byval.ll b/test/Analysis/BasicAA/tail-byval.ll index 2fdedb2ae60..58c211c20b9 100644 --- a/test/Analysis/BasicAA/tail-byval.ll +++ b/test/Analysis/BasicAA/tail-byval.ll @@ -1,15 +1,15 @@ ; RUN: opt -basic-aa -aa-eval -print-all-alias-modref-info -disable-output < %s 2>&1 | FileCheck %s -declare void @takebyval(i32* byval %p) +declare void @takebyval(i32* byval(i32) %p) define i32 @tailbyval() { entry: %p = alloca i32 store i32 42, i32* %p - tail call void @takebyval(i32* byval %p) + tail call void @takebyval(i32* byval(i32) %p) %rv = load i32, i32* %p ret i32 %rv } ; FIXME: This should be Just Ref. ; CHECK-LABEL: Function: tailbyval: 1 pointers, 1 call sites -; CHECK-NEXT: Both ModRef: Ptr: i32* %p <-> tail call void @takebyval(i32* byval %p) +; CHECK-NEXT: Both ModRef: Ptr: i32* %p <-> tail call void @takebyval(i32* byval(i32) %p) diff --git a/test/Analysis/DivergenceAnalysis/AMDGPU/kernel-args.ll b/test/Analysis/DivergenceAnalysis/AMDGPU/kernel-args.ll index 85712e63d5f..bc9ed6fb879 100644 --- a/test/Analysis/DivergenceAnalysis/AMDGPU/kernel-args.ll +++ b/test/Analysis/DivergenceAnalysis/AMDGPU/kernel-args.ll @@ -32,7 +32,7 @@ define amdgpu_kernel void @test_amdgpu_kernel([4 x <16 x i8>] addrspace(4)* byre ; CHECK: DIVERGENT: ; CHECK: DIVERGENT: ; CHECK: DIVERGENT: -define void @test_c([4 x <16 x i8>] addrspace(5)* byval %arg0, float inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <3 x i32> %arg4, float %arg5, i32 %arg6) #0 { +define void @test_c([4 x <16 x i8>] addrspace(5)* byval([4 x <16 x i8>]) %arg0, float inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <3 x i32> %arg4, float %arg5, i32 %arg6) #0 { ret void } diff --git a/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/kernel-args.ll b/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/kernel-args.ll index 7276634f225..f06c9e2a315 100644 --- a/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/kernel-args.ll +++ b/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/kernel-args.ll @@ -32,7 +32,7 @@ define amdgpu_kernel void @test_amdgpu_kernel([4 x <16 x i8>] addrspace(4)* byre ; CHECK: DIVERGENT: ; CHECK: DIVERGENT: ; CHECK: DIVERGENT: -define void @test_c([4 x <16 x i8>] addrspace(4)* byval %arg0, float inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <3 x i32> %arg4, float %arg5, i32 %arg6) #0 { +define void @test_c([4 x <16 x i8>] addrspace(4)* byval([4 x <16 x i8>]) %arg0, float inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <3 x i32> %arg4, float %arg5, i32 %arg6) #0 { ret void } diff --git a/test/Analysis/Lint/noalias-byval.ll b/test/Analysis/Lint/noalias-byval.ll index 76e2d03d29f..b6cb23047c3 100644 --- a/test/Analysis/Lint/noalias-byval.ll +++ b/test/Analysis/Lint/noalias-byval.ll @@ -26,7 +26,7 @@ entry: ; CHECK: Unusual: noalias argument aliases another argument ; CHECK-NEXT: call void @f1(%s* sret %c, %s* %c) -declare void @f3(%s* noalias nocapture sret, %s* byval nocapture readnone) +declare void @f3(%s* noalias nocapture sret, %s* byval(%s) nocapture readnone) define void @f4() { entry: @@ -35,7 +35,7 @@ entry: %0 = bitcast %s* %c to i8* %1 = bitcast %s* %tmp to i8* call void @llvm.memset.p0i8.i32(i8* %0, i8 0, i32 1, i1 false) - call void @f3(%s* sret %c, %s* byval %c) + call void @f3(%s* sret %c, %s* byval(%s) %c) ret void } @@ -43,6 +43,6 @@ entry: ; noalias, since the other one is byval, effectively copying the data to the ; stack instead of passing the pointer itself. ; CHECK-NOT: Unusual: noalias argument aliases another argument -; CHECK-NOT: call void @f3(%s* sret %c, %s* %c) +; CHECK-NOT: call void @f3(%s* sret %c, %s* byval(%s) %c) attributes #0 = { argmemonly nounwind } diff --git a/test/Analysis/Lint/tail-call-byval.ll b/test/Analysis/Lint/tail-call-byval.ll index 9f274981898..14d1474b0bf 100644 --- a/test/Analysis/Lint/tail-call-byval.ll +++ b/test/Analysis/Lint/tail-call-byval.ll @@ -15,12 +15,12 @@ entry: ; CHECK: Undefined behavior: Call with "tail" keyword references alloca ; CHECK-NEXT: tail call void @f1(%s* %c) -declare void @f3(%s* byval) +declare void @f3(%s* byval(%s)) define void @f4() { entry: %c = alloca %s - tail call void @f3(%s* byval %c) + tail call void @f3(%s* byval(%s) %c) ret void } @@ -28,6 +28,6 @@ entry: ; byval, effectively copying the data to the stack instead of leaking the ; pointer itself. ; CHECK-NOT: Undefined behavior: Call with "tail" keyword references alloca -; CHECK-NOT: tail call void @f3(%s* byval %c) +; CHECK-NOT: tail call void @f3(%s* byval(%s) %c) diff --git a/test/Analysis/StackSafetyAnalysis/local.ll b/test/Analysis/StackSafetyAnalysis/local.ll index 4d3ee0d210a..1a14a0c87a5 100644 --- a/test/Analysis/StackSafetyAnalysis/local.ll +++ b/test/Analysis/StackSafetyAnalysis/local.ll @@ -445,7 +445,7 @@ entry: ret void } -define void @ByVal(i16* byval %p) { +define void @ByVal(i16* byval(i16) %p) { ; CHECK-LABEL: @ByVal dso_preemptable{{$}} ; CHECK-NEXT: args uses: ; CHECK-NEXT: allocas uses: @@ -463,16 +463,16 @@ define void @TestByVal() { ; CHECK-EMPTY: entry: %x = alloca i16, align 4 - call void @ByVal(i16* byval %x) + call void @ByVal(i16* byval(i16) %x) %y = alloca i64, align 4 %y1 = bitcast i64* %y to i16* - call void @ByVal(i16* byval %y1) - + call void @ByVal(i16* byval(i16) %y1) + ret void } -declare void @ByValArray([100000 x i64]* byval %p) +declare void @ByValArray([100000 x i64]* byval([100000 x i64]) %p) define void @TestByValArray() { ; CHECK-LABEL: @TestByValArray dso_preemptable{{$}} @@ -485,7 +485,7 @@ entry: %z1 = bitcast [100000 x i64]* %z to i8* %z2 = getelementptr i8, i8* %z1, i64 500000 %z3 = bitcast i8* %z2 to [100000 x i64]* - call void @ByValArray([100000 x i64]* byval %z3) + call void @ByValArray([100000 x i64]* byval([100000 x i64]) %z3) ret void } diff --git a/test/Analysis/ValueTracking/memory-dereferenceable.ll b/test/Analysis/ValueTracking/memory-dereferenceable.ll index 340123abba9..680143898c9 100644 --- a/test/Analysis/ValueTracking/memory-dereferenceable.ll +++ b/test/Analysis/ValueTracking/memory-dereferenceable.ll @@ -24,8 +24,8 @@ define void @test(%struct.A* sret %result, i32 addrspace(1)* dereferenceable(8) %dparam, i8 addrspace(1)* dereferenceable(32) align 1 %dparam.align1, i8 addrspace(1)* dereferenceable(32) align 16 %dparam.align16, - i8* byval %i8_byval, - %struct.A* byval %A_byval) + i8* byval(i8) %i8_byval, + %struct.A* byval(%struct.A) %A_byval) gc "statepoint-example" { ; CHECK: The following are dereferenceable: entry: @@ -177,7 +177,7 @@ entry: define i32 @f_0(i32 %val) { %ptr = inttoptr i32 %val to i32*, !dereferenceable !0 %load29 = load i32, i32* %ptr, align 8 - ret i32 %load29 + ret i32 %load29 } ; Just check that we don't crash. diff --git a/test/Assembler/2008-01-11-VarargAttrs.ll b/test/Assembler/2008-01-11-VarargAttrs.ll index 3111f2d3216..72d02efa212 100644 --- a/test/Assembler/2008-01-11-VarargAttrs.ll +++ b/test/Assembler/2008-01-11-VarargAttrs.ll @@ -6,6 +6,6 @@ declare void @foo(...) define void @bar() { - call void (...) @foo(%struct* byval null ) + call void (...) @foo(%struct* byval(%struct) null ) ret void } diff --git a/test/Assembler/byval-type-attr.ll b/test/Assembler/byval-type-attr.ll index dd195a39651..4b2e31bc3f9 100644 --- a/test/Assembler/byval-type-attr.ll +++ b/test/Assembler/byval-type-attr.ll @@ -13,8 +13,8 @@ define void @bar({i32*, i8}* byval({i32*, i8}) align 4 %0) { define void @caller({ i32*, i8 }* %ptr) personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { ; CHECK: call void @bar({ i32*, i8 }* byval({ i32*, i8 }) %ptr) ; CHECK: invoke void @bar({ i32*, i8 }* byval({ i32*, i8 }) %ptr) - call void @bar({i32*, i8}* byval %ptr) - invoke void @bar({i32*, i8}* byval %ptr) to label %success unwind label %fail + call void @bar({i32*, i8}* byval({i32*, i8}) %ptr) + invoke void @bar({i32*, i8}* byval({i32*, i8}) %ptr) to label %success unwind label %fail success: ret void diff --git a/test/Assembler/invalid-immarg.ll b/test/Assembler/invalid-immarg.ll index 65f6ba6c5f4..72dc99dc826 100644 --- a/test/Assembler/invalid-immarg.ll +++ b/test/Assembler/invalid-immarg.ll @@ -1,7 +1,7 @@ ; RUN: not llvm-as < %s -o /dev/null 2>&1 | FileCheck %s ; CHECK: Attribute 'immarg' is incompatible with other attributes -declare void @llvm.immarg.byval(i32* byval immarg) +declare void @llvm.immarg.byval(i32* byval(i32) immarg) ; CHECK: Attribute 'immarg' is incompatible with other attributes declare void @llvm.immarg.inalloca(i32* inalloca immarg) diff --git a/test/Bitcode/attributes-3.3.ll b/test/Bitcode/attributes-3.3.ll index 9149fc9e10e..eecdfd30485 100644 --- a/test/Bitcode/attributes-3.3.ll +++ b/test/Bitcode/attributes-3.3.ll @@ -47,7 +47,7 @@ define void @f7(i8* noalias %0) ret void; } -define void @f8(i8* byval %0) +define void @f8(i8* byval(i8) %0) ; CHECK: define void @f8(i8* byval(i8) %0) { ret void; diff --git a/test/Bitcode/attributes.ll b/test/Bitcode/attributes.ll index f87708e8347..1739f5109a1 100644 --- a/test/Bitcode/attributes.ll +++ b/test/Bitcode/attributes.ll @@ -44,7 +44,7 @@ define void @f7(i8* noalias %0) ret void; } -define void @f8(i8* byval %0) +define void @f8(i8* byval(i8) %0) ; CHECK: define void @f8(i8* byval(i8) %0) { ret void; diff --git a/test/Bitcode/compatibility-3.6.ll b/test/Bitcode/compatibility-3.6.ll index 4aa4d42aaae..97ba84656f0 100644 --- a/test/Bitcode/compatibility-3.6.ll +++ b/test/Bitcode/compatibility-3.6.ll @@ -403,7 +403,7 @@ declare void @f.param.signext(i8 signext) ; CHECK: declare void @f.param.signext(i8 signext) declare void @f.param.inreg(i8 inreg) ; CHECK: declare void @f.param.inreg(i8 inreg) -declare void @f.param.byval({ i8, i8 }* byval) +declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 })) ; CHECK: declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 })) declare void @f.param.inalloca(i8* inalloca) ; CHECK: declare void @f.param.inalloca(i8* inalloca) diff --git a/test/Bitcode/compatibility-3.7.ll b/test/Bitcode/compatibility-3.7.ll index c3658440a26..e3fbe4896a7 100644 --- a/test/Bitcode/compatibility-3.7.ll +++ b/test/Bitcode/compatibility-3.7.ll @@ -409,7 +409,7 @@ declare void @f.param.signext(i8 signext) ; CHECK: declare void @f.param.signext(i8 signext) declare void @f.param.inreg(i8 inreg) ; CHECK: declare void @f.param.inreg(i8 inreg) -declare void @f.param.byval({ i8, i8 }* byval) +declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 })) ; CHECK: declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 })) declare void @f.param.inalloca(i8* inalloca) ; CHECK: declare void @f.param.inalloca(i8* inalloca) diff --git a/test/Bitcode/compatibility-3.8.ll b/test/Bitcode/compatibility-3.8.ll index a4e1426059e..225d48b06cf 100644 --- a/test/Bitcode/compatibility-3.8.ll +++ b/test/Bitcode/compatibility-3.8.ll @@ -434,7 +434,7 @@ declare void @f.param.signext(i8 signext) ; CHECK: declare void @f.param.signext(i8 signext) declare void @f.param.inreg(i8 inreg) ; CHECK: declare void @f.param.inreg(i8 inreg) -declare void @f.param.byval({ i8, i8 }* byval) +declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 })) ; CHECK: declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 })) declare void @f.param.inalloca(i8* inalloca) ; CHECK: declare void @f.param.inalloca(i8* inalloca) diff --git a/test/Bitcode/compatibility-3.9.ll b/test/Bitcode/compatibility-3.9.ll index 448adfb33e8..50116144e77 100644 --- a/test/Bitcode/compatibility-3.9.ll +++ b/test/Bitcode/compatibility-3.9.ll @@ -503,7 +503,7 @@ declare void @f.param.signext(i8 signext) ; CHECK: declare void @f.param.signext(i8 signext) declare void @f.param.inreg(i8 inreg) ; CHECK: declare void @f.param.inreg(i8 inreg) -declare void @f.param.byval({ i8, i8 }* byval) +declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 })) ; CHECK: declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 })) declare void @f.param.inalloca(i8* inalloca) ; CHECK: declare void @f.param.inalloca(i8* inalloca) diff --git a/test/Bitcode/compatibility-4.0.ll b/test/Bitcode/compatibility-4.0.ll index e5e7194662f..b005fb7062b 100644 --- a/test/Bitcode/compatibility-4.0.ll +++ b/test/Bitcode/compatibility-4.0.ll @@ -503,7 +503,7 @@ declare void @f.param.signext(i8 signext) ; CHECK: declare void @f.param.signext(i8 signext) declare void @f.param.inreg(i8 inreg) ; CHECK: declare void @f.param.inreg(i8 inreg) -declare void @f.param.byval({ i8, i8 }* byval) +declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 })) ; CHECK: declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 })) declare void @f.param.inalloca(i8* inalloca) ; CHECK: declare void @f.param.inalloca(i8* inalloca) diff --git a/test/Bitcode/compatibility-5.0.ll b/test/Bitcode/compatibility-5.0.ll index 45055486c1e..0cad1b00d5f 100644 --- a/test/Bitcode/compatibility-5.0.ll +++ b/test/Bitcode/compatibility-5.0.ll @@ -507,7 +507,7 @@ declare void @f.param.signext(i8 signext) ; CHECK: declare void @f.param.signext(i8 signext) declare void @f.param.inreg(i8 inreg) ; CHECK: declare void @f.param.inreg(i8 inreg) -declare void @f.param.byval({ i8, i8 }* byval) +declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 })) ; CHECK: declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 })) declare void @f.param.inalloca(i8* inalloca) ; CHECK: declare void @f.param.inalloca(i8* inalloca) diff --git a/test/Bitcode/compatibility-6.0.ll b/test/Bitcode/compatibility-6.0.ll index 75e9e8dbc3d..69e38642814 100644 --- a/test/Bitcode/compatibility-6.0.ll +++ b/test/Bitcode/compatibility-6.0.ll @@ -514,7 +514,7 @@ declare void @f.param.signext(i8 signext) ; CHECK: declare void @f.param.signext(i8 signext) declare void @f.param.inreg(i8 inreg) ; CHECK: declare void @f.param.inreg(i8 inreg) -declare void @f.param.byval({ i8, i8 }* byval) +declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 })) ; CHECK: declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 })) declare void @f.param.inalloca(i8* inalloca) ; CHECK: declare void @f.param.inalloca(i8* inalloca) diff --git a/test/Bitcode/compatibility.ll b/test/Bitcode/compatibility.ll index 41fb68455bd..b7f9f357914 100644 --- a/test/Bitcode/compatibility.ll +++ b/test/Bitcode/compatibility.ll @@ -530,7 +530,7 @@ declare void @f.param.signext(i8 signext) ; CHECK: declare void @f.param.signext(i8 signext) declare void @f.param.inreg(i8 inreg) ; CHECK: declare void @f.param.inreg(i8 inreg) -declare void @f.param.byval({ i8, i8 }* byval) +declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 })) ; CHECK: declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 })) declare void @f.param.inalloca(i8* inalloca) ; CHECK: declare void @f.param.inalloca(i8* inalloca) diff --git a/test/Bitcode/highLevelStructure.3.2.ll b/test/Bitcode/highLevelStructure.3.2.ll index 97f9a26c414..6920ddb26f6 100644 --- a/test/Bitcode/highLevelStructure.3.2.ll +++ b/test/Bitcode/highLevelStructure.3.2.ll @@ -42,7 +42,7 @@ declare void @ParamAttr4(i8 signext) ; CHECK: declare void @ParamAttr5(i8* inreg) declare void @ParamAttr5(i8* inreg) ; CHECK: declare void @ParamAttr6(i8* byval(i8)) -declare void @ParamAttr6(i8* byval) +declare void @ParamAttr6(i8* byval(i8)) ; CHECK: declare void @ParamAttr7(i8* noalias) declare void @ParamAttr7(i8* noalias) ; CHECK: declare void @ParamAttr8(i8* nocapture) @@ -52,7 +52,7 @@ declare void @ParamAttr9(i8* nest noalias nocapture) ; CHECK: declare void @ParamAttr10{{[(i8* sret noalias nocapture) | (i8* noalias nocapture sret)]}} declare void @ParamAttr10(i8* sret noalias nocapture) ;CHECK: declare void @ParamAttr11{{[(i8* byval(i8) noalias nocapture) | (i8* noalias nocapture byval(i8))]}} -declare void @ParamAttr11(i8* byval noalias nocapture) +declare void @ParamAttr11(i8* byval(i8) noalias nocapture) ;CHECK: declare void @ParamAttr12{{[(i8* inreg noalias nocapture) | (i8* noalias nocapture inreg)]}} declare void @ParamAttr12(i8* inreg noalias nocapture) diff --git a/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll b/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll index 4c2bae90706..8f43ed01d1b 100644 --- a/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll +++ b/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll @@ -166,7 +166,7 @@ define void @test_bad_call_conv() { } ; Shouldn't tail call when the caller has byval arguments. -define void @test_byval(i8* byval %ptr) { +define void @test_byval(i8* byval(i8) %ptr) { ; COMMON-LABEL: name: test_byval ; COMMON: bb.1 (%ir-block.0): ; COMMON: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 diff --git a/test/CodeGen/AArch64/big-callframe.ll b/test/CodeGen/AArch64/big-callframe.ll index d5ee233095c..3ef57d5abc9 100644 --- a/test/CodeGen/AArch64/big-callframe.ll +++ b/test/CodeGen/AArch64/big-callframe.ll @@ -6,11 +6,11 @@ ; CHECK: stur {{.*}}, [x29, #{{.*}}] // 8-byte Folded Spill ; CHECK: ldur {{.*}}, [x29, #{{.*}}] // 8-byte Folded Reload target triple = "aarch64--" -declare void @extfunc([4096 x i64]* byval %p) +declare void @extfunc([4096 x i64]* byval([4096 x i64]) %p) define void @func([4096 x i64]* %z) { %lvar = alloca [31 x i8] %v = load volatile [31 x i8], [31 x i8]* %lvar store volatile [31 x i8] %v, [31 x i8]* %lvar - call void @extfunc([4096 x i64]* byval %z) + call void @extfunc([4096 x i64]* byval([4096 x i64]) %z) ret void } diff --git a/test/CodeGen/AArch64/byval-type.ll b/test/CodeGen/AArch64/byval-type.ll index 0c2e2dc471d..d49ac16f8e1 100644 --- a/test/CodeGen/AArch64/byval-type.ll +++ b/test/CodeGen/AArch64/byval-type.ll @@ -1,6 +1,6 @@ ; RUN: llc -mtriple=aarch64-linux-gnu %s -o - | FileCheck %s -define i8 @byval_match(i8* byval(i8) align 1, i8* byval %ptr) { +define i8 @byval_match(i8* byval(i8) align 1, i8* byval(i8) %ptr) { ; CHECK-LABEL: byval_match: ; CHECK: ldrb w0, [sp, #8] %res = load i8, i8* %ptr @@ -14,11 +14,11 @@ define void @caller_match(i8* %p0, i8* %p1) { ; CHECK: ldrb [[P0:w[0-9]+]], [x0] ; CHECK: strb [[P0]], [sp] ; CHECK: bl byval_match - call i8 @byval_match(i8* byval(i8) align 1 %p0, i8* byval %p1) + call i8 @byval_match(i8* byval(i8) align 1 %p0, i8* byval(i8) %p1) ret void } -define i8 @byval_large([3 x i64]* byval([3 x i64]) align 8, i8* byval %ptr) { +define i8 @byval_large([3 x i64]* byval([3 x i64]) align 8, i8* byval(i8) %ptr) { ; CHECK-LABEL: byval_large: ; CHECK: ldrb w0, [sp, #24] %res = load i8, i8* %ptr @@ -32,6 +32,6 @@ define void @caller_large([3 x i64]* %p0, i8* %p1) { ; CHECK: str [[P0HI]], [sp, #16] ; CHECK: str [[P0LO]], [sp] ; CHECK: bl byval_large - call i8 @byval_large([3 x i64]* byval([3 x i64]) align 8 %p0, i8* byval %p1) + call i8 @byval_large([3 x i64]* byval([3 x i64]) align 8 %p0, i8* byval(i8) %p1) ret void } diff --git a/test/CodeGen/AArch64/func-argpassing.ll b/test/CodeGen/AArch64/func-argpassing.ll index 3e6a8bb2c8c..a912f71fda8 100644 --- a/test/CodeGen/AArch64/func-argpassing.ll +++ b/test/CodeGen/AArch64/func-argpassing.ll @@ -32,7 +32,7 @@ define void @add_floats(float %val1, float %val2) { ; byval pointers should be allocated to the stack and copied as if ; with memcpy. -define void @take_struct(%myStruct* byval %structval) { +define void @take_struct(%myStruct* byval(%myStruct) %structval) { ; CHECK-LABEL: take_struct: %addr0 = getelementptr %myStruct, %myStruct* %structval, i64 0, i32 2 %addr1 = getelementptr %myStruct, %myStruct* %structval, i64 0, i32 0 @@ -52,7 +52,7 @@ define void @take_struct(%myStruct* byval %structval) { } ; %structval should be at sp + 16 -define void @check_byval_align(i32* byval %ignore, %myStruct* byval align 16 %structval) { +define void @check_byval_align(i32* byval(i32) %ignore, %myStruct* byval(%myStruct) align 16 %structval) { ; CHECK-LABEL: check_byval_align: %addr0 = getelementptr %myStruct, %myStruct* %structval, i64 0, i32 2 @@ -126,7 +126,7 @@ define void @return_large_struct(%myStruct* sret %retval) { ; available, but it needs two). Also make sure that %stacked doesn't ; sneak into x7 behind. define i32 @struct_on_stack(i8 %var0, i16 %var1, i32 %var2, i64 %var3, i128 %var45, - i32* %var6, %myStruct* byval %struct, i32* byval %stacked, + i32* %var6, %myStruct* byval(%myStruct) %struct, i32* byval(i32) %stacked, double %notstacked) { ; CHECK-LABEL: struct_on_stack: %addr = getelementptr %myStruct, %myStruct* %struct, i64 0, i32 0 diff --git a/test/CodeGen/AArch64/func-calls.ll b/test/CodeGen/AArch64/func-calls.ll index fe48fd30826..efc8915384d 100644 --- a/test/CodeGen/AArch64/func-calls.ll +++ b/test/CodeGen/AArch64/func-calls.ll @@ -74,7 +74,7 @@ define void @simple_rets() { declare i32 @struct_on_stack(i8 %var0, i16 %var1, i32 %var2, i64 %var3, i128 %var45, - i32* %var6, %myStruct* byval %struct, i32 %stacked, + i32* %var6, %myStruct* byval(%myStruct) %struct, i32 %stacked, double %notstacked) declare void @stacked_fpu(float %var0, double %var1, float %var2, float %var3, float %var4, float %var5, float %var6, float %var7, @@ -83,7 +83,7 @@ declare void @stacked_fpu(float %var0, double %var1, float %var2, float %var3, define void @check_stack_args() { ; CHECK-LABEL: check_stack_args: call i32 @struct_on_stack(i8 0, i16 12, i32 42, i64 99, i128 1, - i32* @var32, %myStruct* byval @varstruct, + i32* @var32, %myStruct* byval(%myStruct) @varstruct, i32 999, double 1.0) ; Want to check that the final double is passed in registers and ; that varstruct is passed on the stack. Rather dependent on how a diff --git a/test/CodeGen/AArch64/statepoint-call-lowering.ll b/test/CodeGen/AArch64/statepoint-call-lowering.ll index 9819f64a954..da35684a09a 100644 --- a/test/CodeGen/AArch64/statepoint-call-lowering.ll +++ b/test/CodeGen/AArch64/statepoint-call-lowering.ll @@ -171,9 +171,9 @@ right: %struct2 = type { i64, i64, i64 } -declare void @consume_attributes(i32, i8* nest, i32, %struct2* byval) +declare void @consume_attributes(i32, i8* nest, i32, %struct2* byval(%struct2)) -define void @test_attributes(%struct2* byval %s) gc "statepoint-example" { +define void @test_attributes(%struct2* byval(%struct2) %s) gc "statepoint-example" { ; CHECK-LABEL: test_attributes: ; CHECK: // %bb.0: // %entry ; CHECK-NEXT: sub sp, sp, #32 // =32 @@ -192,7 +192,7 @@ define void @test_attributes(%struct2* byval %s) gc "statepoint-example" { entry: ; Check that arguments with attributes are lowered correctly. ; We call a function that has a nest argument and a byval argument. - %statepoint_token = call token (i64, i32, void (i32, i8*, i32, %struct2*)*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidi32p0i8i32p0s_struct2sf(i64 0, i32 0, void (i32, i8*, i32, %struct2*)* @consume_attributes, i32 4, i32 0, i32 42, i8* nest null, i32 17, %struct2* byval %s, i32 0, i32 0) + %statepoint_token = call token (i64, i32, void (i32, i8*, i32, %struct2*)*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidi32p0i8i32p0s_struct2sf(i64 0, i32 0, void (i32, i8*, i32, %struct2*)* @consume_attributes, i32 4, i32 0, i32 42, i8* nest null, i32 17, %struct2* byval(%struct2) %s, i32 0, i32 0) ret void } diff --git a/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll b/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll index f244a840476..d215dc05c95 100644 --- a/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll +++ b/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; RUN: llc -global-isel -amdgpu-fixed-function-abi -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s -declare hidden void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32({ i8, i32 } addrspace(5)* sret, { i8, i32 } addrspace(5)* byval) #0 +declare hidden void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32({ i8, i32 } addrspace(5)* sret({ i8, i32 }), { i8, i32 } addrspace(5)* byval({ i8, i32 })) #0 define amdgpu_kernel void @test_call_external_void_func_sret_struct_i8_i32_byval_struct_i8_i32(i32) #0 { ; GCN-LABEL: name: test_call_external_void_func_sret_struct_i8_i32_byval_struct_i8_i32 diff --git a/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll b/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll index 3cd6235cf5d..76048be98a8 100644 --- a/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll +++ b/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll @@ -67,8 +67,8 @@ declare hidden void @external_void_func_v32i32_i8_i8_i16(<32 x i32>, i8, i8, i16 ; Structs declare hidden void @external_void_func_struct_i8_i32({ i8, i32 }) #0 -declare hidden void @external_void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval) #0 -declare hidden void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32({ i8, i32 } addrspace(5)* sret, { i8, i32 } addrspace(5)* byval) #0 +declare hidden void @external_void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval({ i8, i32 })) #0 +declare hidden void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32({ i8, i32 } addrspace(5)* sret({ i8, i32 }), { i8, i32 } addrspace(5)* byval({ i8, i32 })) #0 declare hidden void @external_void_func_v2i8(<2 x i8>) #0 declare hidden void @external_void_func_v3i8(<3 x i8>) #0 @@ -76,7 +76,7 @@ declare hidden void @external_void_func_v4i8(<4 x i8>) #0 declare hidden void @external_void_func_v8i8(<8 x i8>) #0 declare hidden void @external_void_func_v16i8(<16 x i8>) #0 -declare hidden void @byval_align16_f64_arg(<32 x i32>, double addrspace(5)* byval align 16) #0 +declare hidden void @byval_align16_f64_arg(<32 x i32>, double addrspace(5)* byval(double) align 16) #0 declare hidden void @stack_passed_f64_arg(<32 x i32>, double) #0 declare hidden void @external_void_func_12xv3i32(<3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>) #0 diff --git a/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll b/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll index 96d0c9d1d4a..3bf46196fd5 100644 --- a/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll +++ b/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll @@ -1683,7 +1683,7 @@ define void @void_func_struct_i8_i32({ i8, i32 } %arg0) #0 { ret void } -define void @void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval %arg0) #0 { +define void @void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval({ i8, i32 }) %arg0) #0 { ; CHECK-LABEL: name: void_func_byval_struct_i8_i32 ; CHECK: bb.1 (%ir-block.0): ; CHECK: liveins: $sgpr30_sgpr31 @@ -1706,7 +1706,7 @@ define void @void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval %arg0 ret void } -define void @void_func_byval_struct_i8_i32_x2({ i8, i32 } addrspace(5)* byval %arg0, { i8, i32 } addrspace(5)* byval %arg1, i32 %arg2) #0 { +define void @void_func_byval_struct_i8_i32_x2({ i8, i32 } addrspace(5)* byval({ i8, i32 }) %arg0, { i8, i32 } addrspace(5)* byval({ i8, i32 }) %arg1, i32 %arg2) #0 { ; CHECK-LABEL: name: void_func_byval_struct_i8_i32_x2 ; CHECK: bb.1 (%ir-block.0): ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31 @@ -1743,7 +1743,7 @@ define void @void_func_byval_struct_i8_i32_x2({ i8, i32 } addrspace(5)* byval %a ret void } -define void @void_func_byval_i32_byval_i64(i32 addrspace(5)* byval %arg0, i64 addrspace(5)* byval %arg1) #0 { +define void @void_func_byval_i32_byval_i64(i32 addrspace(5)* byval(i32) %arg0, i64 addrspace(5)* byval(i64) %arg1) #0 { ; CHECK-LABEL: name: void_func_byval_i32_byval_i64 ; CHECK: bb.1 (%ir-block.0): ; CHECK: liveins: $sgpr30_sgpr31 diff --git a/test/CodeGen/AMDGPU/byval-frame-setup.ll b/test/CodeGen/AMDGPU/byval-frame-setup.ll index 91eb7d0add4..cf6fb6f1ade 100644 --- a/test/CodeGen/AMDGPU/byval-frame-setup.ll +++ b/test/CodeGen/AMDGPU/byval-frame-setup.ll @@ -23,7 +23,7 @@ ; GCN: [[BB1]] ; GCN: s_or_b64 exec, exec -define hidden void @void_func_byval_struct_use_outside_entry_block(%struct.ByValStruct addrspace(5)* byval noalias nocapture align 4 %arg0, %struct.ByValStruct addrspace(5)* byval noalias nocapture align 4 %arg1, i1 %cond) #1 { +define hidden void @void_func_byval_struct_use_outside_entry_block(%struct.ByValStruct addrspace(5)* byval(%struct.ByValStruct) noalias nocapture align 4 %arg0, %struct.ByValStruct addrspace(5)* byval(%struct.ByValStruct) noalias nocapture align 4 %arg1, i1 %cond) #1 { entry: br i1 %cond, label %bb0, label %bb1 diff --git a/test/CodeGen/AMDGPU/call-argument-types.ll b/test/CodeGen/AMDGPU/call-argument-types.ll index 20d398c772a..51f001199e1 100644 --- a/test/CodeGen/AMDGPU/call-argument-types.ll +++ b/test/CodeGen/AMDGPU/call-argument-types.ll @@ -52,8 +52,8 @@ declare hidden i32 @external_i32_func_i32(i32) #0 ; Structs declare hidden void @external_void_func_struct_i8_i32({ i8, i32 }) #0 -declare hidden void @external_void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval) #0 -declare hidden void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32({ i8, i32 } addrspace(5)* sret, { i8, i32 } addrspace(5)* byval) #0 +declare hidden void @external_void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval({ i8, i32 })) #0 +declare hidden void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32({ i8, i32 } addrspace(5)* sret, { i8, i32 } addrspace(5)* byval({ i8, i32 })) #0 declare hidden void @external_void_func_v16i8(<16 x i8>) #0 @@ -681,7 +681,7 @@ define amdgpu_kernel void @test_call_external_void_func_byval_struct_i8_i32() #0 %gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %val, i32 0, i32 1 store i8 3, i8 addrspace(5)* %gep0 store i32 8, i32 addrspace(5)* %gep1 - call void @external_void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* %val) + call void @external_void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval({ i8, i32 }) %val) ret void } @@ -713,7 +713,7 @@ define amdgpu_kernel void @test_call_external_void_func_sret_struct_i8_i32_byval %in.gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %in.val, i32 0, i32 1 store i8 3, i8 addrspace(5)* %in.gep0 store i32 8, i32 addrspace(5)* %in.gep1 - call void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32({ i8, i32 } addrspace(5)* %out.val, { i8, i32 } addrspace(5)* %in.val) + call void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32({ i8, i32 } addrspace(5)* %out.val, { i8, i32 } addrspace(5)* byval({ i8, i32 }) %in.val) %out.gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %out.val, i32 0, i32 0 %out.gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %out.val, i32 0, i32 1 %out.val0 = load i8, i8 addrspace(5)* %out.gep0 @@ -756,7 +756,7 @@ entry: define void @tail_call_byval_align16(<32 x i32> %val, double %tmp) #0 { entry: %alloca = alloca double, align 8, addrspace(5) - tail call void @byval_align16_f64_arg(<32 x i32> %val, double addrspace(5)* byval align 16 %alloca) + tail call void @byval_align16_f64_arg(<32 x i32> %val, double addrspace(5)* byval(double) align 16 %alloca) ret void } @@ -902,7 +902,7 @@ entry: ret void } -declare hidden void @byval_align16_f64_arg(<32 x i32>, double addrspace(5)* byval align 16) #0 +declare hidden void @byval_align16_f64_arg(<32 x i32>, double addrspace(5)* byval(double) align 16) #0 declare hidden void @stack_passed_f64_arg(<32 x i32>, double) #0 declare hidden void @external_void_func_12xv3i32(<3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>) #0 diff --git a/test/CodeGen/AMDGPU/callee-frame-setup.ll b/test/CodeGen/AMDGPU/callee-frame-setup.ll index 20d50200e3a..ed6140228fc 100644 --- a/test/CodeGen/AMDGPU/callee-frame-setup.ll +++ b/test/CodeGen/AMDGPU/callee-frame-setup.ll @@ -479,7 +479,7 @@ define void @no_unused_non_csr_sgpr_for_fp_no_scratch_vgpr() #1 { ; GCN-NEXT: s_mov_b64 exec, [[COPY_EXEC1]] ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_setpc_b64 -define void @scratch_reg_needed_mubuf_offset([4096 x i8] addrspace(5)* byval align 4 %arg) #1 { +define void @scratch_reg_needed_mubuf_offset([4096 x i8] addrspace(5)* byval([4096 x i8]) align 4 %arg) #1 { %alloca = alloca i32, addrspace(5) store volatile i32 0, i32 addrspace(5)* %alloca @@ -608,7 +608,7 @@ define void @callee_need_to_spill_fp_to_memory_full_reserved_vgpr() #3 { ; FLATSCR: s_add_u32 [[SOFF:s[0-9]+]], s33, 0x1004 ; FLATSCR: v_mov_b32_e32 v0, 0 ; FLATSCR: scratch_store_dword off, v0, [[SOFF]] -define void @spill_fp_to_memory_scratch_reg_needed_mubuf_offset([4096 x i8] addrspace(5)* byval align 4 %arg) #3 { +define void @spill_fp_to_memory_scratch_reg_needed_mubuf_offset([4096 x i8] addrspace(5)* byval([4096 x i8]) align 4 %arg) #3 { %alloca = alloca i32, addrspace(5) store volatile i32 0, i32 addrspace(5)* %alloca diff --git a/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll b/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll index 18fe484f4e3..44cc53e2ce4 100644 --- a/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll +++ b/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll @@ -560,7 +560,7 @@ define void @too_many_args_use_workitem_id_x_byval( i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18, i32 %arg19, i32 %arg20, i32 %arg21, i32 %arg22, i32 %arg23, - i32 %arg24, i32 %arg25, i32 %arg26, i32 %arg27, i32 %arg28, i32 %arg29, i32 %arg30, i32 %arg31, i32 addrspace(5)* byval %arg32) #1 { + i32 %arg24, i32 %arg25, i32 %arg26, i32 %arg27, i32 %arg28, i32 %arg29, i32 %arg30, i32 %arg31, i32 addrspace(5)* byval(i32) %arg32) #1 { %val = call i32 @llvm.amdgcn.workitem.id.x() store volatile i32 %val, i32 addrspace(1)* undef diff --git a/test/CodeGen/AMDGPU/enqueue-kernel.ll b/test/CodeGen/AMDGPU/enqueue-kernel.ll index 7358d9b0dc8..3a5d7bb9be0 100644 --- a/test/CodeGen/AMDGPU/enqueue-kernel.ll +++ b/test/CodeGen/AMDGPU/enqueue-kernel.ll @@ -53,13 +53,13 @@ entry: store i8 %b, i8 addrspace(5)* %block.captured1, align 8 %tmp1 = bitcast <{ i32, i32, i8 addrspace(1)*, i8 }> addrspace(5)* %block to void () addrspace(5)* %tmp4 = addrspacecast void () addrspace(5)* %tmp1 to i8* - %tmp5 = call i32 @__enqueue_kernel_basic(%opencl.queue_t addrspace(1)* undef, i32 0, %struct.ndrange_t addrspace(5)* byval nonnull %tmp, + %tmp5 = call i32 @__enqueue_kernel_basic(%opencl.queue_t addrspace(1)* undef, i32 0, %struct.ndrange_t addrspace(5)* byval(%struct.ndrange_t) nonnull %tmp, i8* bitcast (void (<{ i32, i32, i8 addrspace(1)*, i8 }>)* @__test_block_invoke_kernel to i8*), i8* nonnull %tmp4) #2 - %tmp10 = call i32 @__enqueue_kernel_basic(%opencl.queue_t addrspace(1)* undef, i32 0, %struct.ndrange_t addrspace(5)* byval nonnull %tmp, + %tmp10 = call i32 @__enqueue_kernel_basic(%opencl.queue_t addrspace(1)* undef, i32 0, %struct.ndrange_t addrspace(5)* byval(%struct.ndrange_t) nonnull %tmp, i8* bitcast (void (<{ i32, i32, i8 addrspace(1)*, i8 }>)* @__test_block_invoke_kernel to i8*), i8* nonnull %tmp4) #2 - %tmp11 = call i32 @__enqueue_kernel_basic(%opencl.queue_t addrspace(1)* undef, i32 0, %struct.ndrange_t addrspace(5)* byval nonnull %tmp, + %tmp11 = call i32 @__enqueue_kernel_basic(%opencl.queue_t addrspace(1)* undef, i32 0, %struct.ndrange_t addrspace(5)* byval(%struct.ndrange_t) nonnull %tmp, i8* bitcast (void (<{ i32, i32, i8 addrspace(1)*, i8 }>)* @0 to i8*), i8* nonnull %tmp4) #2 - %tmp12 = call i32 @__enqueue_kernel_basic(%opencl.queue_t addrspace(1)* undef, i32 0, %struct.ndrange_t addrspace(5)* byval nonnull %tmp, + %tmp12 = call i32 @__enqueue_kernel_basic(%opencl.queue_t addrspace(1)* undef, i32 0, %struct.ndrange_t addrspace(5)* byval(%struct.ndrange_t) nonnull %tmp, i8* bitcast (void (<{ i32, i32, i8 addrspace(1)*, i8 }>)* @1 to i8*), i8* nonnull %tmp4) #2 %block.size4 = getelementptr inbounds <{ i32, i32, i8 addrspace(1)*, i64 addrspace(1)*, i64, i8 }>, <{ i32, i32, i8 addrspace(1)*, i64 addrspace(1)*, i64, i8 }> addrspace(5)* %block2, i32 0, i32 0 store i32 41, i32 addrspace(5)* %block.size4, align 8 @@ -75,7 +75,7 @@ entry: store i64 %d, i64 addrspace(5)* %block.captured10, align 8 %tmp6 = bitcast <{ i32, i32, i8 addrspace(1)*, i64 addrspace(1)*, i64, i8 }> addrspace(5)* %block2 to void () addrspace(5)* %tmp8 = addrspacecast void () addrspace(5)* %tmp6 to i8* - %tmp9 = call i32 @__enqueue_kernel_basic(%opencl.queue_t addrspace(1)* undef, i32 0, %struct.ndrange_t addrspace(5)* byval nonnull %tmp3, + %tmp9 = call i32 @__enqueue_kernel_basic(%opencl.queue_t addrspace(1)* undef, i32 0, %struct.ndrange_t addrspace(5)* byval(%struct.ndrange_t) nonnull %tmp3, i8* bitcast (void (<{ i32, i32, i8 addrspace(1)*, i64 addrspace(1)*, i64, i8 }>)* @__test_block_invoke_2_kernel to i8*), i8* nonnull %tmp8) #2 ret void } diff --git a/test/CodeGen/AMDGPU/frame-index-elimination.ll b/test/CodeGen/AMDGPU/frame-index-elimination.ll index 4ef1c41b432..2c18e724278 100644 --- a/test/CodeGen/AMDGPU/frame-index-elimination.ll +++ b/test/CodeGen/AMDGPU/frame-index-elimination.ll @@ -128,7 +128,7 @@ define void @func_load_private_arg_i32_ptr(i32 addrspace(5)* %ptr) #0 { ; GCN-NOT: v_mov ; GCN: ds_write_b32 v0, v0 -define void @void_func_byval_struct_i8_i32_ptr({ i8, i32 } addrspace(5)* byval %arg0) #0 { +define void @void_func_byval_struct_i8_i32_ptr({ i8, i32 } addrspace(5)* byval({ i8, i32 }) %arg0) #0 { %gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %arg0, i32 0, i32 0 %gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %arg0, i32 0, i32 1 %load1 = load i32, i32 addrspace(5)* %gep1 @@ -142,7 +142,7 @@ define void @void_func_byval_struct_i8_i32_ptr({ i8, i32 } addrspace(5)* byval % ; MUBUF-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:4 ; GFX9-FLATSCR-NEXT: scratch_load_ubyte v0, off, s32 ; GFX9-FLATSCR-NEXT: scratch_load_dword v1, off, s32 offset:4 -define void @void_func_byval_struct_i8_i32_ptr_value({ i8, i32 } addrspace(5)* byval %arg0) #0 { +define void @void_func_byval_struct_i8_i32_ptr_value({ i8, i32 } addrspace(5)* byval({ i8, i32 }) %arg0) #0 { %gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %arg0, i32 0, i32 0 %gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %arg0, i32 0, i32 1 %load0 = load i8, i8 addrspace(5)* %gep0 @@ -169,7 +169,7 @@ define void @void_func_byval_struct_i8_i32_ptr_value({ i8, i32 } addrspace(5)* b ; GFX9-FLATSCR: scratch_load_dword v{{[0-9]+}}, [[SP]], off offset:4{{$}} ; GCN: ds_write_b32 v{{[0-9]+}}, [[GEP]] -define void @void_func_byval_struct_i8_i32_ptr_nonentry_block({ i8, i32 } addrspace(5)* byval %arg0, i32 %arg2) #0 { +define void @void_func_byval_struct_i8_i32_ptr_nonentry_block({ i8, i32 } addrspace(5)* byval({ i8, i32 }) %arg0, i32 %arg2) #0 { %cmp = icmp eq i32 %arg2, 0 br i1 %cmp, label %bb, label %ret diff --git a/test/CodeGen/AMDGPU/function-args.ll b/test/CodeGen/AMDGPU/function-args.ll index 1f2657fe94d..8923c8a701b 100644 --- a/test/CodeGen/AMDGPU/function-args.ll +++ b/test/CodeGen/AMDGPU/function-args.ll @@ -530,7 +530,7 @@ define void @void_func_struct_i8_i32({ i8, i32 } %arg0) #0 { ; GCN-DAG: buffer_load_dword v[[ELT1:[0-9]+]], off, s[0:3], s32 offset:4{{$}} ; GCN-DAG: buffer_store_dword v[[ELT1]] ; GCN-DAG: buffer_store_byte v[[ELT0]] -define void @void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval %arg0) #0 { +define void @void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval({ i8, i32 }) %arg0) #0 { %arg0.load = load { i8, i32 }, { i8, i32 } addrspace(5)* %arg0 store { i8, i32 } %arg0.load, { i8, i32 } addrspace(1)* undef ret void @@ -544,7 +544,7 @@ define void @void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval %arg0 ; GCN: ds_write_b32 v0, v0 ; GCN: s_setpc_b64 -define void @void_func_byval_struct_i8_i32_x2({ i8, i32 } addrspace(5)* byval %arg0, { i8, i32 } addrspace(5)* byval %arg1, i32 %arg2) #0 { +define void @void_func_byval_struct_i8_i32_x2({ i8, i32 } addrspace(5)* byval({ i8, i32 }) %arg0, { i8, i32 } addrspace(5)* byval({ i8, i32 }) %arg1, i32 %arg2) #0 { %arg0.load = load volatile { i8, i32 }, { i8, i32 } addrspace(5)* %arg0 %arg1.load = load volatile { i8, i32 }, { i8, i32 } addrspace(5)* %arg1 store volatile { i8, i32 } %arg0.load, { i8, i32 } addrspace(1)* undef @@ -559,7 +559,7 @@ define void @void_func_byval_struct_i8_i32_x2({ i8, i32 } addrspace(5)* byval %a ; GCN-DAG: buffer_load_dword v[[ARG1_LOAD1:[0-9]+]], off, s[0:3], s32 offset:12{{$}} ; GCN-DAG: buffer_store_dword v[[ARG0_LOAD]], off ; GCN-DAG: buffer_store_dwordx2 v{{\[}}[[ARG1_LOAD0]]:[[ARG1_LOAD1]]{{\]}}, off -define void @void_func_byval_i32_byval_i64(i32 addrspace(5)* byval %arg0, i64 addrspace(5)* byval %arg1) #0 { +define void @void_func_byval_i32_byval_i64(i32 addrspace(5)* byval(i32) %arg0, i64 addrspace(5)* byval(i64) %arg1) #0 { %arg0.load = load i32, i32 addrspace(5)* %arg0 %arg1.load = load i64, i64 addrspace(5)* %arg1 store i32 %arg0.load, i32 addrspace(1)* undef diff --git a/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll b/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll index 122b10d1e4e..ec5227d03d2 100644 --- a/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll +++ b/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll @@ -86,8 +86,8 @@ declare hidden amdgpu_gfx i32 @external_i32_func_i32(i32) #0 ; Structs declare hidden amdgpu_gfx void @external_void_func_struct_i8_i32({ i8, i32 }) #0 -declare hidden amdgpu_gfx void @external_void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval) #0 -declare hidden amdgpu_gfx void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32({ i8, i32 } addrspace(5)* sret, { i8, i32 } addrspace(5)* byval) #0 +declare hidden amdgpu_gfx void @external_void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval({ i8, i32 })) #0 +declare hidden amdgpu_gfx void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32({ i8, i32 } addrspace(5)* sret({ i8, i32 }), { i8, i32 } addrspace(5)* byval({ i8, i32 })) #0 declare hidden amdgpu_gfx void @external_void_func_v16i8(<16 x i8>) #0 @@ -3392,7 +3392,7 @@ define void @tail_call_byval_align16(<32 x i32> %val, double %tmp) #0 { ; GFX10-NEXT: s_setpc_b64 s[4:5] entry: %alloca = alloca double, align 8, addrspace(5) - tail call amdgpu_gfx void @byval_align16_f64_arg(<32 x i32> %val, double addrspace(5)* byval align 16 %alloca) + tail call amdgpu_gfx void @byval_align16_f64_arg(<32 x i32> %val, double addrspace(5)* byval(double) align 16 %alloca) ret void } @@ -6542,7 +6542,7 @@ entry: ret void } -declare hidden amdgpu_gfx void @byval_align16_f64_arg(<32 x i32>, double addrspace(5)* byval align 16) #0 +declare hidden amdgpu_gfx void @byval_align16_f64_arg(<32 x i32>, double addrspace(5)* byval(double) align 16) #0 declare hidden amdgpu_gfx void @stack_passed_f64_arg(<32 x i32>, double) #0 declare hidden amdgpu_gfx void @external_void_func_12xv3i32(<3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>) #0 diff --git a/test/CodeGen/AMDGPU/load-hi16.ll b/test/CodeGen/AMDGPU/load-hi16.ll index cda335d73f0..ec757689f6c 100644 --- a/test/CodeGen/AMDGPU/load-hi16.ll +++ b/test/CodeGen/AMDGPU/load-hi16.ll @@ -502,7 +502,7 @@ entry: ; GFX900-NEXT: s_setpc_b64 ; NO-D16-HI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s32 offset:4094{{$}} -define void @load_private_hi_v2i16_reglo_vreg(i16 addrspace(5)* byval %in, i16 %reg) #0 { +define void @load_private_hi_v2i16_reglo_vreg(i16 addrspace(5)* byval(i16) %in, i16 %reg) #0 { entry: %gep = getelementptr inbounds i16, i16 addrspace(5)* %in, i64 2047 %load = load i16, i16 addrspace(5)* %gep @@ -522,7 +522,7 @@ entry: ; GFX900-NEXT: s_setpc_b64 ; NO-D16-HI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s32 offset:4094{{$}} -define void @load_private_hi_v2f16_reglo_vreg(half addrspace(5)* byval %in, half %reg) #0 { +define void @load_private_hi_v2f16_reglo_vreg(half addrspace(5)* byval(half) %in, half %reg) #0 { entry: %gep = getelementptr inbounds half, half addrspace(5)* %in, i64 2047 %load = load half, half addrspace(5)* %gep @@ -543,7 +543,7 @@ entry: ; GFX900-NEXT: s_setpc_b64 ; NO-D16-HI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], 0 offset:4094{{$}} -define void @load_private_hi_v2i16_reglo_vreg_nooff(i16 addrspace(5)* byval %in, i16 %reg) #0 { +define void @load_private_hi_v2i16_reglo_vreg_nooff(i16 addrspace(5)* byval(i16) %in, i16 %reg) #0 { entry: %load = load volatile i16, i16 addrspace(5)* inttoptr (i32 4094 to i16 addrspace(5)*) %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0 @@ -582,7 +582,7 @@ entry: ; GFX900-NEXT: s_setpc_b64 ; NO-D16-HI: buffer_load_ubyte v{{[0-9]+}}, off, s[0:3], s32 offset:4095{{$}} -define void @load_private_hi_v2i16_reglo_vreg_zexti8(i8 addrspace(5)* byval %in, i16 %reg) #0 { +define void @load_private_hi_v2i16_reglo_vreg_zexti8(i8 addrspace(5)* byval(i8) %in, i16 %reg) #0 { entry: %gep = getelementptr inbounds i8, i8 addrspace(5)* %in, i64 4095 %load = load i8, i8 addrspace(5)* %gep @@ -603,7 +603,7 @@ entry: ; GFX900-NEXT: s_setpc_b64 ; NO-D16-HI: buffer_load_ubyte v{{[0-9]+}}, off, s[0:3], s32 offset:4095{{$}} -define void @load_private_hi_v2f16_reglo_vreg_zexti8(i8 addrspace(5)* byval %in, half %reg) #0 { +define void @load_private_hi_v2f16_reglo_vreg_zexti8(i8 addrspace(5)* byval(i8) %in, half %reg) #0 { entry: %gep = getelementptr inbounds i8, i8 addrspace(5)* %in, i64 4095 %load = load i8, i8 addrspace(5)* %gep @@ -625,7 +625,7 @@ entry: ; GFX900-NEXT: s_setpc_b64 ; NO-D16-HI: buffer_load_sbyte v{{[0-9]+}}, off, s[0:3], s32 offset:4095{{$}} -define void @load_private_hi_v2f16_reglo_vreg_sexti8(i8 addrspace(5)* byval %in, half %reg) #0 { +define void @load_private_hi_v2f16_reglo_vreg_sexti8(i8 addrspace(5)* byval(i8) %in, half %reg) #0 { entry: %gep = getelementptr inbounds i8, i8 addrspace(5)* %in, i64 4095 %load = load i8, i8 addrspace(5)* %gep @@ -647,7 +647,7 @@ entry: ; GFX900-NEXT: s_setpc_b64 ; NO-D16-HI: buffer_load_sbyte v{{[0-9]+}}, off, s[0:3], s32 offset:4095{{$}} -define void @load_private_hi_v2i16_reglo_vreg_sexti8(i8 addrspace(5)* byval %in, i16 %reg) #0 { +define void @load_private_hi_v2i16_reglo_vreg_sexti8(i8 addrspace(5)* byval(i8) %in, i16 %reg) #0 { entry: %gep = getelementptr inbounds i8, i8 addrspace(5)* %in, i64 4095 %load = load i8, i8 addrspace(5)* %gep @@ -1004,7 +1004,7 @@ entry: ; GFX900-FLATSCR-NEXT: scratch_load_short_d16_hi v0, off, s32 offset:2 ; GFX900-NEXT: s_waitcnt ; GFX900-NEXT: s_setpc_b64 -define <2 x i16> @load_private_v2i16_split(i16 addrspace(5)* byval %in) #0 { +define <2 x i16> @load_private_v2i16_split(i16 addrspace(5)* byval(i16) %in) #0 { entry: %gep = getelementptr inbounds i16, i16 addrspace(5)* %in, i32 1 %load0 = load volatile i16, i16 addrspace(5)* %in diff --git a/test/CodeGen/AMDGPU/load-lo16.ll b/test/CodeGen/AMDGPU/load-lo16.ll index 44fe6cdf915..e0866ca5195 100644 --- a/test/CodeGen/AMDGPU/load-lo16.ll +++ b/test/CodeGen/AMDGPU/load-lo16.ll @@ -1177,7 +1177,7 @@ entry: ret void } -define void @load_private_lo_v2i16_reglo_vreg(i16 addrspace(5)* byval %in, i32 %reg) #0 { +define void @load_private_lo_v2i16_reglo_vreg(i16 addrspace(5)* byval(i16) %in, i32 %reg) #0 { ; GFX900-MUBUF-LABEL: load_private_lo_v2i16_reglo_vreg: ; GFX900-MUBUF: ; %bb.0: ; %entry ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1226,7 +1226,7 @@ entry: ret void } -define void @load_private_lo_v2i16_reghi_vreg(i16 addrspace(5)* byval %in, i16 %reg) #0 { +define void @load_private_lo_v2i16_reghi_vreg(i16 addrspace(5)* byval(i16) %in, i16 %reg) #0 { ; GFX900-MUBUF-LABEL: load_private_lo_v2i16_reghi_vreg: ; GFX900-MUBUF: ; %bb.0: ; %entry ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1279,7 +1279,7 @@ entry: ret void } -define void @load_private_lo_v2f16_reglo_vreg(half addrspace(5)* byval %in, i32 %reg) #0 { +define void @load_private_lo_v2f16_reglo_vreg(half addrspace(5)* byval(half) %in, i32 %reg) #0 { ; GFX900-MUBUF-LABEL: load_private_lo_v2f16_reglo_vreg: ; GFX900-MUBUF: ; %bb.0: ; %entry ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1477,7 +1477,7 @@ entry: ret void } -define void @load_private_lo_v2i16_reglo_vreg_zexti8(i8 addrspace(5)* byval %in, i32 %reg) #0 { +define void @load_private_lo_v2i16_reglo_vreg_zexti8(i8 addrspace(5)* byval(i8) %in, i32 %reg) #0 { ; GFX900-MUBUF-LABEL: load_private_lo_v2i16_reglo_vreg_zexti8: ; GFX900-MUBUF: ; %bb.0: ; %entry ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1528,7 +1528,7 @@ entry: ret void } -define void @load_private_lo_v2i16_reglo_vreg_sexti8(i8 addrspace(5)* byval %in, i32 %reg) #0 { +define void @load_private_lo_v2i16_reglo_vreg_sexti8(i8 addrspace(5)* byval(i8) %in, i32 %reg) #0 { ; GFX900-MUBUF-LABEL: load_private_lo_v2i16_reglo_vreg_sexti8: ; GFX900-MUBUF: ; %bb.0: ; %entry ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) diff --git a/test/CodeGen/AMDGPU/rewrite-out-arguments.ll b/test/CodeGen/AMDGPU/rewrite-out-arguments.ll index 35797c42b9a..573b9757c62 100644 --- a/test/CodeGen/AMDGPU/rewrite-out-arguments.ll +++ b/test/CodeGen/AMDGPU/rewrite-out-arguments.ll @@ -56,7 +56,7 @@ define void @void_one_out_arg_i32_no_use(i32* %val) #0 { ; CHECK-LABEL: define void @skip_byval_arg( ; CHECK-NEXT: store i32 0, i32* %val ; CHECK-NEXT: ret void -define void @skip_byval_arg(i32* byval %val) #0 { +define void @skip_byval_arg(i32* byval(i32) %val) #0 { store i32 0, i32* %val ret void } @@ -65,7 +65,7 @@ define void @skip_byval_arg(i32* byval %val) #0 { ; CHECK-LABEL: define void @skip_optnone( ; CHECK-NEXT: store i32 0, i32* %val ; CHECK-NEXT: ret void -define void @skip_optnone(i32* byval %val) #1 { +define void @skip_optnone(i32* byval(i32) %val) #1 { store i32 0, i32* %val ret void } @@ -74,7 +74,7 @@ define void @skip_optnone(i32* byval %val) #1 { ; CHECK-LABEL: define void @skip_volatile( ; CHECK-NEXT: store volatile i32 0, i32* %val ; CHECK-NEXT: ret void -define void @skip_volatile(i32* byval %val) #0 { +define void @skip_volatile(i32* byval(i32) %val) #0 { store volatile i32 0, i32* %val ret void } @@ -83,7 +83,7 @@ define void @skip_volatile(i32* byval %val) #0 { ; CHECK-LABEL: define void @skip_atomic( ; CHECK-NEXT: store atomic i32 0, i32* %val ; CHECK-NEXT: ret void -define void @skip_atomic(i32* byval %val) #0 { +define void @skip_atomic(i32* byval(i32) %val) #0 { store atomic i32 0, i32* %val seq_cst, align 4 ret void } diff --git a/test/CodeGen/AMDGPU/sibling-call.ll b/test/CodeGen/AMDGPU/sibling-call.ll index bfab65bbab0..3f711e4989f 100644 --- a/test/CodeGen/AMDGPU/sibling-call.ll +++ b/test/CodeGen/AMDGPU/sibling-call.ll @@ -91,7 +91,7 @@ entry: ; GFX9-NEXT: v_add_u32_e32 v0, v0, v1 ; GCN-NEXT: s_setpc_b64 s[30:31] -define hidden fastcc i32 @i32_fastcc_i32_byval_i32(i32 %arg0, i32 addrspace(5)* byval align 4 %arg1) #1 { +define hidden fastcc i32 @i32_fastcc_i32_byval_i32(i32 %arg0, i32 addrspace(5)* byval(i32) align 4 %arg1) #1 { %arg1.load = load i32, i32 addrspace(5)* %arg1, align 4 %add0 = add i32 %arg0, %arg1.load ret i32 %add0 @@ -104,9 +104,9 @@ define hidden fastcc i32 @i32_fastcc_i32_byval_i32(i32 %arg0, i32 addrspace(5)* ; GCN: s_swappc_b64 ; GCN-NOT: v_readlane_b32 s32 ; GCN: s_setpc_b64 -define fastcc i32 @sibling_call_i32_fastcc_i32_byval_i32_byval_parent(i32 %a, i32 addrspace(5)* byval %b.byval, i32 %c) #1 { +define fastcc i32 @sibling_call_i32_fastcc_i32_byval_i32_byval_parent(i32 %a, i32 addrspace(5)* byval(i32) %b.byval, i32 %c) #1 { entry: - %ret = tail call fastcc i32 @i32_fastcc_i32_byval_i32(i32 %a, i32 addrspace(5)* %b.byval) + %ret = tail call fastcc i32 @i32_fastcc_i32_byval_i32(i32 %a, i32 addrspace(5)* byval(i32) %b.byval) ret i32 %ret } @@ -122,7 +122,7 @@ entry: ; GCN-NEXT: s_setpc_b64 define fastcc i32 @sibling_call_i32_fastcc_i32_byval_i32(i32 %a, [32 x i32] %large) #1 { entry: - %ret = tail call fastcc i32 @i32_fastcc_i32_byval_i32(i32 %a, i32 addrspace(5)* inttoptr (i32 16 to i32 addrspace(5)*)) + %ret = tail call fastcc i32 @i32_fastcc_i32_byval_i32(i32 %a, i32 addrspace(5)* byval(i32) inttoptr (i32 16 to i32 addrspace(5)*)) ret i32 %ret } diff --git a/test/CodeGen/AMDGPU/stack-realign.ll b/test/CodeGen/AMDGPU/stack-realign.ll index c9203e8a8c2..438031226ae 100644 --- a/test/CodeGen/AMDGPU/stack-realign.ll +++ b/test/CodeGen/AMDGPU/stack-realign.ll @@ -284,7 +284,7 @@ define void @no_free_regs_spill_bp_to_memory(<32 x i32> %a, i32 %b) #5 { ret void } -define void @spill_bp_to_memory_scratch_reg_needed_mubuf_offset(<32 x i32> %a, i32 %b, [4096 x i8] addrspace(5)* byval align 4 %arg) #5 { +define void @spill_bp_to_memory_scratch_reg_needed_mubuf_offset(<32 x i32> %a, i32 %b, [4096 x i8] addrspace(5)* byval([4096 x i8]) align 4 %arg) #5 { ; If the size of the offset exceeds the MUBUF offset field we need another ; scratch VGPR to hold the offset. diff --git a/test/CodeGen/AMDGPU/store-hi16.ll b/test/CodeGen/AMDGPU/store-hi16.ll index 85ea81ff172..702c28a33a9 100644 --- a/test/CodeGen/AMDGPU/store-hi16.ll +++ b/test/CodeGen/AMDGPU/store-hi16.ll @@ -495,7 +495,7 @@ entry: ; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_setpc_b64 -define void @store_private_hi_v2i16_max_offset(i16 addrspace(5)* byval %out, i32 %arg) #0 { +define void @store_private_hi_v2i16_max_offset(i16 addrspace(5)* byval(i16) %out, i32 %arg) #0 { entry: %value = bitcast i32 %arg to <2 x i16> %hi = extractelement <2 x i16> %value, i32 1 diff --git a/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll b/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll index a48e41f55e5..c50aa4a018b 100644 --- a/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll +++ b/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll @@ -6,6 +6,6 @@ define fastcc void @t() { entry: - %tmp28 = call fastcc i1 null(i32* null, %"byte[]" undef, %"byte[]" undef, %tango.time.Time.Time* byval null) ; [#uses=0] + %tmp28 = call fastcc i1 null(i32* null, %"byte[]" undef, %"byte[]" undef, %tango.time.Time.Time* byval(%tango.time.Time.Time) null) ; [#uses=0] ret void } diff --git a/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll b/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll index f4b93ca74fc..b2557b7165d 100644 --- a/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll +++ b/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll @@ -33,8 +33,8 @@ target triple = "thumbv7-apple-darwin10" define i32 @"\01_fnmatch"(i8* %pattern, i8* %string, i32 %flags) nounwind optsize { entry: - %call4 = tail call i32 @fnmatch1(i8* %pattern, i8* %string, i8* %string, i32 %flags, %union.__mbstate_t* byval @"\01_fnmatch.initial", %union.__mbstate_t* byval @"\01_fnmatch.initial", %struct._xlocale* undef, i32 64) optsize + %call4 = tail call i32 @fnmatch1(i8* %pattern, i8* %string, i8* %string, i32 %flags, %union.__mbstate_t* byval(%union.__mbstate_t) @"\01_fnmatch.initial", %union.__mbstate_t* byval(%union.__mbstate_t) @"\01_fnmatch.initial", %struct._xlocale* undef, i32 64) optsize ret i32 %call4 } -declare i32 @fnmatch1(i8*, i8*, i8*, i32, %union.__mbstate_t* byval, %union.__mbstate_t* byval, %struct._xlocale*, i32) nounwind optsize +declare i32 @fnmatch1(i8*, i8*, i8*, i32, %union.__mbstate_t* byval(%union.__mbstate_t), %union.__mbstate_t* byval(%union.__mbstate_t), %struct._xlocale*, i32) nounwind optsize diff --git a/test/CodeGen/ARM/2011-06-16-TailCallByVal.ll b/test/CodeGen/ARM/2011-06-16-TailCallByVal.ll index d93cc57574b..aa83b7e2fa8 100644 --- a/test/CodeGen/ARM/2011-06-16-TailCallByVal.ll +++ b/test/CodeGen/ARM/2011-06-16-TailCallByVal.ll @@ -16,7 +16,7 @@ target triple = "thumbv7-apple-ios5.0" ; CHECK: add sp, #12 ; CHECK: b.w _puts -define void @f(i8* %s, %struct.A* nocapture byval %a) nounwind optsize { +define void @f(i8* %s, %struct.A* nocapture byval(%struct.A) %a) nounwind optsize { entry: %puts = tail call i32 @puts(i8* %s) ret void diff --git a/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll b/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll index 1b0dbe9f47f..f50fa8c77c7 100644 --- a/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll +++ b/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll @@ -34,7 +34,7 @@ entry: ; CHECK: movw r0, #555 define i32 @main() { entry: - call void (i32, ...) @test_byval_8_bytes_alignment(i32 555, %struct_t* byval @static_val) + call void (i32, ...) @test_byval_8_bytes_alignment(i32 555, %struct_t* byval(%struct_t) @static_val) ret i32 0 } @@ -45,7 +45,7 @@ declare void @f(double); ; CHECK-DAG: str r3, [sp, #12] ; CHECK-DAG: str r2, [sp, #8] ; CHECK-NOT: str r1 -define void @test_byval_8_bytes_alignment_fixed_arg(i32 %n1, %struct_t* byval %val) nounwind { +define void @test_byval_8_bytes_alignment_fixed_arg(i32 %n1, %struct_t* byval(%struct_t) %val) nounwind { entry: %a = getelementptr inbounds %struct_t, %struct_t* %val, i32 0, i32 0 %0 = load double, double* %a @@ -61,6 +61,6 @@ entry: ; CHECK: movw r0, #555 define i32 @main_fixed_arg() { entry: - call void (i32, %struct_t*) @test_byval_8_bytes_alignment_fixed_arg(i32 555, %struct_t* byval @static_val) + call void (i32, %struct_t*) @test_byval_8_bytes_alignment_fixed_arg(i32 555, %struct_t* byval(%struct_t) @static_val) ret i32 0 } diff --git a/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll b/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll index 1530d645620..3ac6f6879a4 100644 --- a/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll +++ b/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll @@ -10,7 +10,7 @@ declare i32 @printf(i8*, ...) ; CHECK-DAG: str r3, [sp, #12] ; CHECK-DAG: str r2, [sp, #8] ; CHECK: vldr d16, [sp, #8] -define void @test_byval_usage_scheduling(i32 %n1, i32 %n2, %struct_t* byval %val) nounwind { +define void @test_byval_usage_scheduling(i32 %n1, i32 %n2, %struct_t* byval(%struct_t) %val) nounwind { entry: %a = getelementptr inbounds %struct_t, %struct_t* %val, i32 0, i32 0 %0 = load double, double* %a diff --git a/test/CodeGen/ARM/2012-10-04-LDRB_POST_IMM-Crash.ll b/test/CodeGen/ARM/2012-10-04-LDRB_POST_IMM-Crash.ll index a59533c4a85..b06da52973d 100644 --- a/test/CodeGen/ARM/2012-10-04-LDRB_POST_IMM-Crash.ll +++ b/test/CodeGen/ARM/2012-10-04-LDRB_POST_IMM-Crash.ll @@ -4,13 +4,13 @@ %my_struct_t = type { i8, i8, i8, i8, i8 } @main.val = private unnamed_addr constant %my_struct_t { i8 1, i8 2, i8 3, i8 4, i8 5 } -declare void @f(i32 %n1, i32 %n2, i32 %n3, %my_struct_t* byval %val); +declare void @f(i32 %n1, i32 %n2, i32 %n3, %my_struct_t* byval(%my_struct_t) %val); ; CHECK-LABEL: main: define i32 @main() nounwind { entry: ; CHECK: ldrb {{(r[0-9]+)}}, {{(\[r[0-9]+\])}}, #1 - call void @f(i32 555, i32 555, i32 555, %my_struct_t* byval @main.val) + call void @f(i32 555, i32 555, i32 555, %my_struct_t* byval(%my_struct_t) @main.val) ret i32 0 } diff --git a/test/CodeGen/ARM/2012-10-18-PR14099-ByvalFrameAddress.ll b/test/CodeGen/ARM/2012-10-18-PR14099-ByvalFrameAddress.ll index fefe16747f1..a1c2bede04a 100644 --- a/test/CodeGen/ARM/2012-10-18-PR14099-ByvalFrameAddress.ll +++ b/test/CodeGen/ARM/2012-10-18-PR14099-ByvalFrameAddress.ll @@ -1,12 +1,12 @@ ; RUN: llc < %s -mtriple=armv7-linux-gnueabi | FileCheck %s %struct.s = type { [4 x i32] } -@v = constant %struct.s zeroinitializer; +@v = constant %struct.s zeroinitializer; declare void @f(%struct.s* %p); ; CHECK-LABEL: t: -define void @t(i32 %a, %struct.s* byval %s) nounwind { +define void @t(i32 %a, %struct.s* byval(%struct.s) %s) nounwind { entry: ; Here we need to only check proper start address of restored %s argument. @@ -25,6 +25,6 @@ entry: define void @caller() { ; CHECK: ldm r{{[0-9]+}}, {r1, r2, r3} - call void @t(i32 0, %struct.s* @v); + call void @t(i32 0, %struct.s* byval(%struct.s) @v); ret void } diff --git a/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll b/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll index c38dd16f0d2..6d26c04445f 100644 --- a/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll +++ b/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll @@ -49,12 +49,12 @@ declare void @fooUseParam(%artz* ) -define void @foo(%artz* byval %s) { +define void @foo(%artz* byval(%artz) %s) { call void @fooUseParam(%artz* %s) ret void } -define void @foo2(%artz* byval %s, i32 %p, %artz* byval %s2) { +define void @foo2(%artz* byval(%artz) %s, i32 %p, %artz* byval(%artz) %s2) { call void @fooUseParam(%artz* %s) call void @fooUseParam(%artz* %s2) ret void @@ -62,12 +62,12 @@ define void @foo2(%artz* byval %s, i32 %p, %artz* byval %s2) { define void @doFoo() { - call void @foo(%artz* byval @static_val) + call void @foo(%artz* byval(%artz) @static_val) ret void } define void @doFoo2() { - call void @foo2(%artz* byval @static_val, i32 0, %artz* byval @static_val) + call void @foo2(%artz* byval(%artz) @static_val, i32 0, %artz* byval(%artz) @static_val) ret void } diff --git a/test/CodeGen/ARM/2013-04-16-AAPCS-C5-vs-VFP.ll b/test/CodeGen/ARM/2013-04-16-AAPCS-C5-vs-VFP.ll index 5e82b0925b2..91e01147730 100644 --- a/test/CodeGen/ARM/2013-04-16-AAPCS-C5-vs-VFP.ll +++ b/test/CodeGen/ARM/2013-04-16-AAPCS-C5-vs-VFP.ll @@ -30,7 +30,7 @@ define void @foo2(double %p0, ; --> D0 double %p7, ; --> D7 double %p8, ; --> Stack i32 %p9, ; --> R0 - %struct_t* byval %p10) ; --> Stack+8 + %struct_t* byval(%struct_t) %p10) ; --> Stack+8 { entry: ;CHECK: push {r7, lr} @@ -55,7 +55,7 @@ entry: double 23.7, ; --> D7 double 23.8, ; --> Stack i32 43, ; --> R0, not Stack+8 - %struct_t* byval @static_val) ; --> Stack+8, not R1 + %struct_t* byval(%struct_t) @static_val) ; --> Stack+8, not R1 ret void } diff --git a/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll b/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll index ac5b6f9c970..d6de8c9587c 100644 --- a/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll +++ b/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll @@ -16,9 +16,9 @@ define void @foo(double %vfp0, ; --> D0, NSAA=SP double %vfp6, ; --> D6, NSAA=SP double %vfp7, ; --> D7, NSAA=SP double %vfp8, ; --> SP, NSAA=SP+8 (!) - i32 %p0, ; --> R0, NSAA=SP+8 - %st_t* byval %p1, ; --> R1, R2, NSAA=SP+8 - i32 %p2, ; --> R3, NSAA=SP+8 + i32 %p0, ; --> R0, NSAA=SP+8 + %st_t* byval(%st_t) %p1, ; --> R1, R2, NSAA=SP+8 + i32 %p2, ; --> R3, NSAA=SP+8 i32 %p3) #0 { ; --> SP+4, NSAA=SP+12 entry: ;CHECK: sub sp, #12 @@ -42,7 +42,7 @@ entry: double 23.6, double 23.7, double 23.8, - i32 0, %st_t* byval @static_val, i32 1, i32 2) + i32 0, %st_t* byval(%st_t) @static_val, i32 1, i32 2) ret void } diff --git a/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll b/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll index 944a60c0610..d2e3fef51c3 100644 --- a/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll +++ b/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll @@ -14,10 +14,10 @@ define void @foo(double %vfp0, ; --> D0, NSAA=SP double %vfp6, ; --> D6, NSAA=SP double %vfp7, ; --> D7, NSAA=SP double %vfp8, ; --> SP, NSAA=SP+8 (!) - i32 %p0, ; --> R0, NSAA=SP+8 - %st_t* byval %p1, ; --> SP+8, 4 words NSAA=SP+24 - i32 %p2) #0 { ; --> SP+24, NSAA=SP+24 - + i32 %p0, ; --> R0, NSAA=SP+8 + %st_t* byval(%st_t) %p1, ; --> SP+8, 4 words NSAA=SP+24 + i32 %p2) #0 { ; --> SP+24, NSAA=SP+24 + entry: ;CHECK: push {r7, lr} ;CHECK: ldr r0, [sp, #32] @@ -39,7 +39,7 @@ entry: double 23.6, double 23.7, double 23.8, - i32 0, %st_t* byval @static_val, i32 1) + i32 0, %st_t* byval(%st_t) @static_val, i32 1) ret void } diff --git a/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding.ll b/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding.ll index 3c20c6b5363..353fade4992 100644 --- a/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding.ll +++ b/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding.ll @@ -5,7 +5,7 @@ define void @check227( i32 %b, - %struct.S227* byval nocapture %arg0, + %struct.S227* byval(%struct.S227) nocapture %arg0, %struct.S227* %arg1) { ; b --> R0 ; arg0 --> [R1, R2, R3, SP+0 .. SP+188) diff --git a/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding2.ll b/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding2.ll index d3aa2331d45..0f9273ded6b 100644 --- a/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding2.ll +++ b/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding2.ll @@ -4,8 +4,8 @@ %struct4bytes = type { i32 } %struct20bytes = type { i32, i32, i32, i32, i32 } -define void @foo(%struct4bytes* byval %p0, ; --> R0 - %struct20bytes* byval %p1 ; --> R1,R2,R3, [SP+0 .. SP+8) +define void @foo(%struct4bytes* byval(%struct4bytes) %p0, ; --> R0 + %struct20bytes* byval(%struct20bytes) %p1 ; --> R1,R2,R3, [SP+0 .. SP+8) ) { ;CHECK: sub sp, sp, #16 ;CHECK: push {r11, lr} diff --git a/test/CodeGen/ARM/2013-06-03-ByVal-2Kbytes.ll b/test/CodeGen/ARM/2013-06-03-ByVal-2Kbytes.ll index 1c138007021..e5059edf0c4 100644 --- a/test/CodeGen/ARM/2013-06-03-ByVal-2Kbytes.ll +++ b/test/CodeGen/ARM/2013-06-03-ByVal-2Kbytes.ll @@ -12,19 +12,19 @@ define void @f(%big_struct0* %p0, %big_struct1* %p1) { ;CHECK: sub sp, sp, #8 ;CHECK: sub sp, sp, #2048 ;CHECK: bl callme0 - call void @callme0(%big_struct0* byval %p0) + call void @callme0(%big_struct0* byval(%big_struct0) %p0) ;CHECK: add sp, sp, #8 ;CHECK: add sp, sp, #2048 ;CHECK: sub sp, sp, #2048 ;CHECK: bl callme1 - call void @callme1(%big_struct1* byval %p1) + call void @callme1(%big_struct1* byval(%big_struct1) %p1) ;CHECK: add sp, sp, #2048 ret void } -declare void @callme0(%big_struct0* byval) -declare void @callme1(%big_struct1* byval) +declare void @callme0(%big_struct0* byval(%big_struct0)) +declare void @callme1(%big_struct1* byval(%big_struct1)) diff --git a/test/CodeGen/ARM/2014-02-21-byval-reg-split-alignment.ll b/test/CodeGen/ARM/2014-02-21-byval-reg-split-alignment.ll index f8c4d5d8db8..f9d24ad1ad4 100644 --- a/test/CodeGen/ARM/2014-02-21-byval-reg-split-alignment.ll +++ b/test/CodeGen/ARM/2014-02-21-byval-reg-split-alignment.ll @@ -11,7 +11,7 @@ declare void @usePtr(%struct8bytes8align*) ; a -> r0 ; b -> r1..r3 ; c -> sp+0..sp+7 -define void @foo1(i32 %a, %struct12bytes* byval %b, i64 %c) { +define void @foo1(i32 %a, %struct12bytes* byval(%struct12bytes) %b, i64 %c) { ; CHECK-LABEL: foo1 ; CHECK: sub sp, sp, #12 ; CHECK: push {r11, lr} @@ -30,7 +30,7 @@ define void @foo1(i32 %a, %struct12bytes* byval %b, i64 %c) { ; a -> r0 ; b -> r2..r3 -define void @foo2(i32 %a, %struct8bytes8align* byval %b) { +define void @foo2(i32 %a, %struct8bytes8align* byval(%struct8bytes8align) %b) { ; CHECK-LABEL: foo2 ; CHECK: sub sp, sp, #8 ; CHECK: push {r11, lr} @@ -47,7 +47,7 @@ define void @foo2(i32 %a, %struct8bytes8align* byval %b) { ; a -> r0..r1 ; b -> r2 -define void @foo3(%struct8bytes8align* byval %a, %struct4bytes* byval %b) { +define void @foo3(%struct8bytes8align* byval(%struct8bytes8align) %a, %struct4bytes* byval(%struct4bytes) %b) { ; CHECK-LABEL: foo3 ; CHECK: sub sp, sp, #16 ; CHECK: push {r11, lr} @@ -64,7 +64,7 @@ define void @foo3(%struct8bytes8align* byval %a, %struct4bytes* byval %b) { ; a -> r0 ; b -> r2..r3 -define void @foo4(%struct4bytes* byval %a, %struct8bytes8align* byval %b) { +define void @foo4(%struct4bytes* byval(%struct4bytes) %a, %struct8bytes8align* byval(%struct8bytes8align) %b) { ; CHECK-LABEL: foo4 ; CHECK: sub sp, sp, #16 ; CHECK: push {r11, lr} @@ -84,7 +84,7 @@ define void @foo4(%struct4bytes* byval %a, %struct8bytes8align* byval %b) { ; a -> r0..r1 ; b -> r2 ; c -> r3 -define void @foo5(%struct8bytes8align* byval %a, %struct4bytes* byval %b, %struct4bytes* byval %c) { +define void @foo5(%struct8bytes8align* byval(%struct8bytes8align) %a, %struct4bytes* byval(%struct4bytes) %b, %struct4bytes* byval(%struct4bytes) %c) { ; CHECK-LABEL: foo5 ; CHECK: sub sp, sp, #16 ; CHECK: push {r11, lr} @@ -102,7 +102,7 @@ define void @foo5(%struct8bytes8align* byval %a, %struct4bytes* byval %b, %struc ; a..c -> r0..r2 ; d -> sp+0..sp+7 -define void @foo6(i32 %a, i32 %b, i32 %c, %struct8bytes8align* byval %d) { +define void @foo6(i32 %a, i32 %b, i32 %c, %struct8bytes8align* byval(%struct8bytes8align) %d) { ; CHECK-LABEL: foo6 ; CHECK: push {r11, lr} ; CHECK: add r0, sp, #8 diff --git a/test/CodeGen/ARM/GlobalISel/arm-unsupported.ll b/test/CodeGen/ARM/GlobalISel/arm-unsupported.ll index 78cdd59894f..1c0072ef5e3 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-unsupported.ll +++ b/test/CodeGen/ARM/GlobalISel/arm-unsupported.ll @@ -122,7 +122,7 @@ define i32 @test_thread_local_global() { %byval.class = type { i32 } -define void @test_byval_arg(%byval.class* byval %x) { +define void @test_byval_arg(%byval.class* byval(%byval.class) %x) { ; CHECK: remark: {{.*}} unable to lower arguments: void (%byval.class*)* ; CHECK-LABEL: warning: Instruction selection used fallback path for test_byval ret void @@ -131,7 +131,7 @@ define void @test_byval_arg(%byval.class* byval %x) { define void @test_byval_param(%byval.class* %x) { ; CHECK: remark: {{.*}} unable to translate instruction: call ; CHECK-LABEL: warning: Instruction selection used fallback path for test_byval_param - call void @test_byval_arg(%byval.class* byval %x) + call void @test_byval_arg(%byval.class* byval(%byval.class) %x) ret void } diff --git a/test/CodeGen/ARM/align-sp-adjustment.ll b/test/CodeGen/ARM/align-sp-adjustment.ll index cce7b03e236..7840d95c151 100644 --- a/test/CodeGen/ARM/align-sp-adjustment.ll +++ b/test/CodeGen/ARM/align-sp-adjustment.ll @@ -11,7 +11,7 @@ @.str.3 = private unnamed_addr constant [2 x i8] c"d\00", align 1 declare i32* @_Z4bar3iiPKcS0_i(i32, i32, i8*, i8*, i32) -declare void @_Z4bar1i8struct_2(i32, %struct.struct_2* byval align 4) +declare void @_Z4bar1i8struct_2(i32, %struct.struct_2* byval(%struct.struct_2) align 4) declare i32 @_Z4bar2PiPKc(i32*, i8*) define void @_Z3fooiiiii(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5) #0 { @@ -38,7 +38,7 @@ for.inc: br i1 %cmp, label %for.body, label %for.end for.end: - call void @_Z4bar1i8struct_2(i32 %p4, %struct.struct_2* byval nonnull align 4 %params) #4 + call void @_Z4bar1i8struct_2(i32 %p4, %struct.struct_2* byval(%struct.struct_2) nonnull align 4 %params) #4 br label %cleanup.8 cleanup.8: diff --git a/test/CodeGen/ARM/alloca-align.ll b/test/CodeGen/ARM/alloca-align.ll index 3326d361c07..76c265abbd1 100644 --- a/test/CodeGen/ARM/alloca-align.ll +++ b/test/CodeGen/ARM/alloca-align.ll @@ -3,7 +3,7 @@ target triple="arm--" @glob = external global i32* -declare void @bar(i32*, [20000 x i8]* byval) +declare void @bar(i32*, [20000 x i8]* byval([20000 x i8])) ; CHECK-LABEL: foo: ; We should see the stack getting additional alignment @@ -17,7 +17,7 @@ declare void @bar(i32*, [20000 x i8]* byval) define void @foo([20000 x i8]* %addr) { %tmp = alloca [4 x i32], align 32 %tmp0 = getelementptr [4 x i32], [4 x i32]* %tmp, i32 0, i32 0 - call void @bar(i32* %tmp0, [20000 x i8]* byval %addr) + call void @bar(i32* %tmp0, [20000 x i8]* byval([20000 x i8]) %addr) ret void } diff --git a/test/CodeGen/ARM/byval-align.ll b/test/CodeGen/ARM/byval-align.ll index 8a506280dd5..e3fe15c7010 100644 --- a/test/CodeGen/ARM/byval-align.ll +++ b/test/CodeGen/ARM/byval-align.ll @@ -6,7 +6,7 @@ ; users of byval alignments > 4, so no real calls for ABI stability. ; "byval align 16" can't fit in any regs with an i8* taking up r0. -define i32 @test_align16(i8*, [4 x i32]* byval align 16 %b) { +define i32 @test_align16(i8*, [4 x i32]* byval([4 x i32]) align 16 %b) { ; CHECK-LABEL: test_align16: ; CHECK-NOT: sub sp ; CHECK: push {r4, r7, lr} @@ -22,7 +22,7 @@ define i32 @test_align16(i8*, [4 x i32]* byval align 16 %b) { ; byval align 8 can, but we used to incorrectly set r7 here (miscalculating the ; space taken up by arg regs). -define i32 @test_align8(i8*, [4 x i32]* byval align 8 %b) { +define i32 @test_align8(i8*, [4 x i32]* byval([4 x i32]) align 8 %b) { ; CHECK-LABEL: test_align8: ; CHECK: sub sp, #8 ; CHECK: push {r4, r7, lr} @@ -40,7 +40,7 @@ define i32 @test_align8(i8*, [4 x i32]* byval align 8 %b) { ; "byval align 32" can't fit in regs no matter what: it would be misaligned ; unless the incoming stack was deliberately misaligned. -define i32 @test_align32(i8*, [4 x i32]* byval align 32 %b) { +define i32 @test_align32(i8*, [4 x i32]* byval([4 x i32]) align 32 %b) { ; CHECK-LABEL: test_align32: ; CHECK-NOT: sub sp ; CHECK: push {r4, r7, lr} @@ -67,7 +67,7 @@ define void @test_call_align16() { ; While we're here, make sure the caller also puts it at sp ; CHECK: mov r[[BASE:[0-9]+]], sp ; CHECK: vst1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r[[BASE]]] - call i32 @test_align16(i8* null, [4 x i32]* byval align 16 @var) + call i32 @test_align16(i8* null, [4 x i32]* byval([4 x i32]) align 16 @var) ret void } diff --git a/test/CodeGen/ARM/byval_load_align.ll b/test/CodeGen/ARM/byval_load_align.ll index 141ead6c0ad..eb34badc8d5 100644 --- a/test/CodeGen/ARM/byval_load_align.ll +++ b/test/CodeGen/ARM/byval_load_align.ll @@ -16,11 +16,11 @@ ; Function Attrs: nounwind ssp define void @Client() #0 { entry: - tail call void @Logger(i8 signext 97, %struct.ModuleID* byval @sID) #2 + tail call void @Logger(i8 signext 97, %struct.ModuleID* byval(%struct.ModuleID) @sID) #2 ret void } -declare void @Logger(i8 signext, %struct.ModuleID* byval) #1 +declare void @Logger(i8 signext, %struct.ModuleID* byval(%struct.ModuleID)) #1 attributes #0 = { nounwind ssp "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/ARM/copy-by-struct-i32.ll b/test/CodeGen/ARM/copy-by-struct-i32.ll index d6b72a2f0af..d3bc2d61fcb 100644 --- a/test/CodeGen/ARM/copy-by-struct-i32.ll +++ b/test/CodeGen/ARM/copy-by-struct-i32.ll @@ -54,7 +54,7 @@ define arm_aapcscc void @s(i64* %q, %struct.anon* %p) { entry: %0 = load i64, i64* %q, align 8 %sub = add nsw i64 %0, -1 - tail call arm_aapcscc void bitcast (void (...)* @r to void (%struct.anon*, %struct.anon*, i64)*)(%struct.anon* byval nonnull align 8 %p, %struct.anon* byval nonnull align 8 %p, i64 %sub) + tail call arm_aapcscc void bitcast (void (...)* @r to void (%struct.anon*, %struct.anon*, i64)*)(%struct.anon* byval(%struct.anon) nonnull align 8 %p, %struct.anon* byval(%struct.anon) nonnull align 8 %p, i64 %sub) ret void } diff --git a/test/CodeGen/ARM/ssp-data-layout.ll b/test/CodeGen/ARM/ssp-data-layout.ll index feb0189be9e..8a850c48db8 100644 --- a/test/CodeGen/ARM/ssp-data-layout.ll +++ b/test/CodeGen/ARM/ssp-data-layout.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -frame-pointer=all -mcpu=cortex-a8 -mtriple arm-linux-gnu -target-abi=apcs -o - | FileCheck %s ; This test is fairly fragile. The goal is to ensure that "large" stack -; objects are allocated closest to the stack protector (i.e., farthest away +; objects are allocated closest to the stack protector (i.e., farthest away ; from the Stack Pointer.) In standard SSP mode this means that large (>= ; ssp-buffer-size) arrays and structures containing such arrays are ; closet to the protector. With sspstrong and sspreq this means large @@ -159,7 +159,7 @@ entry: %coerce.dive26 = getelementptr %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d, i32 0, i32 0 %7 = bitcast [2 x i16]* %coerce.dive26 to i32* %8 = load i32, i32* %7, align 1 - call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval align 4 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2) + call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval(%struct.struct_large_nonchar) align 4 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2) ret void } @@ -170,7 +170,7 @@ entry: ; 136 large_char . arrays >= ssp-buffer-size ; 128 struct_large_char . ; 96 struct_large_nonchar . -; 84+8 small_non_char | Group 2, nested arrays, +; 84+8 small_non_char | Group 2, nested arrays, ; 90 small_char | arrays < ssp-buffer-size ; 88 struct_small_char | ; 84 struct_small_nonchar | @@ -178,7 +178,7 @@ entry: ; 76 scalar1 + Group 4, everything else ; 72 scalar2 + ; 68 scalar3 + -; +; ; CHECK: layout_sspstrong: ; CHECK: bl get_scalar1 @@ -304,14 +304,14 @@ entry: %coerce.dive26 = getelementptr %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d, i32 0, i32 0 %7 = bitcast [2 x i16]* %coerce.dive26 to i32* %8 = load i32, i32* %7, align 1 - call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval align 4 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2) + call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval(%struct.struct_large_nonchar) align 4 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2) ret void } define void @layout_sspreq() sspreq { entry: ; Expected stack layout for sspreq is the same as sspstrong -; +; ; CHECK: layout_sspreq: ; CHECK: bl get_scalar1 @@ -437,7 +437,7 @@ entry: %coerce.dive26 = getelementptr %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d, i32 0, i32 0 %7 = bitcast [2 x i16]* %coerce.dive26 to i32* %8 = load i32, i32* %7, align 1 - call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval align 4 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2) + call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval(%struct.struct_large_nonchar) align 4 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2) ret void } @@ -476,7 +476,7 @@ entry: %coerce.dive5 = getelementptr %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d2, i32 0, i32 0 %5 = bitcast [2 x i16]* %coerce.dive5 to i32* %6 = load i32, i32* %5, align 1 - call void @takes_all(i64 %2, i16 %4, %struct.struct_large_nonchar* byval align 4 %d1, i32 %6, i8* null, i8* null, i32* null, i16* null, i32* null, i32 0, i32 0, i32 0) + call void @takes_all(i64 %2, i16 %4, %struct.struct_large_nonchar* byval(%struct.struct_large_nonchar) align 4 %d1, i32 %6, i8* null, i8* null, i32* null, i16* null, i32* null, i32 0, i32 0, i32 0) ret void } @@ -519,4 +519,4 @@ declare void @end_struct_large_nonchar() declare signext i16 @get_struct_small_nonchar() declare void @end_struct_small_nonchar() -declare void @takes_all(i64, i16, %struct.struct_large_nonchar* byval align 8, i32, i8*, i8*, i32*, i16*, i32*, i32, i32, i32) +declare void @takes_all(i64, i16, %struct.struct_large_nonchar* byval(%struct.struct_large_nonchar) align 8, i32, i8*, i8*, i32*, i16*, i32*, i32, i32, i32) diff --git a/test/CodeGen/ARM/struct-byval-frame-index.ll b/test/CodeGen/ARM/struct-byval-frame-index.ll index 0e33a9efbc9..c398e362b1c 100644 --- a/test/CodeGen/ARM/struct-byval-frame-index.ll +++ b/test/CodeGen/ARM/struct-byval-frame-index.ll @@ -33,6 +33,6 @@ entry: } ; Function Attrs: nounwind -declare void @RestoreMVBlock8x8(i32, i32, %structN* byval nocapture, i32) #1 +declare void @RestoreMVBlock8x8(i32, i32, %structN* byval(%structN) nocapture, i32) #1 attributes #1 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/ARM/struct_byval.ll b/test/CodeGen/ARM/struct_byval.ll index 6c8f6fa0b39..69fdd243559 100644 --- a/test/CodeGen/ARM/struct_byval.ll +++ b/test/CodeGen/ARM/struct_byval.ll @@ -16,7 +16,7 @@ entry: ; CHECK: str ; CHECK-NOT:bne %st = alloca %struct.SmallStruct, align 4 - %call = call i32 @e1(%struct.SmallStruct* byval %st) + %call = call i32 @e1(%struct.SmallStruct* byval(%struct.SmallStruct) %st) ret i32 0 } @@ -37,7 +37,7 @@ entry: ; NACL: str ; NACL: bne %st = alloca %struct.LargeStruct, align 4 - %call = call i32 @e2(%struct.LargeStruct* byval %st) + %call = call i32 @e2(%struct.LargeStruct* byval(%struct.LargeStruct) %st) ret i32 0 } @@ -55,18 +55,18 @@ entry: ; NACL: vst1 ; NACL: bne %st = alloca %struct.LargeStruct, align 16 - %call = call i32 @e3(%struct.LargeStruct* byval align 16 %st) + %call = call i32 @e3(%struct.LargeStruct* byval(%struct.LargeStruct) align 16 %st) ret i32 0 } -declare i32 @e1(%struct.SmallStruct* nocapture byval %in) nounwind -declare i32 @e2(%struct.LargeStruct* nocapture byval %in) nounwind -declare i32 @e3(%struct.LargeStruct* nocapture byval align 16 %in) nounwind +declare i32 @e1(%struct.SmallStruct* nocapture byval(%struct.SmallStruct) %in) nounwind +declare i32 @e2(%struct.LargeStruct* nocapture byval(%struct.LargeStruct) %in) nounwind +declare i32 @e3(%struct.LargeStruct* nocapture byval(%struct.LargeStruct) align 16 %in) nounwind ; rdar://12442472 ; We can't do tail call since address of s is passed to the callee and part of ; s is in caller's local frame. -define void @f3(%struct.SmallStruct* nocapture byval %s) nounwind optsize { +define void @f3(%struct.SmallStruct* nocapture byval(%struct.SmallStruct) %s) nounwind optsize { ; CHECK-LABEL: f3 ; CHECK: bl _consumestruct entry: @@ -75,7 +75,7 @@ entry: ret void } -define void @f4(%struct.SmallStruct* nocapture byval %s) nounwind optsize { +define void @f4(%struct.SmallStruct* nocapture byval(%struct.SmallStruct) %s) nounwind optsize { ; CHECK-LABEL: f4 ; CHECK: bl _consumestruct entry: @@ -86,7 +86,7 @@ entry: } ; We can do tail call here since s is in the incoming argument area. -define void @f5(i32 %a, i32 %b, i32 %c, i32 %d, %struct.SmallStruct* nocapture byval %s) nounwind optsize { +define void @f5(i32 %a, i32 %b, i32 %c, i32 %d, %struct.SmallStruct* nocapture byval(%struct.SmallStruct) %s) nounwind optsize { ; CHECK-LABEL: f5 ; CHECK: b{{(\.w)?}} _consumestruct entry: @@ -95,7 +95,7 @@ entry: ret void } -define void @f6(i32 %a, i32 %b, i32 %c, i32 %d, %struct.SmallStruct* nocapture byval %s) nounwind optsize { +define void @f6(i32 %a, i32 %b, i32 %c, i32 %d, %struct.SmallStruct* nocapture byval(%struct.SmallStruct) %s) nounwind optsize { ; CHECK-LABEL: f6 ; CHECK: b{{(\.w)?}} _consumestruct entry: @@ -110,12 +110,12 @@ declare void @consumestruct(i8* nocapture %structp, i32 %structsize) nounwind ; PR17309 %struct.I.8 = type { [10 x i32], [3 x i8] } -declare void @use_I(%struct.I.8* byval) +declare void @use_I(%struct.I.8* byval(%struct.I.8)) define void @test_I_16() { ; CHECK-LABEL: test_I_16 ; CHECK: ldrb ; CHECK: strb entry: - call void @use_I(%struct.I.8* byval align 16 undef) + call void @use_I(%struct.I.8* byval(%struct.I.8) align 16 undef) ret void } diff --git a/test/CodeGen/ARM/struct_byval_arm_t1_t2.ll b/test/CodeGen/ARM/struct_byval_arm_t1_t2.ll index 1ff8a39fbb8..eb1e710ae6c 100644 --- a/test/CodeGen/ARM/struct_byval_arm_t1_t2.ll +++ b/test/CodeGen/ARM/struct_byval_arm_t1_t2.ll @@ -25,33 +25,33 @@ ;cleanup if the number of bytes does not divide evenly by the store size %struct.A = type <{ [ 10 x i32 ] }> ; 40 bytes -declare void @use_A(%struct.A* byval) +declare void @use_A(%struct.A* byval(%struct.A)) %struct.B = type <{ [ 10 x i32 ], i8 }> ; 41 bytes -declare void @use_B(%struct.B* byval) +declare void @use_B(%struct.B* byval(%struct.B)) %struct.C = type <{ [ 10 x i32 ], [ 3 x i8 ] }> ; 43 bytes -declare void @use_C(%struct.C* byval) +declare void @use_C(%struct.C* byval(%struct.C)) %struct.D = type <{ [ 100 x i32 ] }> ; 400 bytes -declare void @use_D(%struct.D* byval) +declare void @use_D(%struct.D* byval(%struct.D)) %struct.E = type <{ [ 100 x i32 ], i8 }> ; 401 bytes -declare void @use_E(%struct.E* byval) +declare void @use_E(%struct.E* byval(%struct.E)) %struct.F = type <{ [ 100 x i32 ], [ 3 x i8 ] }> ; 403 bytes -declare void @use_F(%struct.F* byval) +declare void @use_F(%struct.F* byval(%struct.F)) %struct.G = type { [ 10 x i32 ] } ; 40 bytes -declare void @use_G(%struct.G* byval) +declare void @use_G(%struct.G* byval(%struct.G)) %struct.H = type { [ 10 x i32 ], i8 } ; 41 bytes -declare void @use_H(%struct.H* byval) +declare void @use_H(%struct.H* byval(%struct.H)) %struct.I = type { [ 10 x i32 ], [ 3 x i8 ] } ; 43 bytes -declare void @use_I(%struct.I* byval) +declare void @use_I(%struct.I* byval(%struct.I)) %struct.J = type { [ 100 x i32 ] } ; 400 bytes -declare void @use_J(%struct.J* byval) +declare void @use_J(%struct.J* byval(%struct.J)) %struct.K = type { [ 100 x i32 ], i8 } ; 401 bytes -declare void @use_K(%struct.K* byval) +declare void @use_K(%struct.K* byval(%struct.K)) %struct.L = type { [ 100 x i32 ], [ 3 x i8 ] } ; 403 bytes -declare void @use_L(%struct.L* byval) +declare void @use_L(%struct.L* byval(%struct.L)) %struct.M = type { [ 64 x i8 ] } ; 64 bytes -declare void @use_M(%struct.M* byval) +declare void @use_M(%struct.M* byval(%struct.M)) %struct.N = type { [ 128 x i8 ] } ; 128 bytes -declare void @use_N(%struct.N* byval) +declare void @use_N(%struct.N* byval(%struct.N)) ;ARM-LABEL: : ;THUMB2-LABEL: : @@ -71,7 +71,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 entry: %a = alloca %struct.A, align 1 - call void @use_A(%struct.A* byval align 1 %a) + call void @use_A(%struct.A* byval(%struct.A) align 1 %a) ret void } ;ARM-LABEL: : @@ -92,7 +92,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 entry: %a = alloca %struct.A, align 2 - call void @use_A(%struct.A* byval align 2 %a) + call void @use_A(%struct.A* byval(%struct.A) align 2 %a) ret void } ;ARM-LABEL: : @@ -113,7 +113,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 entry: %a = alloca %struct.A, align 4 - call void @use_A(%struct.A* byval align 4 %a) + call void @use_A(%struct.A* byval(%struct.A) align 4 %a) ret void } ;ARM-LABEL: : @@ -135,7 +135,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.A, align 8 - call void @use_A(%struct.A* byval align 8 %a) + call void @use_A(%struct.A* byval(%struct.A) align 8 %a) ret void } ;ARM-LABEL: : @@ -159,7 +159,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.A, align 16 - call void @use_A(%struct.A* byval align 16 %a) + call void @use_A(%struct.A* byval(%struct.A) align 16 %a) ret void } ;ARM-LABEL: : @@ -180,7 +180,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 entry: %a = alloca %struct.B, align 1 - call void @use_B(%struct.B* byval align 1 %a) + call void @use_B(%struct.B* byval(%struct.B) align 1 %a) ret void } ;ARM-LABEL: : @@ -205,7 +205,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 entry: %a = alloca %struct.B, align 2 - call void @use_B(%struct.B* byval align 2 %a) + call void @use_B(%struct.B* byval(%struct.B) align 2 %a) ret void } ;ARM-LABEL: : @@ -230,7 +230,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 entry: %a = alloca %struct.B, align 4 - call void @use_B(%struct.B* byval align 4 %a) + call void @use_B(%struct.B* byval(%struct.B) align 4 %a) ret void } ;ARM-LABEL: : @@ -256,7 +256,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.B, align 8 - call void @use_B(%struct.B* byval align 8 %a) + call void @use_B(%struct.B* byval(%struct.B) align 8 %a) ret void } ;ARM-LABEL: : @@ -282,7 +282,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.B, align 16 - call void @use_B(%struct.B* byval align 16 %a) + call void @use_B(%struct.B* byval(%struct.B) align 16 %a) ret void } ;ARM-LABEL: : @@ -303,7 +303,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 entry: %a = alloca %struct.C, align 1 - call void @use_C(%struct.C* byval align 1 %a) + call void @use_C(%struct.C* byval(%struct.C) align 1 %a) ret void } ;ARM-LABEL: : @@ -328,7 +328,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 entry: %a = alloca %struct.C, align 2 - call void @use_C(%struct.C* byval align 2 %a) + call void @use_C(%struct.C* byval(%struct.C) align 2 %a) ret void } ;ARM-LABEL: : @@ -354,7 +354,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 entry: %a = alloca %struct.C, align 4 - call void @use_C(%struct.C* byval align 4 %a) + call void @use_C(%struct.C* byval(%struct.C) align 4 %a) ret void } ;ARM-LABEL: : @@ -381,7 +381,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.C, align 8 - call void @use_C(%struct.C* byval align 8 %a) + call void @use_C(%struct.C* byval(%struct.C) align 8 %a) ret void } ;ARM-LABEL: : @@ -408,7 +408,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.C, align 16 - call void @use_C(%struct.C* byval align 16 %a) + call void @use_C(%struct.C* byval(%struct.C) align 16 %a) ret void } ;ARM-LABEL: : @@ -433,7 +433,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 entry: %a = alloca %struct.D, align 1 - call void @use_D(%struct.D* byval align 1 %a) + call void @use_D(%struct.D* byval(%struct.D) align 1 %a) ret void } ;ARM-LABEL: : @@ -458,7 +458,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 entry: %a = alloca %struct.D, align 2 - call void @use_D(%struct.D* byval align 2 %a) + call void @use_D(%struct.D* byval(%struct.D) align 2 %a) ret void } ;ARM-LABEL: : @@ -483,7 +483,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 entry: %a = alloca %struct.D, align 4 - call void @use_D(%struct.D* byval align 4 %a) + call void @use_D(%struct.D* byval(%struct.D) align 4 %a) ret void } ;ARM-LABEL: : @@ -509,7 +509,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.D, align 8 - call void @use_D(%struct.D* byval align 8 %a) + call void @use_D(%struct.D* byval(%struct.D) align 8 %a) ret void } ;ARM-LABEL: : @@ -535,7 +535,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.D, align 16 - call void @use_D(%struct.D* byval align 16 %a) + call void @use_D(%struct.D* byval(%struct.D) align 16 %a) ret void } ;ARM-LABEL: : @@ -560,7 +560,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 entry: %a = alloca %struct.E, align 1 - call void @use_E(%struct.E* byval align 1 %a) + call void @use_E(%struct.E* byval(%struct.E) align 1 %a) ret void } ;ARM-LABEL: : @@ -589,7 +589,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 entry: %a = alloca %struct.E, align 2 - call void @use_E(%struct.E* byval align 2 %a) + call void @use_E(%struct.E* byval(%struct.E) align 2 %a) ret void } ;ARM-LABEL: : @@ -618,7 +618,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 entry: %a = alloca %struct.E, align 4 - call void @use_E(%struct.E* byval align 4 %a) + call void @use_E(%struct.E* byval(%struct.E) align 4 %a) ret void } ;ARM-LABEL: : @@ -648,7 +648,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.E, align 8 - call void @use_E(%struct.E* byval align 8 %a) + call void @use_E(%struct.E* byval(%struct.E) align 8 %a) ret void } ;ARM-LABEL: : @@ -678,7 +678,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.E, align 16 - call void @use_E(%struct.E* byval align 16 %a) + call void @use_E(%struct.E* byval(%struct.E) align 16 %a) ret void } ;ARM-LABEL: : @@ -703,7 +703,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 entry: %a = alloca %struct.F, align 1 - call void @use_F(%struct.F* byval align 1 %a) + call void @use_F(%struct.F* byval(%struct.F) align 1 %a) ret void } ;ARM-LABEL: : @@ -732,7 +732,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 entry: %a = alloca %struct.F, align 2 - call void @use_F(%struct.F* byval align 2 %a) + call void @use_F(%struct.F* byval(%struct.F) align 2 %a) ret void } ;ARM-LABEL: : @@ -762,7 +762,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 entry: %a = alloca %struct.F, align 4 - call void @use_F(%struct.F* byval align 4 %a) + call void @use_F(%struct.F* byval(%struct.F) align 4 %a) ret void } ;ARM-LABEL: : @@ -793,7 +793,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.F, align 8 - call void @use_F(%struct.F* byval align 8 %a) + call void @use_F(%struct.F* byval(%struct.F) align 8 %a) ret void } ;ARM-LABEL: : @@ -824,7 +824,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.F, align 16 - call void @use_F(%struct.F* byval align 16 %a) + call void @use_F(%struct.F* byval(%struct.F) align 16 %a) ret void } ;ARM-LABEL: : @@ -845,7 +845,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 entry: %a = alloca %struct.G, align 1 - call void @use_G(%struct.G* byval align 1 %a) + call void @use_G(%struct.G* byval(%struct.G) align 1 %a) ret void } ;ARM-LABEL: : @@ -866,7 +866,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 entry: %a = alloca %struct.G, align 2 - call void @use_G(%struct.G* byval align 2 %a) + call void @use_G(%struct.G* byval(%struct.G) align 2 %a) ret void } ;ARM-LABEL: : @@ -887,7 +887,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 entry: %a = alloca %struct.G, align 4 - call void @use_G(%struct.G* byval align 4 %a) + call void @use_G(%struct.G* byval(%struct.G) align 4 %a) ret void } ;ARM-LABEL: : @@ -909,7 +909,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.G, align 8 - call void @use_G(%struct.G* byval align 8 %a) + call void @use_G(%struct.G* byval(%struct.G) align 8 %a) ret void } ;ARM-LABEL: : @@ -931,7 +931,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.G, align 16 - call void @use_G(%struct.G* byval align 16 %a) + call void @use_G(%struct.G* byval(%struct.G) align 16 %a) ret void } ;ARM-LABEL: : @@ -952,7 +952,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 entry: %a = alloca %struct.H, align 1 - call void @use_H(%struct.H* byval align 1 %a) + call void @use_H(%struct.H* byval(%struct.H) align 1 %a) ret void } ;ARM-LABEL: : @@ -973,7 +973,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 entry: %a = alloca %struct.H, align 2 - call void @use_H(%struct.H* byval align 2 %a) + call void @use_H(%struct.H* byval(%struct.H) align 2 %a) ret void } ;ARM-LABEL: : @@ -994,7 +994,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 entry: %a = alloca %struct.H, align 4 - call void @use_H(%struct.H* byval align 4 %a) + call void @use_H(%struct.H* byval(%struct.H) align 4 %a) ret void } ;ARM-LABEL: : @@ -1016,7 +1016,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.H, align 8 - call void @use_H(%struct.H* byval align 8 %a) + call void @use_H(%struct.H* byval(%struct.H) align 8 %a) ret void } ;ARM-LABEL: : @@ -1038,7 +1038,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.H, align 16 - call void @use_H(%struct.H* byval align 16 %a) + call void @use_H(%struct.H* byval(%struct.H) align 16 %a) ret void } ;ARM-LABEL: : @@ -1059,7 +1059,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 entry: %a = alloca %struct.I, align 1 - call void @use_I(%struct.I* byval align 1 %a) + call void @use_I(%struct.I* byval(%struct.I) align 1 %a) ret void } ;ARM-LABEL: : @@ -1080,7 +1080,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 entry: %a = alloca %struct.I, align 2 - call void @use_I(%struct.I* byval align 2 %a) + call void @use_I(%struct.I* byval(%struct.I) align 2 %a) ret void } ;ARM-LABEL: : @@ -1101,7 +1101,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 entry: %a = alloca %struct.I, align 4 - call void @use_I(%struct.I* byval align 4 %a) + call void @use_I(%struct.I* byval(%struct.I) align 4 %a) ret void } ;ARM-LABEL: : @@ -1123,7 +1123,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.I, align 8 - call void @use_I(%struct.I* byval align 8 %a) + call void @use_I(%struct.I* byval(%struct.I) align 8 %a) ret void } ;ARM-LABEL: : @@ -1145,7 +1145,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.I, align 16 - call void @use_I(%struct.I* byval align 16 %a) + call void @use_I(%struct.I* byval(%struct.I) align 16 %a) ret void } ;ARM-LABEL: : @@ -1170,7 +1170,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 entry: %a = alloca %struct.J, align 1 - call void @use_J(%struct.J* byval align 1 %a) + call void @use_J(%struct.J* byval(%struct.J) align 1 %a) ret void } ;ARM-LABEL: : @@ -1195,7 +1195,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 entry: %a = alloca %struct.J, align 2 - call void @use_J(%struct.J* byval align 2 %a) + call void @use_J(%struct.J* byval(%struct.J) align 2 %a) ret void } ;ARM-LABEL: : @@ -1220,7 +1220,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 entry: %a = alloca %struct.J, align 4 - call void @use_J(%struct.J* byval align 4 %a) + call void @use_J(%struct.J* byval(%struct.J) align 4 %a) ret void } ;ARM-LABEL: : @@ -1246,7 +1246,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.J, align 8 - call void @use_J(%struct.J* byval align 8 %a) + call void @use_J(%struct.J* byval(%struct.J) align 8 %a) ret void } ;ARM-LABEL: : @@ -1272,7 +1272,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.J, align 16 - call void @use_J(%struct.J* byval align 16 %a) + call void @use_J(%struct.J* byval(%struct.J) align 16 %a) ret void } ;ARM-LABEL: : @@ -1297,7 +1297,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 entry: %a = alloca %struct.K, align 1 - call void @use_K(%struct.K* byval align 1 %a) + call void @use_K(%struct.K* byval(%struct.K) align 1 %a) ret void } ;ARM-LABEL: : @@ -1322,7 +1322,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 entry: %a = alloca %struct.K, align 2 - call void @use_K(%struct.K* byval align 2 %a) + call void @use_K(%struct.K* byval(%struct.K) align 2 %a) ret void } ;ARM-LABEL: : @@ -1347,7 +1347,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 entry: %a = alloca %struct.K, align 4 - call void @use_K(%struct.K* byval align 4 %a) + call void @use_K(%struct.K* byval(%struct.K) align 4 %a) ret void } ;ARM-LABEL: : @@ -1373,7 +1373,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.K, align 8 - call void @use_K(%struct.K* byval align 8 %a) + call void @use_K(%struct.K* byval(%struct.K) align 8 %a) ret void } ;ARM-LABEL: : @@ -1399,7 +1399,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.K, align 16 - call void @use_K(%struct.K* byval align 16 %a) + call void @use_K(%struct.K* byval(%struct.K) align 16 %a) ret void } ;ARM-LABEL: : @@ -1424,7 +1424,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 entry: %a = alloca %struct.L, align 1 - call void @use_L(%struct.L* byval align 1 %a) + call void @use_L(%struct.L* byval(%struct.L) align 1 %a) ret void } ;ARM-LABEL: : @@ -1449,7 +1449,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 entry: %a = alloca %struct.L, align 2 - call void @use_L(%struct.L* byval align 2 %a) + call void @use_L(%struct.L* byval(%struct.L) align 2 %a) ret void } ;ARM-LABEL: : @@ -1474,7 +1474,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 entry: %a = alloca %struct.L, align 4 - call void @use_L(%struct.L* byval align 4 %a) + call void @use_L(%struct.L* byval(%struct.L) align 4 %a) ret void } ;ARM-LABEL: : @@ -1500,7 +1500,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.L, align 8 - call void @use_L(%struct.L* byval align 8 %a) + call void @use_L(%struct.L* byval(%struct.L) align 8 %a) ret void } ;ARM-LABEL: : @@ -1526,7 +1526,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.L, align 16 - call void @use_L(%struct.L* byval align 16 %a) + call void @use_L(%struct.L* byval(%struct.L) align 16 %a) ret void } ;V8MBASE-LABEL: : @@ -1537,7 +1537,7 @@ declare void @use_N(%struct.N* byval) ;V8MBASE-NOT: movw entry: %a = alloca %struct.M, align 1 - call void @use_M(%struct.M* byval align 1 %a) + call void @use_M(%struct.M* byval(%struct.M) align 1 %a) ret void } ;V8MBASE-LABEL: : @@ -1547,6 +1547,6 @@ declare void @use_N(%struct.N* byval) ;V8MBASE-NOT: b #{{[0-9]+}} entry: %a = alloca %struct.N, align 1 - call void @use_N(%struct.N* byval align 1 %a) + call void @use_N(%struct.N* byval(%struct.N) align 1 %a) ret void } diff --git a/test/CodeGen/BPF/byval.ll b/test/CodeGen/BPF/byval.ll index 2d2e8d289d6..b8ae806c092 100644 --- a/test/CodeGen/BPF/byval.ll +++ b/test/CodeGen/BPF/byval.ll @@ -17,11 +17,11 @@ entry: %arrayinit.start = getelementptr inbounds %struct.S, %struct.S* %.compoundliteral, i64 0, i32 0, i64 3 %scevgep4 = bitcast i32* %arrayinit.start to i8* call void @llvm.memset.p0i8.i64(i8* align 4 %scevgep4, i8 0, i64 28, i1 false) - call void @foo(i32 %a, %struct.S* byval align 8 %.compoundliteral) #3 + call void @foo(i32 %a, %struct.S* byval(%struct.S) align 8 %.compoundliteral) #3 ret void } -declare void @foo(i32, %struct.S* byval align 8) #1 +declare void @foo(i32, %struct.S* byval(%struct.S) align 8) #1 ; Function Attrs: nounwind declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) #3 diff --git a/test/CodeGen/Generic/2010-11-04-BigByval.ll b/test/CodeGen/Generic/2010-11-04-BigByval.ll index df2ca4c18a0..39b98a77552 100644 --- a/test/CodeGen/Generic/2010-11-04-BigByval.ll +++ b/test/CodeGen/Generic/2010-11-04-BigByval.ll @@ -3,9 +3,9 @@ %big = type [131072 x i8] -declare void @foo(%big* byval align 1) +declare void @foo(%big* byval(%big) align 1) -define void @bar(%big* byval align 1 %x) { - call void @foo(%big* byval align 1 %x) +define void @bar(%big* byval(%big) align 1 %x) { + call void @foo(%big* byval(%big) align 1 %x) ret void } diff --git a/test/CodeGen/Hexagon/bit-skip-byval.ll b/test/CodeGen/Hexagon/bit-skip-byval.ll index 9ee4014ae34..139726626c3 100644 --- a/test/CodeGen/Hexagon/bit-skip-byval.ll +++ b/test/CodeGen/Hexagon/bit-skip-byval.ll @@ -5,7 +5,7 @@ %struct.t0 = type { i32 } -define i32 @foo(%struct.t0* byval align 8 %s, i8 zeroext %t, i8 %u) #0 { +define i32 @foo(%struct.t0* byval(%struct.t0) align 8 %s, i8 zeroext %t, i8 %u) #0 { %a = zext i8 %u to i32 ret i32 %a } diff --git a/test/CodeGen/Hexagon/calling-conv.ll b/test/CodeGen/Hexagon/calling-conv.ll index bbe376b7f51..271a74d58f2 100644 --- a/test/CodeGen/Hexagon/calling-conv.ll +++ b/test/CodeGen/Hexagon/calling-conv.ll @@ -11,7 +11,7 @@ ; CHECK-TWO: memw(r29+#52) = r2 ; CHECK-THREE: memw(r29+#56) = r2 -define void @f0(%s.0* noalias nocapture sret %a0, i32 %a1, i8 zeroext %a2, %s.0* byval nocapture readnone align 8 %a3, %s.1* byval nocapture readnone align 8 %a4) #0 { +define void @f0(%s.0* noalias nocapture sret %a0, i32 %a1, i8 zeroext %a2, %s.0* byval(%s.0) nocapture readnone align 8 %a3, %s.1* byval(%s.1) nocapture readnone align 8 %a4) #0 { b0: %v0 = alloca %s.0, align 8 %v1 = load %s.0*, %s.0** @g0, align 4 @@ -19,7 +19,7 @@ b0: %v3 = add nsw i64 %v2, 1 %v4 = add nsw i32 %a1, 2 %v5 = add nsw i64 %v2, 3 - call void @f1(%s.0* sret %v0, i32 45, %s.0* byval align 8 %v1, %s.0* byval align 8 %v1, i8 zeroext %a2, i64 %v3, i32 %v4, i64 %v5, i8 zeroext %a2, i8 zeroext %a2, i8 zeroext %a2, i32 45) + call void @f1(%s.0* sret %v0, i32 45, %s.0* byval(%s.0) align 8 %v1, %s.0* byval(%s.0) align 8 %v1, i8 zeroext %a2, i64 %v3, i32 %v4, i64 %v5, i8 zeroext %a2, i8 zeroext %a2, i8 zeroext %a2, i32 45) %v6 = bitcast %s.0* %v0 to i32* store i32 20, i32* %v6, align 8 %v7 = bitcast %s.0* %a0 to i8* @@ -28,7 +28,7 @@ b0: ret void } -declare void @f1(%s.0* sret, i32, %s.0* byval align 8, %s.0* byval align 8, i8 zeroext, i64, i32, i64, i8 zeroext, i8 zeroext, i8 zeroext, i32) +declare void @f1(%s.0* sret, i32, %s.0* byval(%s.0) align 8, %s.0* byval(%s.0) align 8, i8 zeroext, i64, i32, i64, i8 zeroext, i8 zeroext, i8 zeroext, i32) ; Function Attrs: argmemonly nounwind declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture writeonly, i8* nocapture readonly, i32, i1) #1 diff --git a/test/CodeGen/Hexagon/cext-opt-negative-fi.mir b/test/CodeGen/Hexagon/cext-opt-negative-fi.mir index 0390ac292b7..63277e05cd1 100644 --- a/test/CodeGen/Hexagon/cext-opt-negative-fi.mir +++ b/test/CodeGen/Hexagon/cext-opt-negative-fi.mir @@ -22,7 +22,7 @@ %s.9 = type { i8, i8 } ; Function Attrs: nounwind optsize - define dso_local void @f0(%s.0* byval nocapture readonly align 8 %a0) local_unnamed_addr #0 { + define dso_local void @f0(%s.0* byval(%s.0) nocapture readonly align 8 %a0) local_unnamed_addr #0 { b0: %v0 = getelementptr inbounds %s.0, %s.0* %a0, i32 0, i32 10 %v1 = load i8, i8* %v0, align 8 diff --git a/test/CodeGen/Hexagon/inline-asm-error.ll b/test/CodeGen/Hexagon/inline-asm-error.ll index a8901a9d226..0a1e70830f5 100644 --- a/test/CodeGen/Hexagon/inline-asm-error.ll +++ b/test/CodeGen/Hexagon/inline-asm-error.ll @@ -6,7 +6,7 @@ %s.1 = type { %s.2 } %s.2 = type { i32, i8* } -define void @f0(%s.0* byval align 8 %a0) { +define void @f0(%s.0* byval(%s.0) align 8 %a0) { b0: call void asm sideeffect ".weak OFFSET_0;jump ##(OFFSET_0 + 0x14c15f0)", "*r"(%s.0* nonnull %a0), !srcloc !0 ret void diff --git a/test/CodeGen/Hexagon/struct_args_large.ll b/test/CodeGen/Hexagon/struct_args_large.ll index fb4780b0e5a..86550cce0cb 100644 --- a/test/CodeGen/Hexagon/struct_args_large.ll +++ b/test/CodeGen/Hexagon/struct_args_large.ll @@ -10,8 +10,8 @@ define void @foo() nounwind { entry: - call void @bar(%struct.large* byval @s2) + call void @bar(%struct.large* byval(%struct.large) @s2) ret void } -declare void @bar(%struct.large* byval) +declare void @bar(%struct.large* byval(%struct.large)) diff --git a/test/CodeGen/Hexagon/tail-dup-subreg-map.ll b/test/CodeGen/Hexagon/tail-dup-subreg-map.ll index f6110308011..6dd83a07bdc 100644 --- a/test/CodeGen/Hexagon/tail-dup-subreg-map.ll +++ b/test/CodeGen/Hexagon/tail-dup-subreg-map.ll @@ -14,7 +14,7 @@ target triple = "hexagon" declare hidden fastcc void @foo(%struct.0* noalias nocapture, i8 signext, i8 zeroext, i32, i64, i64) unnamed_addr #0 -define void @fred(%struct.0* noalias nocapture sret %agg.result, %struct.1* byval nocapture readonly align 8 %a, i32 %a0) #1 { +define void @fred(%struct.0* noalias nocapture sret %agg.result, %struct.1* byval(%struct.1) nocapture readonly align 8 %a, i32 %a0) #1 { entry: %0 = load i64, i64* undef, align 8 switch i32 %a0, label %if.else [ diff --git a/test/CodeGen/Hexagon/v6vect-locals1.ll b/test/CodeGen/Hexagon/v6vect-locals1.ll index c1ab52f50f7..8ae0c7b66ee 100644 --- a/test/CodeGen/Hexagon/v6vect-locals1.ll +++ b/test/CodeGen/Hexagon/v6vect-locals1.ll @@ -16,7 +16,7 @@ target triple = "hexagon" declare i32 @f0(i8* nocapture, ...) #0 ; Function Attrs: nounwind -define void @f1(%s.0* byval %a0, <16 x i32> %a1) #0 { +define void @f1(%s.0* byval(%s.0) %a0, <16 x i32> %a1) #0 { b0: %v0 = alloca <16 x i32>, align 64 store <16 x i32> %a1, <16 x i32>* %v0, align 64, !tbaa !0 @@ -30,7 +30,7 @@ b0: define i32 @f2() #0 { b0: %v0 = load <16 x i32>, <16 x i32>* @g2, align 64, !tbaa !0 - tail call void @f1(%s.0* byval @g1, <16 x i32> %v0) + tail call void @f1(%s.0* byval(%s.0) @g1, <16 x i32> %v0) ret i32 0 } diff --git a/test/CodeGen/Hexagon/vararg.ll b/test/CodeGen/Hexagon/vararg.ll index ed9029016af..c22da1a1163 100644 --- a/test/CodeGen/Hexagon/vararg.ll +++ b/test/CodeGen/Hexagon/vararg.ll @@ -82,7 +82,7 @@ declare void @llvm.va_end(i8*) #1 ; Function Attrs: nounwind define i32 @main() #0 { entry: - %call = tail call i32 (i32, ...) @foo(i32 undef, i32 2, %struct.AAA* byval align 4 @aaa, i32 4) + %call = tail call i32 (i32, ...) @foo(i32 undef, i32 2, %struct.AAA* byval(%struct.AAA) align 4 @aaa, i32 4) %call1 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i32 0, i32 0), i32 %call) #1 ret i32 %call } diff --git a/test/CodeGen/Hexagon/vararg_align_check.ll b/test/CodeGen/Hexagon/vararg_align_check.ll index 0152eec7020..647625f4ed1 100644 --- a/test/CodeGen/Hexagon/vararg_align_check.ll +++ b/test/CodeGen/Hexagon/vararg_align_check.ll @@ -29,7 +29,7 @@ @.str = private unnamed_addr constant [13 x i8] c"result = %d\0A\00", align 1 ; Function Attrs: nounwind -define i32 @foo(i32 %xx, %struct.BBB* byval align 8 %eee, ...) #0 { +define i32 @foo(i32 %xx, %struct.BBB* byval(%struct.BBB) align 8 %eee, ...) #0 { entry: %xx.addr = alloca i32, align 4 %ap = alloca [1 x %struct.__va_list_tag], align 8 @@ -169,7 +169,7 @@ entry: store i32 0, i32* %retval store i64 1000000, i64* %m, align 8 %0 = load i64, i64* %m, align 8 - %call = call i32 (i32, %struct.BBB*, ...) @foo(i32 1, %struct.BBB* byval align 8 bitcast ({ i8, i64, i32, [4 x i8] }* @ddd to %struct.BBB*), i64 %0, %struct.AAA* byval align 4 @aaa, i32 4) + %call = call i32 (i32, %struct.BBB*, ...) @foo(i32 1, %struct.BBB* byval(%struct.BBB) align 8 bitcast ({ i8, i64, i32, [4 x i8] }* @ddd to %struct.BBB*), i64 %0, %struct.AAA* byval(%struct.AAA) align 4 @aaa, i32 4) store i32 %call, i32* %x, align 4 %1 = load i32, i32* %x, align 4 %call1 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i32 0, i32 0), i32 %1) diff --git a/test/CodeGen/Hexagon/vararg_double_onstack.ll b/test/CodeGen/Hexagon/vararg_double_onstack.ll index 0a755e57fe0..613fce8bb0e 100644 --- a/test/CodeGen/Hexagon/vararg_double_onstack.ll +++ b/test/CodeGen/Hexagon/vararg_double_onstack.ll @@ -197,7 +197,7 @@ entry: store i64 1000000, i64* %y, align 8 %0 = load i64, i64* %y, align 8 %1 = load i64, i64* %y, align 8 - %call = call i32 (i32, i32, i32, i32, i32, ...) @foo(i32 1, i32 2, i32 3, i32 4, i32 5, i64 %0, %struct.AAA* byval align 4 @aaa, i32 4, i64 %1) + %call = call i32 (i32, i32, i32, i32, i32, ...) @foo(i32 1, i32 2, i32 3, i32 4, i32 5, i64 %0, %struct.AAA* byval(%struct.AAA) align 4 @aaa, i32 4, i64 %1) store i32 %call, i32* %x, align 4 %2 = load i32, i32* %x, align 4 %call1 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i32 0, i32 0), i32 %2) diff --git a/test/CodeGen/Hexagon/vararg_named.ll b/test/CodeGen/Hexagon/vararg_named.ll index 5a357284caf..413dc2e1d5d 100644 --- a/test/CodeGen/Hexagon/vararg_named.ll +++ b/test/CodeGen/Hexagon/vararg_named.ll @@ -31,7 +31,7 @@ @.str = private unnamed_addr constant [13 x i8] c"result = %d\0A\00", align 1 ; Function Attrs: nounwind -define i32 @foo(i32 %xx, i32 %z, i32 %m, %struct.AAA* byval align 4 %bbb, %struct.AAA* byval align 4 %GGG, ...) #0 { +define i32 @foo(i32 %xx, i32 %z, i32 %m, %struct.AAA* byval(%struct.AAA) align 4 %bbb, %struct.AAA* byval(%struct.AAA) align 4 %GGG, ...) #0 { entry: %xx.addr = alloca i32, align 4 %z.addr = alloca i32, align 4 @@ -194,7 +194,7 @@ entry: %retval = alloca i32, align 4 %x = alloca i32, align 4 store i32 0, i32* %retval - %call = call i32 (i32, i32, i32, %struct.AAA*, %struct.AAA*, ...) @foo(i32 1, i32 3, i32 5, %struct.AAA* byval align 4 @aaa, %struct.AAA* byval align 4 @fff, i32 2, %struct.AAA* byval align 4 @xxx, %struct.AAA* byval align 4 @yyy, %struct.AAA* byval align 4 @ccc, i32 4) + %call = call i32 (i32, i32, i32, %struct.AAA*, %struct.AAA*, ...) @foo(i32 1, i32 3, i32 5, %struct.AAA* byval(%struct.AAA) align 4 @aaa, %struct.AAA* byval(%struct.AAA) align 4 @fff, i32 2, %struct.AAA* byval(%struct.AAA) align 4 @xxx, %struct.AAA* byval(%struct.AAA) align 4 @yyy, %struct.AAA* byval(%struct.AAA) align 4 @ccc, i32 4) store i32 %call, i32* %x, align 4 %0 = load i32, i32* %x, align 4 %call1 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i32 0, i32 0), i32 %0) diff --git a/test/CodeGen/MIR/X86/fixed-stack-di.mir b/test/CodeGen/MIR/X86/fixed-stack-di.mir index 0add9f1c793..5bdece87aa8 100644 --- a/test/CodeGen/MIR/X86/fixed-stack-di.mir +++ b/test/CodeGen/MIR/X86/fixed-stack-di.mir @@ -8,7 +8,7 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) #0 - define hidden void @foo(i32* byval %dstRect) { + define hidden void @foo(i32* byval(i32) %dstRect) { entry: call void @llvm.dbg.declare(metadata i32* %dstRect, metadata !3, metadata !DIExpression()), !dbg !5 unreachable diff --git a/test/CodeGen/MSP430/byval.ll b/test/CodeGen/MSP430/byval.ll index 838e883d4be..5faeba5f7c6 100644 --- a/test/CodeGen/MSP430/byval.ll +++ b/test/CodeGen/MSP430/byval.ll @@ -6,7 +6,7 @@ target triple = "msp430---elf" %struct.Foo = type { i16, i16, i16 } @foo = global %struct.Foo { i16 1, i16 2, i16 3 }, align 2 -define i16 @callee(%struct.Foo* byval %f) nounwind { +define i16 @callee(%struct.Foo* byval(%struct.Foo) %f) nounwind { entry: ; CHECK-LABEL: callee: ; CHECK: mov 2(r1), r12 @@ -21,6 +21,6 @@ entry: ; CHECK: mov &foo+4, 4(r1) ; CHECK-NEXT: mov &foo+2, 2(r1) ; CHECK-NEXT: mov &foo, 0(r1) - %call = call i16 @callee(%struct.Foo* byval @foo) + %call = call i16 @callee(%struct.Foo* byval(%struct.Foo) @foo) ret void } diff --git a/test/CodeGen/MSP430/spill-to-stack.ll b/test/CodeGen/MSP430/spill-to-stack.ll index d925bc91b72..549e30c43a2 100644 --- a/test/CodeGen/MSP430/spill-to-stack.ll +++ b/test/CodeGen/MSP430/spill-to-stack.ll @@ -2,7 +2,7 @@ %VeryLarge = type { i8, i32, i32, i32, i32, i32, i32, i32, i32, i32 } ; intentionally cause a spill -define void @inc(%VeryLarge* byval align 1 %s) { +define void @inc(%VeryLarge* byval(%VeryLarge) align 1 %s) { entry: %p0 = getelementptr inbounds %VeryLarge, %VeryLarge* %s, i32 0, i32 0 %0 = load i8, i8* %p0 diff --git a/test/CodeGen/Mips/cconv/byval.ll b/test/CodeGen/Mips/cconv/byval.ll index e3e7eccd262..180563d1ec9 100644 --- a/test/CodeGen/Mips/cconv/byval.ll +++ b/test/CodeGen/Mips/cconv/byval.ll @@ -152,11 +152,11 @@ define dso_local void @g() #0 { ; N64-NEXT: daddu $sp, $sp, $1 entry: %a = alloca %struct.S1, align 4 - call void @f2(%struct.S1* byval align 4 %a) + call void @f2(%struct.S1* byval(%struct.S1) align 4 %a) ret void } -declare dso_local void @f2(%struct.S1* byval align 4) #1 +declare dso_local void @f2(%struct.S1* byval(%struct.S1) align 4) #1 ; O32-SDAG-LABEL: Initial selection DAG: %bb.0 'g2:entry' ; O32-SDAG: t{{.*}}: ch,glue = callseq_start t{{.*}}, TargetConstant:i32<{{.*}}> @@ -348,7 +348,7 @@ entry: %1 = bitcast %struct.S1* %byval-temp to i8* %2 = bitcast %struct.S1* %0 to i8* call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %1, i8* align 1 %2, i32 65520, i1 false) - call void @f2(%struct.S1* byval align 4 %byval-temp) + call void @f2(%struct.S1* byval(%struct.S1) align 4 %byval-temp) ret void } diff --git a/test/CodeGen/Mips/cprestore.ll b/test/CodeGen/Mips/cprestore.ll index a618b675c55..b4489b6e221 100644 --- a/test/CodeGen/Mips/cprestore.ll +++ b/test/CodeGen/Mips/cprestore.ll @@ -13,8 +13,8 @@ define void @foo2() nounwind { entry: %s = alloca %struct.S, align 4 - call void @foo1(%struct.S* byval %s) + call void @foo1(%struct.S* byval(%struct.S) %s) ret void } -declare void @foo1(%struct.S* byval) +declare void @foo1(%struct.S* byval(%struct.S)) diff --git a/test/CodeGen/Mips/fastcc_byval.ll b/test/CodeGen/Mips/fastcc_byval.ll index 4a55ac7422c..15e2a2b44ae 100644 --- a/test/CodeGen/Mips/fastcc_byval.ll +++ b/test/CodeGen/Mips/fastcc_byval.ll @@ -5,9 +5,9 @@ %struct.str = type { i32, i32, [3 x i32*] } -declare fastcc void @_Z1F3str(%struct.str* noalias nocapture sret %agg.result, %struct.str* byval nocapture readonly align 4 %s) +declare fastcc void @_Z1F3str(%struct.str* noalias nocapture sret %agg.result, %struct.str* byval(%struct.str) nocapture readonly align 4 %s) -define i32 @_Z1g3str(%struct.str* byval nocapture readonly align 4 %s) { +define i32 @_Z1g3str(%struct.str* byval(%struct.str) nocapture readonly align 4 %s) { ; CHECK-LABEL: _Z1g3str: ; CHECK: sw $7, [[OFFSET:[0-9]+]]($sp) ; CHECK: lw ${{[0-9]+}}, [[OFFSET]]($sp) @@ -15,7 +15,7 @@ entry: %ref.tmp = alloca %struct.str, align 4 %0 = bitcast %struct.str* %ref.tmp to i8* call void @llvm.lifetime.start.p0i8(i64 20, i8* nonnull %0) - call fastcc void @_Z1F3str(%struct.str* nonnull sret %ref.tmp, %struct.str* byval nonnull align 4 %s) + call fastcc void @_Z1F3str(%struct.str* nonnull sret %ref.tmp, %struct.str* byval(%struct.str) nonnull align 4 %s) %cl.sroa.3.0..sroa_idx2 = getelementptr inbounds %struct.str, %struct.str* %ref.tmp, i32 0, i32 1 %cl.sroa.3.0.copyload = load i32, i32* %cl.sroa.3.0..sroa_idx2, align 4 call void @llvm.lifetime.end.p0i8(i64 20, i8* nonnull %0) diff --git a/test/CodeGen/Mips/largeimmprinting.ll b/test/CodeGen/Mips/largeimmprinting.ll index 6460260f67b..1d5b9c47b7d 100644 --- a/test/CodeGen/Mips/largeimmprinting.ll +++ b/test/CodeGen/Mips/largeimmprinting.ll @@ -27,10 +27,10 @@ entry: %agg.tmp = alloca %struct.S1, align 1 %tmp = getelementptr inbounds %struct.S1, %struct.S1* %agg.tmp, i32 0, i32 0, i32 0 call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 %tmp, i8* align 1 getelementptr inbounds (%struct.S1, %struct.S1* @s1, i32 0, i32 0, i32 0), i32 65536, i1 false) - call void @f2(%struct.S1* byval %agg.tmp) nounwind + call void @f2(%struct.S1* byval(%struct.S1) %agg.tmp) nounwind ret void } -declare void @f2(%struct.S1* byval) +declare void @f2(%struct.S1* byval(%struct.S1)) declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i1) nounwind diff --git a/test/CodeGen/Mips/load-store-left-right.ll b/test/CodeGen/Mips/load-store-left-right.ll index 69ad307df7a..8da37e7a02b 100644 --- a/test/CodeGen/Mips/load-store-left-right.ll +++ b/test/CodeGen/Mips/load-store-left-right.ll @@ -535,8 +535,8 @@ entry: ; MIPS64R6: ld $[[SPTR:[0-9]+]], %got_disp(arr)( - tail call void @extern_func([7 x i8]* byval @arr) nounwind + tail call void @extern_func([7 x i8]* byval([7 x i8]) @arr) nounwind ret void } -declare void @extern_func([7 x i8]* byval) +declare void @extern_func([7 x i8]* byval([7 x i8])) diff --git a/test/CodeGen/Mips/o32_cc_byval.ll b/test/CodeGen/Mips/o32_cc_byval.ll index d9951ebeaf3..de17a1e502f 100644 --- a/test/CodeGen/Mips/o32_cc_byval.ll +++ b/test/CodeGen/Mips/o32_cc_byval.ll @@ -81,21 +81,21 @@ define void @f1() nounwind { ; CHECK-NEXT: addiu $sp, $sp, 64 entry: %agg.tmp10 = alloca %struct.S3, align 4 - call void @callee1(float 2.000000e+01, %struct.S1* byval bitcast (%0* @f1.s1 to %struct.S1*)) nounwind - call void @callee2(%struct.S2* byval @f1.s2) nounwind + call void @callee1(float 2.000000e+01, %struct.S1* byval(%struct.S1) bitcast (%0* @f1.s1 to %struct.S1*)) nounwind + call void @callee2(%struct.S2* byval(%struct.S2) @f1.s2) nounwind %tmp11 = getelementptr inbounds %struct.S3, %struct.S3* %agg.tmp10, i32 0, i32 0 store i8 11, i8* %tmp11, align 4 - call void @callee3(float 2.100000e+01, %struct.S3* byval %agg.tmp10, %struct.S1* byval bitcast (%0* @f1.s1 to %struct.S1*)) nounwind + call void @callee3(float 2.100000e+01, %struct.S3* byval(%struct.S3) %agg.tmp10, %struct.S1* byval(%struct.S1) bitcast (%0* @f1.s1 to %struct.S1*)) nounwind ret void } -declare void @callee1(float, %struct.S1* byval) +declare void @callee1(float, %struct.S1* byval(%struct.S1)) -declare void @callee2(%struct.S2* byval) +declare void @callee2(%struct.S2* byval(%struct.S2)) -declare void @callee3(float, %struct.S3* byval, %struct.S1* byval) +declare void @callee3(float, %struct.S3* byval(%struct.S3), %struct.S1* byval(%struct.S1)) -define void @f2(float %f, %struct.S1* nocapture byval %s1) nounwind { +define void @f2(float %f, %struct.S1* nocapture byval(%struct.S1) %s1) nounwind { ; CHECK-LABEL: f2: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lui $2, %hi(_gp_disp) @@ -144,7 +144,7 @@ entry: declare void @callee4(i32, double, i64, i32, i16 signext, i8 signext, float) -define void @f3(%struct.S2* nocapture byval %s2) nounwind { +define void @f3(%struct.S2* nocapture byval(%struct.S2) %s2) nounwind { ; CHECK-LABEL: f3: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lui $2, %hi(_gp_disp) @@ -184,7 +184,7 @@ entry: ret void } -define void @f4(float %f, %struct.S3* nocapture byval %s3, %struct.S1* nocapture byval %s1) nounwind { +define void @f4(float %f, %struct.S3* nocapture byval(%struct.S3) %s3, %struct.S1* nocapture byval(%struct.S1) %s1) nounwind { ; CHECK-LABEL: f4: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lui $2, %hi(_gp_disp) @@ -230,7 +230,7 @@ entry: %struct.S4 = type { [4 x i32] } -define void @f5(i64 %a0, %struct.S4* nocapture byval %a1) nounwind { +define void @f5(i64 %a0, %struct.S4* nocapture byval(%struct.S4) %a1) nounwind { ; CHECK-LABEL: f5: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lui $2, %hi(_gp_disp) @@ -252,8 +252,8 @@ define void @f5(i64 %a0, %struct.S4* nocapture byval %a1) nounwind { ; CHECK-NEXT: jr $ra ; CHECK-NEXT: addiu $sp, $sp, 32 entry: - tail call void @f6(%struct.S4* byval %a1, i64 %a0) nounwind + tail call void @f6(%struct.S4* byval(%struct.S4) %a1, i64 %a0) nounwind ret void } -declare void @f6(%struct.S4* nocapture byval, i64) +declare void @f6(%struct.S4* nocapture byval(%struct.S4), i64) diff --git a/test/CodeGen/Mips/tailcall/tailcall.ll b/test/CodeGen/Mips/tailcall/tailcall.ll index 50759b2104e..aaa596c4258 100644 --- a/test/CodeGen/Mips/tailcall/tailcall.ll +++ b/test/CodeGen/Mips/tailcall/tailcall.ll @@ -192,7 +192,7 @@ entry: @gs1 = external global %struct.S -declare i32 @callee9(%struct.S* byval) +declare i32 @callee9(%struct.S* byval(%struct.S)) define i32 @caller9_0() nounwind { entry: @@ -223,7 +223,7 @@ entry: ; PIC64R6: jalrc $25 ; PIC16: jalrc - %call = tail call i32 @callee9(%struct.S* byval @gs1) nounwind + %call = tail call i32 @callee9(%struct.S* byval(%struct.S) @gs1) nounwind ret i32 %call } @@ -246,7 +246,7 @@ entry: ret i32 %call } -declare i32 @callee11(%struct.S* byval) +declare i32 @callee11(%struct.S* byval(%struct.S)) define i32 @caller11() nounwind noinline { entry: @@ -261,7 +261,7 @@ entry: ; PIC64R6: jalrc $25 ; PIC16: jalrc - %call = tail call i32 @callee11(%struct.S* byval @gs1) nounwind + %call = tail call i32 @callee11(%struct.S* byval(%struct.S) @gs1) nounwind ret i32 %call } @@ -269,7 +269,7 @@ declare i32 @callee12() declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i1) nounwind -define i32 @caller12(%struct.S* nocapture byval %a0) nounwind { +define i32 @caller12(%struct.S* nocapture byval(%struct.S) %a0) nounwind { entry: ; ALL-LABEL: caller12: ; PIC32: jalr $25 diff --git a/test/CodeGen/Mips/unalignedload.ll b/test/CodeGen/Mips/unalignedload.ll index 9a4a0456a7e..14a94313c1c 100644 --- a/test/CodeGen/Mips/unalignedload.ll +++ b/test/CodeGen/Mips/unalignedload.ll @@ -30,7 +30,7 @@ entry: ; MIPS32R6-DAG: lhu $[[PART1:[0-9]+]], 2($[[R0]]) - tail call void @foo2(%struct.S1* byval getelementptr inbounds (%struct.S2, %struct.S2* @s2, i32 0, i32 1)) nounwind + tail call void @foo2(%struct.S1* byval(%struct.S1) getelementptr inbounds (%struct.S2, %struct.S2* @s2, i32 0, i32 1)) nounwind ret void } @@ -76,10 +76,10 @@ entry: ; MIPS32R6-EB-DAG: sll $[[T3:[0-9]+]], $[[T1]], 8 ; MIPS32R6-EB-DAG: or $5, $[[T2]], $[[T3]] - tail call void @foo4(%struct.S4* byval @s4) nounwind + tail call void @foo4(%struct.S4* byval(%struct.S4) @s4) nounwind ret void } -declare void @foo2(%struct.S1* byval) +declare void @foo2(%struct.S1* byval(%struct.S1)) -declare void @foo4(%struct.S4* byval) +declare void @foo4(%struct.S4* byval(%struct.S4)) diff --git a/test/CodeGen/NVPTX/bug21465.ll b/test/CodeGen/NVPTX/bug21465.ll index 9a221988d90..03cde33f31c 100644 --- a/test/CodeGen/NVPTX/bug21465.ll +++ b/test/CodeGen/NVPTX/bug21465.ll @@ -7,7 +7,7 @@ target triple = "nvptx64-unknown-unknown" %struct.S = type { i32, i32 } ; Function Attrs: nounwind -define void @_Z11TakesStruct1SPi(%struct.S* byval nocapture readonly %input, i32* nocapture %output) #0 { +define void @_Z11TakesStruct1SPi(%struct.S* byval(%struct.S) nocapture readonly %input, i32* nocapture %output) #0 { entry: ; CHECK-LABEL: @_Z11TakesStruct1SPi ; PTX-LABEL: .visible .entry _Z11TakesStruct1SPi( diff --git a/test/CodeGen/NVPTX/lower-kernel-ptr-arg.ll b/test/CodeGen/NVPTX/lower-kernel-ptr-arg.ll index bdb1d3c546c..3430f1eecad 100644 --- a/test/CodeGen/NVPTX/lower-kernel-ptr-arg.ll +++ b/test/CodeGen/NVPTX/lower-kernel-ptr-arg.ll @@ -28,7 +28,7 @@ define void @kernel2(float addrspace(1)* %input, float addrspace(1)* %output) { %struct.S = type { i32*, i32* } -define void @ptr_in_byval_kernel(%struct.S* byval %input, i32* %output) { +define void @ptr_in_byval_kernel(%struct.S* byval(%struct.S) %input, i32* %output) { ; CHECK-LABEL: .visible .entry ptr_in_byval_kernel( ; CHECK: ld.param.u64 %[[optr:rd.*]], [ptr_in_byval_kernel_param_1] ; CHECK: cvta.to.global.u64 %[[optr_g:.*]], %[[optr]]; @@ -46,7 +46,7 @@ define void @ptr_in_byval_kernel(%struct.S* byval %input, i32* %output) { ; Regular functions lower byval arguments differently. We need to make ; sure that we're loading byval argument data using [symbol+offset]. ; There's also no assumption that all pointers within are in global space. -define void @ptr_in_byval_func(%struct.S* byval %input, i32* %output) { +define void @ptr_in_byval_func(%struct.S* byval(%struct.S) %input, i32* %output) { ; CHECK-LABEL: .visible .func ptr_in_byval_func( ; CHECK: ld.param.u64 %[[optr:rd.*]], [ptr_in_byval_func_param_1] ; CHECK: ld.param.u64 %[[iptr:rd.*]], [ptr_in_byval_func_param_0+8] diff --git a/test/CodeGen/NVPTX/param-align.ll b/test/CodeGen/NVPTX/param-align.ll index 75b6917265e..b5b27770c45 100644 --- a/test/CodeGen/NVPTX/param-align.ll +++ b/test/CodeGen/NVPTX/param-align.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s ;;; Need 4-byte alignment on float* passed byval -define ptx_device void @t1(float* byval %x) { +define ptx_device void @t1(float* byval(float) %x) { ; CHECK: .func t1 ; CHECK: .param .align 4 .b8 t1_param_0[4] ret void @@ -9,7 +9,7 @@ define ptx_device void @t1(float* byval %x) { ;;; Need 8-byte alignment on double* passed byval -define ptx_device void @t2(double* byval %x) { +define ptx_device void @t2(double* byval(double) %x) { ; CHECK: .func t2 ; CHECK: .param .align 8 .b8 t2_param_0[8] ret void @@ -18,7 +18,7 @@ define ptx_device void @t2(double* byval %x) { ;;; Need 4-byte alignment on float2* passed byval %struct.float2 = type { float, float } -define ptx_device void @t3(%struct.float2* byval %x) { +define ptx_device void @t3(%struct.float2* byval(%struct.float2) %x) { ; CHECK: .func t3 ; CHECK: .param .align 4 .b8 t3_param_0[8] ret void @@ -26,19 +26,19 @@ define ptx_device void @t3(%struct.float2* byval %x) { ;;; Need at least 4-byte alignment in order to avoid miscompilation by ;;; ptxas for sm_50+ -define ptx_device void @t4(i8* byval %x) { +define ptx_device void @t4(i8* byval(i8) %x) { ; CHECK: .func t4 ; CHECK: .param .align 4 .b8 t4_param_0[1] ret void } ;;; Make sure we adjust alignment at the call site as well. -define ptx_device void @t5(i8* align 2 byval %x) { +define ptx_device void @t5(i8* align 2 byval(i8) %x) { ; CHECK: .func t5 ; CHECK: .param .align 4 .b8 t5_param_0[1] ; CHECK: { ; CHECK: .param .align 4 .b8 param0[1]; ; CHECK: call.uni - call void @t4(i8* byval %x) + call void @t4(i8* byval(i8) %x) ret void } diff --git a/test/CodeGen/PowerPC/MMO-flags-assertion.ll b/test/CodeGen/PowerPC/MMO-flags-assertion.ll index 64fa85a8195..156214f419b 100644 --- a/test/CodeGen/PowerPC/MMO-flags-assertion.ll +++ b/test/CodeGen/PowerPC/MMO-flags-assertion.ll @@ -3,7 +3,7 @@ ; void llvm::MachineMemOperand::refineAlignment(const llvm::MachineMemOperand*): ; Assertion `MMO->getFlags() == getFlags() && "Flags mismatch !"' failed. -declare void @_Z3fn11F(%class.F* byval align 8) local_unnamed_addr +declare void @_Z3fn11F(%class.F* byval(%class.F) align 8) local_unnamed_addr declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i1) declare signext i32 @_ZN1F11isGlobalRegEv(%class.F*) local_unnamed_addr declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) @@ -12,9 +12,9 @@ declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) %class.F = type { i32, i64, i8, [64 x i8], i8, i32* } -define signext i32 @_Z29EmitOMPAtomicSimpleUpdateExpr1F(%class.F* byval align 8 %p1) local_unnamed_addr { +define signext i32 @_Z29EmitOMPAtomicSimpleUpdateExpr1F(%class.F* byval(%class.F) align 8 %p1) local_unnamed_addr { entry: - call void @_Z3fn11F(%class.F* byval nonnull align 8 %p1) + call void @_Z3fn11F(%class.F* byval(%class.F) nonnull align 8 %p1) %call = call signext i32 @_ZN1F11isGlobalRegEv(%class.F* nonnull %p1) ret i32 %call } @@ -29,7 +29,7 @@ entry: %1 = bitcast %class.F* %agg.tmp1 to i8* call void @llvm.lifetime.start.p0i8(i64 96, i8* nonnull %1) call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 nonnull %1, i8* align 8 nonnull %0, i64 96, i1 false) - call void @_Z3fn11F(%class.F* byval nonnull align 8 %XLValue) + call void @_Z3fn11F(%class.F* byval(%class.F) nonnull align 8 %XLValue) %call.i = call signext i32 @_ZN1F11isGlobalRegEv(%class.F* nonnull %agg.tmp1) call void @llvm.lifetime.end.p0i8(i64 96, i8* nonnull %1) call void @llvm.lifetime.end.p0i8(i64 96, i8* nonnull %0) diff --git a/test/CodeGen/PowerPC/a2-fp-basic.ll b/test/CodeGen/PowerPC/a2-fp-basic.ll index e4a7c537d74..1bb75c95413 100644 --- a/test/CodeGen/PowerPC/a2-fp-basic.ll +++ b/test/CodeGen/PowerPC/a2-fp-basic.ll @@ -2,7 +2,7 @@ %0 = type { double, double } -define void @maybe_an_fma(%0* sret %agg.result, %0* byval %a, %0* byval %b, %0* byval %c) nounwind { +define void @maybe_an_fma(%0* sret %agg.result, %0* byval(%0) %a, %0* byval(%0) %b, %0* byval(%0) %c) nounwind { entry: %a.realp = getelementptr inbounds %0, %0* %a, i32 0, i32 0 %a.real = load double, double* %a.realp diff --git a/test/CodeGen/PowerPC/anon_aggr.ll b/test/CodeGen/PowerPC/anon_aggr.ll index cc07c484365..ca29ad889e2 100644 --- a/test/CodeGen/PowerPC/anon_aggr.ll +++ b/test/CodeGen/PowerPC/anon_aggr.ll @@ -25,7 +25,7 @@ unequal: ; CHECK: ld 3, -[[OFFSET1]](1) ; CHECK: ld 3, -[[OFFSET2]](1) -define i8* @func2({ i64, i8* } %array1, %tarray* byval %array2) { +define i8* @func2({ i64, i8* } %array1, %tarray* byval(%tarray) %array2) { entry: %array1_ptr = extractvalue {i64, i8* } %array1, 1 %tmp = getelementptr inbounds %tarray, %tarray* %array2, i32 0, i32 1 @@ -46,7 +46,7 @@ unequal: ; CHECK: ld 3, -[[OFFSET1]](1) ; CHECK: ld 3, -[[OFFSET2]](1) -define i8* @func3({ i64, i8* }* byval %array1, %tarray* byval %array2) { +define i8* @func3({ i64, i8* }* byval({ i64, i8* }) %array1, %tarray* byval(%tarray) %array2) { entry: %tmp1 = getelementptr inbounds { i64, i8* }, { i64, i8* }* %array1, i32 0, i32 1 %array1_ptr = load i8*, i8** %tmp1 @@ -69,7 +69,7 @@ unequal: define i8* @func4(i64 %p1, i64 %p2, i64 %p3, i64 %p4, i64 %p5, i64 %p6, i64 %p7, i64 %p8, - { i64, i8* } %array1, %tarray* byval %array2) { + { i64, i8* } %array1, %tarray* byval(%tarray) %array2) { entry: %array1_ptr = extractvalue {i64, i8* } %array1, 1 %tmp = getelementptr inbounds %tarray, %tarray* %array2, i32 0, i32 1 diff --git a/test/CodeGen/PowerPC/byval-agg-info.ll b/test/CodeGen/PowerPC/byval-agg-info.ll index 21aa5821c88..d78ea09d37e 100644 --- a/test/CodeGen/PowerPC/byval-agg-info.ll +++ b/test/CodeGen/PowerPC/byval-agg-info.ll @@ -5,7 +5,7 @@ target triple = "powerpc64-unknown-linux-gnu" %struct.anon = type { i32, i32 } declare void @foo(%struct.anon* %v) -define void @test(i32 %a, i32 %b, %struct.anon* byval nocapture %v) { +define void @test(i32 %a, i32 %b, %struct.anon* byval(%struct.anon) nocapture %v) { entry: call void @foo(%struct.anon* %v) ret void diff --git a/test/CodeGen/PowerPC/byval-aliased.ll b/test/CodeGen/PowerPC/byval-aliased.ll index 8c8cbc0e71d..18d748defa1 100644 --- a/test/CodeGen/PowerPC/byval-aliased.ll +++ b/test/CodeGen/PowerPC/byval-aliased.ll @@ -1,11 +1,11 @@ ; RUN: llc -verify-machineinstrs -mcpu=ppc64 -ppc-asm-full-reg-names < %s | FileCheck %s target datalayout = "E-m:o-p:32:32-f64:32:64-n32" target triple = "powerpc-unknown-linux-gnu" - + %struct.sm = type { i8, i8 } - + ; Function Attrs: nounwind ssp -define void @foo(%struct.sm* byval %s) #0 { +define void @foo(%struct.sm* byval(%struct.sm) %s) #0 { entry: %a = getelementptr inbounds %struct.sm, %struct.sm* %s, i32 0, i32 0 %0 = load i8, i8* %a, align 1 @@ -13,7 +13,7 @@ entry: %add = add nuw nsw i32 %conv2, 3 %conv1 = trunc i32 %add to i8 store i8 %conv1, i8* %a, align 1 - call void @bar(%struct.sm* byval %s, %struct.sm* byval %s) #1 + call void @bar(%struct.sm* byval(%struct.sm) %s, %struct.sm* byval(%struct.sm) %s) #1 ret void } @@ -22,9 +22,9 @@ entry: ; CHECK: lhz r4, [[OFF]]({{r[3?1]}}) ; CHECK: bl bar ; CHECK: blr - -declare void @bar(%struct.sm* byval, %struct.sm* byval) - + +declare void @bar(%struct.sm* byval(%struct.sm), %struct.sm* byval(%struct.sm)) + attributes #0 = { nounwind ssp } attributes #1 = { nounwind } - + diff --git a/test/CodeGen/PowerPC/dyn-alloca-aligned.ll b/test/CodeGen/PowerPC/dyn-alloca-aligned.ll index e0f28475d8f..bb6c47a7e19 100644 --- a/test/CodeGen/PowerPC/dyn-alloca-aligned.ll +++ b/test/CodeGen/PowerPC/dyn-alloca-aligned.ll @@ -6,7 +6,7 @@ target triple = "powerpc64-unknown-linux-gnu" declare void @bar(i32*, i32*) #0 -define void @goo(%struct.s* byval nocapture readonly %a, i32 signext %n) #0 { +define void @goo(%struct.s* byval(%struct.s) nocapture readonly %a, i32 signext %n) #0 { entry: %0 = zext i32 %n to i64 %vla = alloca i32, i64 %0, align 128 diff --git a/test/CodeGen/PowerPC/emptystruct.ll b/test/CodeGen/PowerPC/emptystruct.ll index b0e41ec29e4..aaa15ab13b6 100644 --- a/test/CodeGen/PowerPC/emptystruct.ll +++ b/test/CodeGen/PowerPC/emptystruct.ll @@ -3,8 +3,8 @@ ; This tests correct handling of empty aggregate parameters and return values. ; An empty parameter passed by value does not consume a protocol register or ; a parameter save area doubleword. An empty parameter passed by reference -; is treated as any other pointer parameter. An empty aggregate return value -; is treated as any other aggregate return value, passed via address as a +; is treated as any other pointer parameter. An empty aggregate return value +; is treated as any other aggregate return value, passed via address as a ; hidden parameter in GPR3. In this example, GPR3 contains the return value ; address, GPR4 contains the address of e2, and e1 and e3 are not passed or ; received. @@ -14,7 +14,7 @@ target triple = "powerpc64-unknown-linux-gnu" %struct.empty = type {} -define void @callee(%struct.empty* noalias sret %agg.result, %struct.empty* byval %a1, %struct.empty* %a2, %struct.empty* byval %a3) nounwind { +define void @callee(%struct.empty* noalias sret %agg.result, %struct.empty* byval(%struct.empty) %a1, %struct.empty* %a2, %struct.empty* byval(%struct.empty) %a3) nounwind { entry: %a2.addr = alloca %struct.empty*, align 8 store %struct.empty* %a2, %struct.empty** %a2.addr, align 8 @@ -38,7 +38,7 @@ entry: %e1 = alloca %struct.empty, align 1 %e2 = alloca %struct.empty, align 1 %e3 = alloca %struct.empty, align 1 - call void @callee(%struct.empty* sret %agg.result, %struct.empty* byval %e1, %struct.empty* %e2, %struct.empty* byval %e3) + call void @callee(%struct.empty* sret %agg.result, %struct.empty* byval(%struct.empty) %e1, %struct.empty* %e2, %struct.empty* byval(%struct.empty) %e3) ret void } diff --git a/test/CodeGen/PowerPC/f128-aggregates.ll b/test/CodeGen/PowerPC/f128-aggregates.ll index 2dacdabd2de..0a23f7ad460 100644 --- a/test/CodeGen/PowerPC/f128-aggregates.ll +++ b/test/CodeGen/PowerPC/f128-aggregates.ll @@ -115,7 +115,7 @@ entry: ; Since we can only pass a max of 8 float128 value in VSX registers, ensure we ; store to stack if passing more. ; Function Attrs: norecurse nounwind readonly -define fp128 @testStruct_03(%struct.With9fp128params* byval nocapture readonly align 16 %a) { +define fp128 @testStruct_03(%struct.With9fp128params* byval(%struct.With9fp128params) nocapture readonly align 16 %a) { ; CHECK-LABEL: testStruct_03: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lxv v2, 128(r1) @@ -409,7 +409,7 @@ entry: ; Function Attrs: norecurse nounwind readonly -define fp128 @testNestedAggregate(%struct.MixedC* byval nocapture readonly align 16 %a) { +define fp128 @testNestedAggregate(%struct.MixedC* byval(%struct.MixedC) nocapture readonly align 16 %a) { ; CHECK-LABEL: testNestedAggregate: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: std r8, 72(r1) diff --git a/test/CodeGen/PowerPC/fastcc_stacksize.ll b/test/CodeGen/PowerPC/fastcc_stacksize.ll index d3e357e89e9..bf3693ac007 100644 --- a/test/CodeGen/PowerPC/fastcc_stacksize.ll +++ b/test/CodeGen/PowerPC/fastcc_stacksize.ll @@ -60,7 +60,7 @@ declare fastcc void define internal fastcc void @CallPassByValue(%"myClass::Mem"* %E) align 2 { entry: - call fastcc void @PassByValue(%"myClass::Mem"* byval nonnull align 8 undef); + call fastcc void @PassByValue(%"myClass::Mem"* byval(%"myClass::Mem") nonnull align 8 undef); ret void ; CHECK-LABEL: PassByValue @@ -69,7 +69,7 @@ entry: } declare dso_local fastcc void - @PassByValue(%"myClass::Mem"* byval nocapture readonly align 8) align 2 + @PassByValue(%"myClass::Mem"* byval(%"myClass::Mem") nocapture readonly align 8) align 2 ; Verify Paramater Save Area is allocated if parameter exceed the number that ; can be passed via registers @@ -127,8 +127,8 @@ declare fastcc void define internal fastcc void @AggMemExprEmitter(%"myClass::MemK"* %E) align 2 { entry: - call fastcc void @MemExprEmitterInitialization(%"myClass::MemK" * - byval nonnull align 8 undef); + call fastcc void @MemExprEmitterInitialization(%"myClass::MemK"* + byval(%"myClass::MemK") nonnull align 8 undef); ret void ; CHECK-LABEL: AggMemExprEmitter @@ -137,5 +137,5 @@ entry: } declare dso_local fastcc void - @MemExprEmitterInitialization(%"myClass::MemK" * - byval nocapture readonly align 8) align 2 + @MemExprEmitterInitialization(%"myClass::MemK"* + byval(%"myClass::MemK") nocapture readonly align 8) align 2 diff --git a/test/CodeGen/PowerPC/glob-comp-aa-crash.ll b/test/CodeGen/PowerPC/glob-comp-aa-crash.ll index 2aa5239f25e..8f56e68505f 100644 --- a/test/CodeGen/PowerPC/glob-comp-aa-crash.ll +++ b/test/CodeGen/PowerPC/glob-comp-aa-crash.ll @@ -36,7 +36,7 @@ invoke.cont: ; preds = %entry %__exception_ = getelementptr inbounds %"class.std::__1::__assoc_sub_state", %"class.std::__1::__assoc_sub_state"* %this, i64 0, i32 1 %0 = bitcast { i64, i64 }* %tmp to i8* call void @llvm.memset.p0i8.i64(i8* align 8 %0, i8 0, i64 16, i1 false) - call void @_ZNSt15__exception_ptr13exception_ptrC1EMS0_FvvE(%"class.std::__exception_ptr::exception_ptr"* %ref.tmp, { i64, i64 }* byval %tmp) #5 + call void @_ZNSt15__exception_ptr13exception_ptrC1EMS0_FvvE(%"class.std::__exception_ptr::exception_ptr"* %ref.tmp, { i64, i64 }* byval({ i64, i64 }) %tmp) #5 %call = call zeroext i1 @_ZNSt15__exception_ptrneERKNS_13exception_ptrES2_(%"class.std::__exception_ptr::exception_ptr"* %__exception_, %"class.std::__exception_ptr::exception_ptr"* %ref.tmp) #5 call void @_ZNSt15__exception_ptr13exception_ptrD1Ev(%"class.std::__exception_ptr::exception_ptr"* %ref.tmp) #5 br i1 %call, label %if.then, label %if.end @@ -102,7 +102,7 @@ declare void @_ZNSt3__117__assoc_sub_state10__sub_waitERNS_11unique_lockINS_5mut declare zeroext i1 @_ZNSt15__exception_ptrneERKNS_13exception_ptrES2_(%"class.std::__exception_ptr::exception_ptr"*, %"class.std::__exception_ptr::exception_ptr"*) #1 ; Function Attrs: nounwind optsize -declare void @_ZNSt15__exception_ptr13exception_ptrC1EMS0_FvvE(%"class.std::__exception_ptr::exception_ptr"*, { i64, i64 }* byval) #1 +declare void @_ZNSt15__exception_ptr13exception_ptrC1EMS0_FvvE(%"class.std::__exception_ptr::exception_ptr"*, { i64, i64 }* byval({ i64, i64 })) #1 ; Function Attrs: nounwind optsize declare void @_ZNSt15__exception_ptr13exception_ptrD1Ev(%"class.std::__exception_ptr::exception_ptr"*) #1 diff --git a/test/CodeGen/PowerPC/jaggedstructs.ll b/test/CodeGen/PowerPC/jaggedstructs.ll index 45e043a669d..18ec0143f02 100644 --- a/test/CodeGen/PowerPC/jaggedstructs.ll +++ b/test/CodeGen/PowerPC/jaggedstructs.ll @@ -12,9 +12,9 @@ target triple = "powerpc64-unknown-linux-gnu" %struct.S6 = type { [6 x i8] } %struct.S7 = type { [7 x i8] } -define void @test(%struct.S3* byval %s3, %struct.S5* byval %s5, %struct.S6* byval %s6, %struct.S7* byval %s7) nounwind { +define void @test(%struct.S3* byval(%struct.S3) %s3, %struct.S5* byval(%struct.S5) %s5, %struct.S6* byval(%struct.S6) %s6, %struct.S7* byval(%struct.S7) %s7) nounwind { entry: - call void @check(%struct.S3* byval %s3, %struct.S5* byval %s5, %struct.S6* byval %s6, %struct.S7* byval %s7) + call void @check(%struct.S3* byval(%struct.S3) %s3, %struct.S5* byval(%struct.S5) %s5, %struct.S6* byval(%struct.S6) %s6, %struct.S7* byval(%struct.S7) %s7) ret void } @@ -43,4 +43,4 @@ entry: ; CHECK-DAG: ld 4, 56(1) ; CHECK-DAG: ld 3, 48(1) -declare void @check(%struct.S3* byval, %struct.S5* byval, %struct.S6* byval, %struct.S7* byval) +declare void @check(%struct.S3* byval(%struct.S3), %struct.S5* byval(%struct.S5), %struct.S6* byval(%struct.S6), %struct.S7* byval(%struct.S7)) diff --git a/test/CodeGen/PowerPC/ppc440-fp-basic.ll b/test/CodeGen/PowerPC/ppc440-fp-basic.ll index 646722958f5..d01ddbef7ad 100644 --- a/test/CodeGen/PowerPC/ppc440-fp-basic.ll +++ b/test/CodeGen/PowerPC/ppc440-fp-basic.ll @@ -2,7 +2,7 @@ %0 = type { double, double } -define void @maybe_an_fma(%0* sret %agg.result, %0* byval %a, %0* byval %b, %0* byval %c) nounwind { +define void @maybe_an_fma(%0* sret %agg.result, %0* byval(%0) %a, %0* byval(%0) %b, %0* byval(%0) %c) nounwind { entry: %a.realp = getelementptr inbounds %0, %0* %a, i32 0, i32 0 %a.real = load double, double* %a.realp diff --git a/test/CodeGen/PowerPC/ppc64-align-long-double.ll b/test/CodeGen/PowerPC/ppc64-align-long-double.ll index 883d892fce3..72fb997c059 100644 --- a/test/CodeGen/PowerPC/ppc64-align-long-double.ll +++ b/test/CodeGen/PowerPC/ppc64-align-long-double.ll @@ -18,7 +18,7 @@ target triple = "powerpc64-unknown-linux-gnu" ; value. Since the target does bitcast through memory and we no longer ; remember the address we need to do the store in a fresh local ; address. -define ppc_fp128 @test(%struct.S* byval %x) nounwind { +define ppc_fp128 @test(%struct.S* byval(%struct.S) %x) nounwind { ; CHECK-LABEL: test: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: std 5, -16(1) diff --git a/test/CodeGen/PowerPC/ppc64-byval-align.ll b/test/CodeGen/PowerPC/ppc64-byval-align.ll index db0cd86995a..ebc8bdb839f 100644 --- a/test/CodeGen/PowerPC/ppc64-byval-align.ll +++ b/test/CodeGen/PowerPC/ppc64-byval-align.ll @@ -9,7 +9,7 @@ target triple = "powerpc64-unknown-linux-gnu" @gt = common global %struct.test zeroinitializer, align 16 @gp = common global %struct.pad zeroinitializer, align 8 -define signext i32 @callee1(i32 signext %x, %struct.test* byval align 16 nocapture readnone %y, i32 signext %z) { +define signext i32 @callee1(i32 signext %x, %struct.test* byval(%struct.test) align 16 nocapture readnone %y, i32 signext %z) { entry: ret i32 %z } @@ -17,17 +17,17 @@ entry: ; CHECK: mr 3, 7 ; CHECK: blr -declare signext i32 @test1(i32 signext, %struct.test* byval align 16, i32 signext) +declare signext i32 @test1(i32 signext, %struct.test* byval(%struct.test) align 16, i32 signext) define void @caller1(i32 signext %z) { entry: - %call = tail call signext i32 @test1(i32 signext 0, %struct.test* byval align 16 @gt, i32 signext %z) + %call = tail call signext i32 @test1(i32 signext 0, %struct.test* byval(%struct.test) align 16 @gt, i32 signext %z) ret void } ; CHECK-LABEL: @caller1 ; CHECK: mr 7, 3 ; CHECK: bl test1 -define i64 @callee2(%struct.pad* byval nocapture readnone %x, i32 signext %y, %struct.test* byval align 16 nocapture readonly %z) { +define i64 @callee2(%struct.pad* byval(%struct.pad) nocapture readnone %x, i32 signext %y, %struct.test* byval(%struct.test) align 16 nocapture readonly %z) { entry: %x1 = getelementptr inbounds %struct.test, %struct.test* %z, i64 0, i32 0 %0 = load i64, i64* %x1, align 16 @@ -37,13 +37,13 @@ entry: ; CHECK: ld {{[0-9]+}}, 128(1) ; CHECK: blr -declare i64 @test2(%struct.pad* byval, i32 signext, %struct.test* byval align 16) +declare i64 @test2(%struct.pad* byval(%struct.pad), i32 signext, %struct.test* byval(%struct.test) align 16) define void @caller2(i64 %z) { entry: %tmp = alloca %struct.test, align 16 %.compoundliteral.sroa.0.0..sroa_idx = getelementptr inbounds %struct.test, %struct.test* %tmp, i64 0, i32 0 store i64 %z, i64* %.compoundliteral.sroa.0.0..sroa_idx, align 16 - %call = call i64 @test2(%struct.pad* byval @gp, i32 signext 0, %struct.test* byval align 16 %tmp) + %call = call i64 @test2(%struct.pad* byval(%struct.pad) @gp, i32 signext 0, %struct.test* byval(%struct.test) align 16 %tmp) ret void } ; CHECK-LABEL: @caller2 diff --git a/test/CodeGen/PowerPC/ppc64-crash.ll b/test/CodeGen/PowerPC/ppc64-crash.ll index d335e1b8229..4431f0c15ec 100644 --- a/test/CodeGen/PowerPC/ppc64-crash.ll +++ b/test/CodeGen/PowerPC/ppc64-crash.ll @@ -8,7 +8,7 @@ target triple = "powerpc64-unknown-freebsd" %struct.pos_T = type { i64 } ; check that we're not copying stuff between R and X registers -define internal void @serialize_pos(%struct.pos_T* byval %pos, %struct.__sFILE* %fp) nounwind { +define internal void @serialize_pos(%struct.pos_T* byval(%struct.pos_T) %pos, %struct.__sFILE* %fp) nounwind { entry: ret void } diff --git a/test/CodeGen/PowerPC/ppc64-sibcall.ll b/test/CodeGen/PowerPC/ppc64-sibcall.ll index 357f28e88b1..65f7243fb67 100644 --- a/test/CodeGen/PowerPC/ppc64-sibcall.ll +++ b/test/CodeGen/PowerPC/ppc64-sibcall.ll @@ -204,9 +204,9 @@ define void @w_caller(i8* %ptr) { %struct.byvalTest = type { [8 x i8] } @byval = common global %struct.byvalTest zeroinitializer -define void @byval_callee(%struct.byvalTest* byval %ptr) { ret void } +define void @byval_callee(%struct.byvalTest* byval(%struct.byvalTest) %ptr) { ret void } define void @byval_caller() { - tail call void @byval_callee(%struct.byvalTest* byval @byval) + tail call void @byval_callee(%struct.byvalTest* byval(%struct.byvalTest) @byval) ret void ; CHECK-SCO-LABEL: bl byval_callee diff --git a/test/CodeGen/PowerPC/ppc64-smallarg.ll b/test/CodeGen/PowerPC/ppc64-smallarg.ll index a71ea80b6f9..885e199b002 100644 --- a/test/CodeGen/PowerPC/ppc64-smallarg.ll +++ b/test/CodeGen/PowerPC/ppc64-smallarg.ll @@ -13,7 +13,7 @@ target triple = "powerpc64-unknown-linux-gnu" @gs = common global %struct.small_arg zeroinitializer, align 2 @gf = common global float 0.000000e+00, align 4 -define void @callee1(%struct.small_arg* noalias nocapture sret %agg.result, %struct.large_arg* byval nocapture readnone %pad, %struct.small_arg* byval nocapture readonly %x) { +define void @callee1(%struct.small_arg* noalias nocapture sret(%struct.small_arg) %agg.result, %struct.large_arg* byval(%struct.large_arg) nocapture readnone %pad, %struct.small_arg* byval(%struct.small_arg) nocapture readonly %x) { entry: %0 = bitcast %struct.small_arg* %x to i32* %1 = bitcast %struct.small_arg* %agg.result to i32* @@ -28,14 +28,14 @@ entry: define void @caller1() { entry: %tmp = alloca %struct.small_arg, align 2 - call void @test1(%struct.small_arg* sret %tmp, %struct.large_arg* byval @gl, %struct.small_arg* byval @gs) + call void @test1(%struct.small_arg* sret %tmp, %struct.large_arg* byval(%struct.large_arg) @gl, %struct.small_arg* byval(%struct.small_arg) @gs) ret void } ; CHECK: @caller1 ; CHECK: stw {{[0-9]+}}, 124(1) ; CHECK: bl test1 -declare void @test1(%struct.small_arg* sret, %struct.large_arg* byval, %struct.small_arg* byval) +declare void @test1(%struct.small_arg* sret, %struct.large_arg* byval(%struct.large_arg), %struct.small_arg* byval(%struct.small_arg)) define float @callee2(float %pad1, float %pad2, float %pad3, float %pad4, float %pad5, float %pad6, float %pad7, float %pad8, float %pad9, float %pad10, float %pad11, float %pad12, float %pad13, float %x) { entry: diff --git a/test/CodeGen/PowerPC/ppc64le-smallarg.ll b/test/CodeGen/PowerPC/ppc64le-smallarg.ll index 9eac7d0c4d7..bd5f29a0118 100644 --- a/test/CodeGen/PowerPC/ppc64le-smallarg.ll +++ b/test/CodeGen/PowerPC/ppc64le-smallarg.ll @@ -13,7 +13,7 @@ target triple = "powerpc64le-unknown-linux-gnu" @gs = common global %struct.small_arg zeroinitializer, align 2 @gf = common global float 0.000000e+00, align 4 -define void @callee1(%struct.small_arg* noalias nocapture sret %agg.result, %struct.large_arg* byval nocapture readnone %pad, %struct.small_arg* byval nocapture readonly %x) { +define void @callee1(%struct.small_arg* noalias nocapture sret %agg.result, %struct.large_arg* byval(%struct.large_arg) nocapture readnone %pad, %struct.small_arg* byval(%struct.small_arg) nocapture readonly %x) { entry: %0 = bitcast %struct.small_arg* %x to i32* %1 = bitcast %struct.small_arg* %agg.result to i32* @@ -28,21 +28,21 @@ entry: define void @caller1() { entry: %tmp = alloca %struct.small_arg, align 2 - call void @test1(%struct.small_arg* sret %tmp, %struct.large_arg* byval @gl, %struct.small_arg* byval @gs) + call void @test1(%struct.small_arg* sret %tmp, %struct.large_arg* byval(%struct.large_arg) @gl, %struct.small_arg* byval(%struct.small_arg) @gs) ret void } ; CHECK: @caller1 ; CHECK: stw {{[0-9]+}}, 104(1) ; CHECK: bl test1 -declare void @test1(%struct.small_arg* sret, %struct.large_arg* byval, %struct.small_arg* byval) +declare void @test1(%struct.small_arg* sret, %struct.large_arg* byval(%struct.large_arg), %struct.small_arg* byval(%struct.small_arg)) define float @callee2(float %pad1, float %pad2, float %pad3, float %pad4, float %pad5, float %pad6, float %pad7, float %pad8, float %pad9, float %pad10, float %pad11, float %pad12, float %pad13, float %x) { entry: ret float %x } ; CHECK: @callee2 -; CHECK: lfs {{[0-9]+}}, 136(1) +; CHECK: lfs {{[0-9]+}}, 136(1) ; CHECK: blr define void @caller2() { diff --git a/test/CodeGen/PowerPC/pr13891.ll b/test/CodeGen/PowerPC/pr13891.ll index 10532a9b38e..f35a0a724bf 100644 --- a/test/CodeGen/PowerPC/pr13891.ll +++ b/test/CodeGen/PowerPC/pr13891.ll @@ -4,7 +4,7 @@ target triple = "powerpc64-unknown-linux-gnu" %struct.foo = type { i8, i8 } -define void @_Z5check3foos(%struct.foo* nocapture byval %f, i16 signext %i) noinline { +define void @_Z5check3foos(%struct.foo* nocapture byval(%struct.foo) %f, i16 signext %i) noinline { ; CHECK-LABEL: _Z5check3foos: ; CHECK: sth 3, {{[0-9]+}}(1) ; CHECK: lha {{[0-9]+}}, {{[0-9]+}}(1) diff --git a/test/CodeGen/PowerPC/reloc-align.ll b/test/CodeGen/PowerPC/reloc-align.ll index 59f7137fd64..929d2bf86c8 100644 --- a/test/CodeGen/PowerPC/reloc-align.ll +++ b/test/CodeGen/PowerPC/reloc-align.ll @@ -15,13 +15,13 @@ target triple = "powerpc64-unknown-linux-gnu" ; Function Attrs: nounwind readonly define signext i32 @main() #0 { entry: - %call = tail call fastcc signext i32 @func_90(%struct.S1* byval bitcast ({ i8, i8, i8, i8, i8, i8, i8, i8 }* @main.l_1554 to %struct.S1*)) + %call = tail call fastcc signext i32 @func_90(%struct.S1* byval(%struct.S1) bitcast ({ i8, i8, i8, i8, i8, i8, i8, i8 }* @main.l_1554 to %struct.S1*)) ; CHECK-NOT: ld {{[0-9]+}}, main.l_1554@toc@l ret i32 %call } ; Function Attrs: nounwind readonly -define internal fastcc signext i32 @func_90(%struct.S1* byval nocapture %p_91) #0 { +define internal fastcc signext i32 @func_90(%struct.S1* byval(%struct.S1) nocapture %p_91) #0 { entry: %0 = bitcast %struct.S1* %p_91 to i64* %bf.load = load i64, i64* %0, align 1 diff --git a/test/CodeGen/PowerPC/resolvefi-basereg.ll b/test/CodeGen/PowerPC/resolvefi-basereg.ll index 731f37d2770..bffe770237c 100644 --- a/test/CodeGen/PowerPC/resolvefi-basereg.ll +++ b/test/CodeGen/PowerPC/resolvefi-basereg.ll @@ -332,15 +332,15 @@ if.end: ; preds = %if.then, %entry call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %62, i8* align 16 bitcast (%struct.S1998* @s1998 to i8*), i64 5168, i1 false) %63 = bitcast %struct.S1998* %agg.tmp112 to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %63, i8* align 16 bitcast (%struct.S1998* getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 2) to i8*), i64 5168, i1 false) - call void @check1998(%struct.S1998* sret %agg.tmp, %struct.S1998* byval align 16 %agg.tmp111, %struct.S1998* getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 1), %struct.S1998* byval align 16 %agg.tmp112) - call void @checkx1998(%struct.S1998* byval align 16 %agg.tmp) + call void @check1998(%struct.S1998* sret %agg.tmp, %struct.S1998* byval(%struct.S1998) align 16 %agg.tmp111, %struct.S1998* getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 1), %struct.S1998* byval(%struct.S1998) align 16 %agg.tmp112) + call void @checkx1998(%struct.S1998* byval(%struct.S1998) align 16 %agg.tmp) %64 = bitcast %struct.S1998* %agg.tmp113 to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %64, i8* align 16 bitcast (%struct.S1998* @s1998 to i8*), i64 5168, i1 false) %65 = bitcast %struct.S1998* %agg.tmp114 to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %65, i8* align 16 bitcast (%struct.S1998* getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 2) to i8*), i64 5168, i1 false) %66 = bitcast %struct.S1998* %agg.tmp115 to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %66, i8* align 16 bitcast (%struct.S1998* getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 2) to i8*), i64 5168, i1 false) - call void (i32, ...) @check1998va(i32 signext 1, double 1.000000e+00, %struct.S1998* byval align 16 %agg.tmp113, i64 2, %struct.S1998* byval align 16 %agg.tmp114, %struct.S1998* byval align 16 %agg.tmp115) + call void (i32, ...) @check1998va(i32 signext 1, double 1.000000e+00, %struct.S1998* byval(%struct.S1998) align 16 %agg.tmp113, i64 2, %struct.S1998* byval(%struct.S1998) align 16 %agg.tmp114, %struct.S1998* byval(%struct.S1998) align 16 %agg.tmp115) %67 = bitcast %struct.S1998* %agg.tmp116 to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %67, i8* align 16 bitcast (%struct.S1998* @s1998 to i8*), i64 5168, i1 false) %68 = bitcast %struct.S1998* %agg.tmp117 to i8* @@ -349,14 +349,14 @@ if.end: ; preds = %if.then, %entry call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %69, i8* align 16 bitcast (%struct.S1998* getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 2) to i8*), i64 5168, i1 false) %70 = bitcast %struct.S1998* %agg.tmp119 to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %70, i8* align 16 bitcast (%struct.S1998* @s1998 to i8*), i64 5168, i1 false) - call void (i32, ...) @check1998va(i32 signext 2, %struct.S1998* byval align 16 %agg.tmp116, %struct.S1998* byval align 16 %agg.tmp117, ppc_fp128 0xM40000000000000000000000000000000, %struct.S1998* byval align 16 %agg.tmp118, %struct.S1998* byval align 16 %agg.tmp119) + call void (i32, ...) @check1998va(i32 signext 2, %struct.S1998* byval(%struct.S1998) align 16 %agg.tmp116, %struct.S1998* byval(%struct.S1998) align 16 %agg.tmp117, ppc_fp128 0xM40000000000000000000000000000000, %struct.S1998* byval(%struct.S1998) align 16 %agg.tmp118, %struct.S1998* byval(%struct.S1998) align 16 %agg.tmp119) ret void } declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i1) -declare void @check1998(%struct.S1998* sret, %struct.S1998* byval align 16, %struct.S1998*, %struct.S1998* byval align 16) +declare void @check1998(%struct.S1998* sret, %struct.S1998* byval(%struct.S1998) align 16, %struct.S1998*, %struct.S1998* byval(%struct.S1998) align 16) declare void @check1998va(i32 signext, ...) -declare void @checkx1998(%struct.S1998* byval align 16 %arg) +declare void @checkx1998(%struct.S1998* byval(%struct.S1998) align 16 %arg) diff --git a/test/CodeGen/PowerPC/resolvefi-disp.ll b/test/CodeGen/PowerPC/resolvefi-disp.ll index 68a31278e77..3af2501a907 100644 --- a/test/CodeGen/PowerPC/resolvefi-disp.ll +++ b/test/CodeGen/PowerPC/resolvefi-disp.ll @@ -20,7 +20,7 @@ target triple = "powerpc64le-unknown-linux-gnu" @s2760 = external global %struct.S2760 @fails = external global i32 -define void @check2760(%struct.S2760* noalias sret %agg.result, %struct.S2760* byval align 16, %struct.S2760* %arg1, %struct.S2760* byval align 16) { +define void @check2760(%struct.S2760* noalias sret %agg.result, %struct.S2760* byval(%struct.S2760) align 16, %struct.S2760* %arg1, %struct.S2760* byval(%struct.S2760) align 16) { entry: %arg0 = alloca %struct.S2760, align 32 %arg2 = alloca %struct.S2760, align 32 diff --git a/test/CodeGen/PowerPC/stack-realign.ll b/test/CodeGen/PowerPC/stack-realign.ll index ea3603b9ce2..abb608797f0 100644 --- a/test/CodeGen/PowerPC/stack-realign.ll +++ b/test/CodeGen/PowerPC/stack-realign.ll @@ -11,7 +11,7 @@ declare void @bar(i32*) @barbaz = external global i32 -define void @goo(%struct.s* byval nocapture readonly %a) { +define void @goo(%struct.s* byval(%struct.s) nocapture readonly %a) { entry: %x = alloca [2 x i32], align 32 %a1 = getelementptr inbounds %struct.s, %struct.s* %a, i64 0, i32 0 @@ -105,7 +105,7 @@ entry: ; CHECK-32-PIC: addic 29, 0, 12 ; The large-frame-size case. -define void @hoo(%struct.s* byval nocapture readonly %a) { +define void @hoo(%struct.s* byval(%struct.s) nocapture readonly %a) { entry: %x = alloca [200000 x i32], align 32 %a1 = getelementptr inbounds %struct.s, %struct.s* %a, i64 0, i32 0 @@ -174,7 +174,7 @@ entry: ; Make sure that the FP save area is still allocated correctly relative to ; where r30 is saved. -define void @loo(%struct.s* byval nocapture readonly %a) { +define void @loo(%struct.s* byval(%struct.s) nocapture readonly %a) { entry: %x = alloca [2 x i32], align 32 %a1 = getelementptr inbounds %struct.s, %struct.s* %a, i64 0, i32 0 diff --git a/test/CodeGen/PowerPC/structsinmem.ll b/test/CodeGen/PowerPC/structsinmem.ll index b994aae6eea..bbbd95ccd5f 100644 --- a/test/CodeGen/PowerPC/structsinmem.ll +++ b/test/CodeGen/PowerPC/structsinmem.ll @@ -56,7 +56,7 @@ entry: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %5, i8* align 4 bitcast ({ i32, i16, [2 x i8] }* @caller1.p6 to i8*), i64 8, i1 false) %6 = bitcast %struct.s7* %p7 to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %6, i8* align 4 bitcast ({ i32, i16, i8, i8 }* @caller1.p7 to i8*), i64 8, i1 false) - %call = call i32 @callee1(i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, %struct.s1* byval %p1, %struct.s2* byval %p2, %struct.s3* byval %p3, %struct.s4* byval %p4, %struct.s5* byval %p5, %struct.s6* byval %p6, %struct.s7* byval %p7) + %call = call i32 @callee1(i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, %struct.s1* byval(%struct.s1) %p1, %struct.s2* byval(%struct.s2) %p2, %struct.s3* byval(%struct.s3) %p3, %struct.s4* byval(%struct.s4) %p4, %struct.s5* byval(%struct.s5) %p5, %struct.s6* byval(%struct.s6) %p6, %struct.s7* byval(%struct.s7) %p7) ret i32 %call ; CHECK: stb {{[0-9]+}}, 119(1) @@ -70,7 +70,7 @@ entry: declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1) nounwind -define internal i32 @callee1(i32 %z1, i32 %z2, i32 %z3, i32 %z4, i32 %z5, i32 %z6, i32 %z7, i32 %z8, %struct.s1* byval %v1, %struct.s2* byval %v2, %struct.s3* byval %v3, %struct.s4* byval %v4, %struct.s5* byval %v5, %struct.s6* byval %v6, %struct.s7* byval %v7) nounwind { +define internal i32 @callee1(i32 %z1, i32 %z2, i32 %z3, i32 %z4, i32 %z5, i32 %z6, i32 %z7, i32 %z8, %struct.s1* byval(%struct.s1) %v1, %struct.s2* byval(%struct.s2) %v2, %struct.s3* byval(%struct.s3) %v3, %struct.s4* byval(%struct.s4) %v4, %struct.s5* byval(%struct.s5) %v5, %struct.s6* byval(%struct.s6) %v6, %struct.s7* byval(%struct.s7) %v7) nounwind { entry: %z1.addr = alloca i32, align 4 %z2.addr = alloca i32, align 4 @@ -145,7 +145,7 @@ entry: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %5, i8* bitcast (%struct.t6* @caller2.p6 to i8*), i64 6, i1 false) %6 = bitcast %struct.t7* %p7 to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* %6, i8* bitcast (%struct.t7* @caller2.p7 to i8*), i64 7, i1 false) - %call = call i32 @callee2(i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, %struct.t1* byval %p1, %struct.t2* byval %p2, %struct.t3* byval %p3, %struct.t4* byval %p4, %struct.t5* byval %p5, %struct.t6* byval %p6, %struct.t7* byval %p7) + %call = call i32 @callee2(i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, %struct.t1* byval(%struct.t1) %p1, %struct.t2* byval(%struct.t2) %p2, %struct.t3* byval(%struct.t3) %p3, %struct.t4* byval(%struct.t4) %p4, %struct.t5* byval(%struct.t5) %p5, %struct.t6* byval(%struct.t6) %p6, %struct.t7* byval(%struct.t7) %p7) ret i32 %call ; CHECK: stb {{[0-9]+}}, 119(1) @@ -161,7 +161,7 @@ entry: ; CHECK: stw {{[0-9]+}}, 161(1) } -define internal i32 @callee2(i32 %z1, i32 %z2, i32 %z3, i32 %z4, i32 %z5, i32 %z6, i32 %z7, i32 %z8, %struct.t1* byval %v1, %struct.t2* byval %v2, %struct.t3* byval %v3, %struct.t4* byval %v4, %struct.t5* byval %v5, %struct.t6* byval %v6, %struct.t7* byval %v7) nounwind { +define internal i32 @callee2(i32 %z1, i32 %z2, i32 %z3, i32 %z4, i32 %z5, i32 %z6, i32 %z7, i32 %z8, %struct.t1* byval(%struct.t1) %v1, %struct.t2* byval(%struct.t2) %v2, %struct.t3* byval(%struct.t3) %v3, %struct.t4* byval(%struct.t4) %v4, %struct.t5* byval(%struct.t5) %v5, %struct.t6* byval(%struct.t6) %v6, %struct.t7* byval(%struct.t7) %v7) nounwind { entry: %z1.addr = alloca i32, align 4 %z2.addr = alloca i32, align 4 diff --git a/test/CodeGen/PowerPC/structsinregs.ll b/test/CodeGen/PowerPC/structsinregs.ll index 08f8ba90fd1..caa78246e05 100644 --- a/test/CodeGen/PowerPC/structsinregs.ll +++ b/test/CodeGen/PowerPC/structsinregs.ll @@ -56,7 +56,7 @@ entry: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %5, i8* align 4 bitcast ({ i32, i16, [2 x i8] }* @caller1.p6 to i8*), i64 8, i1 false) %6 = bitcast %struct.s7* %p7 to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %6, i8* align 4 bitcast ({ i32, i16, i8, i8 }* @caller1.p7 to i8*), i64 8, i1 false) - %call = call i32 @callee1(%struct.s1* byval %p1, %struct.s2* byval %p2, %struct.s3* byval %p3, %struct.s4* byval %p4, %struct.s5* byval %p5, %struct.s6* byval %p6, %struct.s7* byval %p7) + %call = call i32 @callee1(%struct.s1* byval(%struct.s1) %p1, %struct.s2* byval(%struct.s2) %p2, %struct.s3* byval(%struct.s3) %p3, %struct.s4* byval(%struct.s4) %p4, %struct.s5* byval(%struct.s5) %p5, %struct.s6* byval(%struct.s6) %p6, %struct.s7* byval(%struct.s7) %p7) ret i32 %call ; CHECK-LABEL: caller1 @@ -71,7 +71,7 @@ entry: declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1) nounwind -define internal i32 @callee1(%struct.s1* byval %v1, %struct.s2* byval %v2, %struct.s3* byval %v3, %struct.s4* byval %v4, %struct.s5* byval %v5, %struct.s6* byval %v6, %struct.s7* byval %v7) nounwind { +define internal i32 @callee1(%struct.s1* byval(%struct.s1) %v1, %struct.s2* byval(%struct.s2) %v2, %struct.s3* byval(%struct.s3) %v3, %struct.s4* byval(%struct.s4) %v4, %struct.s5* byval(%struct.s5) %v5, %struct.s6* byval(%struct.s6) %v6, %struct.s7* byval(%struct.s7) %v7) nounwind { entry: %a = getelementptr inbounds %struct.s1, %struct.s1* %v1, i32 0, i32 0 %0 = load i8, i8* %a, align 1 @@ -138,7 +138,7 @@ entry: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %5, i8* bitcast (%struct.t6* @caller2.p6 to i8*), i64 6, i1 false) %6 = bitcast %struct.t7* %p7 to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* %6, i8* bitcast (%struct.t7* @caller2.p7 to i8*), i64 7, i1 false) - %call = call i32 @callee2(%struct.t1* byval %p1, %struct.t2* byval %p2, %struct.t3* byval %p3, %struct.t4* byval %p4, %struct.t5* byval %p5, %struct.t6* byval %p6, %struct.t7* byval %p7) + %call = call i32 @callee2(%struct.t1* byval(%struct.t1) %p1, %struct.t2* byval(%struct.t2) %p2, %struct.t3* byval(%struct.t3) %p3, %struct.t4* byval(%struct.t4) %p4, %struct.t5* byval(%struct.t5) %p5, %struct.t6* byval(%struct.t6) %p6, %struct.t7* byval(%struct.t7) %p7) ret i32 %call ; CHECK-LABEL: caller2 @@ -159,7 +159,7 @@ entry: ; CHECK: lbz 3, 160(31) } -define internal i32 @callee2(%struct.t1* byval %v1, %struct.t2* byval %v2, %struct.t3* byval %v3, %struct.t4* byval %v4, %struct.t5* byval %v5, %struct.t6* byval %v6, %struct.t7* byval %v7) nounwind { +define internal i32 @callee2(%struct.t1* byval(%struct.t1) %v1, %struct.t2* byval(%struct.t2) %v2, %struct.t3* byval(%struct.t3) %v3, %struct.t4* byval(%struct.t4) %v4, %struct.t5* byval(%struct.t5) %v5, %struct.t6* byval(%struct.t6) %v6, %struct.t7* byval(%struct.t7) %v7) nounwind { entry: %a = getelementptr inbounds %struct.t1, %struct.t1* %v1, i32 0, i32 0 %0 = load i8, i8* %a, align 1 diff --git a/test/CodeGen/PowerPC/vec-abi-align.ll b/test/CodeGen/PowerPC/vec-abi-align.ll index ba687d3f0b8..c01b55a32a6 100644 --- a/test/CodeGen/PowerPC/vec-abi-align.ll +++ b/test/CodeGen/PowerPC/vec-abi-align.ll @@ -24,7 +24,7 @@ entry: } ; Function Attrs: nounwind -define void @test2(i64 %d1, i64 %d2, i64 %d3, i64 %d4, i64 %d5, i64 %d6, i64 %d7, i64 %d8, %struct.s2* byval nocapture readonly %vs) #0 { +define void @test2(i64 %d1, i64 %d2, i64 %d3, i64 %d4, i64 %d5, i64 %d6, i64 %d7, i64 %d8, %struct.s2* byval(%struct.s2) nocapture readonly %vs) #0 { entry: %m = getelementptr inbounds %struct.s2, %struct.s2* %vs, i64 0, i32 0 %0 = load i64, i64* %m, align 8 @@ -50,7 +50,7 @@ entry: } ; Function Attrs: nounwind -define void @test3(i64 %d1, i64 %d2, i64 %d3, i64 %d4, i64 %d5, i64 %d6, i64 %d7, i64 %d8, i64 %d9, %struct.s2* byval nocapture readonly %vs) #0 { +define void @test3(i64 %d1, i64 %d2, i64 %d3, i64 %d4, i64 %d5, i64 %d6, i64 %d7, i64 %d8, i64 %d9, %struct.s2* byval(%struct.s2) nocapture readonly %vs) #0 { entry: %m = getelementptr inbounds %struct.s2, %struct.s2* %vs, i64 0, i32 0 %0 = load i64, i64* %m, align 8 diff --git a/test/CodeGen/RISCV/byval.ll b/test/CodeGen/RISCV/byval.ll index 832dfb2e8a2..99e6abf23b8 100644 --- a/test/CodeGen/RISCV/byval.ll +++ b/test/CodeGen/RISCV/byval.ll @@ -5,7 +5,7 @@ %struct.Foo = type { i32, i32, i32, i16, i8 } @foo = global %struct.Foo { i32 1, i32 2, i32 3, i16 4, i8 5 }, align 4 -define i32 @callee(%struct.Foo* byval %f) nounwind { +define i32 @callee(%struct.Foo* byval(%struct.Foo) %f) nounwind { ; RV32I-LABEL: callee: ; RV32I: # %bb.0: # %entry ; RV32I-NEXT: lw a0, 0(a0) @@ -38,6 +38,6 @@ define void @caller() nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret entry: - %call = call i32 @callee(%struct.Foo* byval @foo) + %call = call i32 @callee(%struct.Foo* byval(%struct.Foo) @foo) ret void } diff --git a/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll b/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll index 3e7945887f4..d0ac364d46a 100644 --- a/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll +++ b/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll @@ -521,7 +521,7 @@ define i32 @caller_small_coerced_struct() nounwind { %struct.large = type { i32, i32, i32, i32 } -define i32 @callee_large_struct(%struct.large* byval align 4 %a) nounwind { +define i32 @callee_large_struct(%struct.large* byval(%struct.large) align 4 %a) nounwind { ; RV32I-FPELIM-LABEL: callee_large_struct: ; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM-NEXT: lw a1, 0(a0) @@ -607,7 +607,7 @@ define i32 @caller_large_struct() nounwind { store i32 3, i32* %c %d = getelementptr inbounds %struct.large, %struct.large* %ls, i32 0, i32 3 store i32 4, i32* %d - %2 = call i32 @callee_large_struct(%struct.large* byval align 4 %ls) + %2 = call i32 @callee_large_struct(%struct.large* byval(%struct.large) align 4 %ls) ret i32 %2 } diff --git a/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll b/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll index fac227f4978..1c4117fc39d 100644 --- a/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll +++ b/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll @@ -274,7 +274,7 @@ define i64 @caller_small_coerced_struct() nounwind { %struct.large = type { i64, i64, i64, i64 } -define i64 @callee_large_struct(%struct.large* byval align 8 %a) nounwind { +define i64 @callee_large_struct(%struct.large* byval(%struct.large) align 8 %a) nounwind { ; RV64I-LABEL: callee_large_struct: ; RV64I: # %bb.0: ; RV64I-NEXT: ld a1, 0(a0) @@ -321,7 +321,7 @@ define i64 @caller_large_struct() nounwind { store i64 3, i64* %c %d = getelementptr inbounds %struct.large, %struct.large* %ls, i64 0, i32 3 store i64 4, i64* %d - %2 = call i64 @callee_large_struct(%struct.large* byval align 8 %ls) + %2 = call i64 @callee_large_struct(%struct.large* byval(%struct.large) align 8 %ls) ret i64 %2 } diff --git a/test/CodeGen/RISCV/tail-calls.ll b/test/CodeGen/RISCV/tail-calls.ll index c989df932a4..eaf53938c51 100644 --- a/test/CodeGen/RISCV/tail-calls.ll +++ b/test/CodeGen/RISCV/tail-calls.ll @@ -122,14 +122,14 @@ attributes #0 = { "interrupt"="machine" } ; Byval parameters hand the function a pointer directly into the stack area ; we want to reuse during a tail call. Do not tail call optimize functions with ; byval parameters. -declare i32 @callee_byval(i32** byval %a) +declare i32 @callee_byval(i32** byval(i32*) %a) define i32 @caller_byval() nounwind { ; CHECK-LABEL: caller_byval ; CHECK-NOT: tail callee_byval ; CHECK: call callee_byval entry: %a = alloca i32* - %r = tail call i32 @callee_byval(i32** byval %a) + %r = tail call i32 @callee_byval(i32** byval(i32*) %a) ret i32 %r } diff --git a/test/CodeGen/SPARC/2011-01-21-ByValArgs.ll b/test/CodeGen/SPARC/2011-01-21-ByValArgs.ll index 408b13d70a3..cd95fbcf052 100644 --- a/test/CodeGen/SPARC/2011-01-21-ByValArgs.ll +++ b/test/CodeGen/SPARC/2011-01-21-ByValArgs.ll @@ -11,8 +11,8 @@ entry: ;CHECK: st ;CHECK: st ;CHECK: bar - %0 = tail call i32 @bar(%struct.foo_t* byval @s) nounwind + %0 = tail call i32 @bar(%struct.foo_t* byval(%struct.foo_t) @s) nounwind ret i32 %0 } -declare i32 @bar(%struct.foo_t* byval) +declare i32 @bar(%struct.foo_t* byval(%struct.foo_t)) diff --git a/test/CodeGen/SPARC/LeonFixAllFDIVSQRTPassUT.ll b/test/CodeGen/SPARC/LeonFixAllFDIVSQRTPassUT.ll index c79414d2791..c4c022d9f72 100644 --- a/test/CodeGen/SPARC/LeonFixAllFDIVSQRTPassUT.ll +++ b/test/CodeGen/SPARC/LeonFixAllFDIVSQRTPassUT.ll @@ -19,7 +19,7 @@ ; CHECK-NEXT: nop ; CHECK-NEXT: nop ; CHECK-NEXT: nop -define double @test_1(double* byval %a, double* byval %b) { +define double @test_1(double* byval(double) %a, double* byval(double) %b) { entry: %0 = load double, double* %a, align 8 %1 = load double, double* %b, align 8 @@ -50,7 +50,7 @@ declare double @llvm.sqrt.f64(double) nounwind readonly ; CHECK-NEXT: nop ; CHECK-NEXT: nop ; CHECK-NEXT: nop -define double @test_2(double* byval %a) { +define double @test_2(double* byval(double) %a) { entry: %0 = load double, double* %a, align 8 %1 = call double @llvm.sqrt.f64(double %0) nounwind diff --git a/test/CodeGen/SPARC/LeonItinerariesUT.ll b/test/CodeGen/SPARC/LeonItinerariesUT.ll index 5a6be134686..796dcf2e145 100644 --- a/test/CodeGen/SPARC/LeonItinerariesUT.ll +++ b/test/CodeGen/SPARC/LeonItinerariesUT.ll @@ -4,39 +4,39 @@ ; RUN: llc < %s -O1 -march=sparc -mcpu=leon4 | FileCheck %s -check-prefix=LEON3_4_ITIN ; NO_ITIN-LABEL: f32_ops: -; NO_ITIN: ld -; NO_ITIN-NEXT: ld -; NO_ITIN-NEXT: ld -; NO_ITIN-NEXT: ld -; NO_ITIN-NEXT: fadds -; NO_ITIN-NEXT: fsubs -; NO_ITIN-NEXT: fmuls -; NO_ITIN-NEXT: retl -; NO_ITIN-NEXT: fdivs +; NO_ITIN: ld +; NO_ITIN-NEXT: ld +; NO_ITIN-NEXT: ld +; NO_ITIN-NEXT: ld +; NO_ITIN-NEXT: fadds +; NO_ITIN-NEXT: fsubs +; NO_ITIN-NEXT: fmuls +; NO_ITIN-NEXT: retl +; NO_ITIN-NEXT: fdivs ; LEON2_ITIN-LABEL: f32_ops: -; LEON2_ITIN: ld -; LEON2_ITIN-NEXT: ld -; LEON2_ITIN-NEXT: fadds -; LEON2_ITIN-NEXT: ld -; LEON2_ITIN-NEXT: fsubs -; LEON2_ITIN-NEXT: ld -; LEON2_ITIN-NEXT: fmuls -; LEON2_ITIN-NEXT: retl -; LEON2_ITIN-NEXT: fdivs +; LEON2_ITIN: ld +; LEON2_ITIN-NEXT: ld +; LEON2_ITIN-NEXT: fadds +; LEON2_ITIN-NEXT: ld +; LEON2_ITIN-NEXT: fsubs +; LEON2_ITIN-NEXT: ld +; LEON2_ITIN-NEXT: fmuls +; LEON2_ITIN-NEXT: retl +; LEON2_ITIN-NEXT: fdivs ; LEON3_4_ITIN-LABEL: f32_ops: -; LEON3_4_ITIN: ld -; LEON3_4_ITIN-NEXT: ld -; LEON3_4_ITIN-NEXT: ld -; LEON3_4_ITIN-NEXT: fadds -; LEON3_4_ITIN-NEXT: ld -; LEON3_4_ITIN-NEXT: fsubs -; LEON3_4_ITIN-NEXT: fmuls -; LEON3_4_ITIN-NEXT: retl -; LEON3_4_ITIN-NEXT: fdivs +; LEON3_4_ITIN: ld +; LEON3_4_ITIN-NEXT: ld +; LEON3_4_ITIN-NEXT: ld +; LEON3_4_ITIN-NEXT: fadds +; LEON3_4_ITIN-NEXT: ld +; LEON3_4_ITIN-NEXT: fsubs +; LEON3_4_ITIN-NEXT: fmuls +; LEON3_4_ITIN-NEXT: retl +; LEON3_4_ITIN-NEXT: fdivs -define float @f32_ops(float* byval %a, float* byval %b, float* byval %c, float* byval %d) { +define float @f32_ops(float* byval(float) %a, float* byval(float) %b, float* byval(float) %c, float* byval(float) %d) { entry: %0 = load float, float* %a, align 8 %1 = load float, float* %b, align 8 diff --git a/test/CodeGen/SPARC/fp128.ll b/test/CodeGen/SPARC/fp128.ll index 22fab41f479..5abbc50e6bb 100644 --- a/test/CodeGen/SPARC/fp128.ll +++ b/test/CodeGen/SPARC/fp128.ll @@ -23,7 +23,7 @@ ; CHECK: std ; CHECK: std -define void @f128_ops(fp128* noalias sret %scalar.result, fp128* byval %a, fp128* byval %b, fp128* byval %c, fp128* byval %d) { +define void @f128_ops(fp128* noalias sret %scalar.result, fp128* byval(fp128) %a, fp128* byval(fp128) %b, fp128* byval(fp128) %c, fp128* byval(fp128) %d) { entry: %0 = load fp128, fp128* %a, align 8 %1 = load fp128, fp128* %b, align 8 @@ -44,7 +44,7 @@ entry: ; CHECK-DAG: ldd [%[[S1]]], %f{{.+}} ; CHECK: jmp {{%[oi]7}}+12 -define void @f128_spill(fp128* noalias sret %scalar.result, fp128* byval %a) { +define void @f128_spill(fp128* noalias sret %scalar.result, fp128* byval(fp128) %a) { entry: %0 = load fp128, fp128* %a, align 8 call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() @@ -67,7 +67,7 @@ entry: ; CHECK-NEXT: add %g1, %sp, %g1 ; CHECK-NEXT: ldd [%g1+8], %f{{.+}} -define void @f128_spill_large(<251 x fp128>* noalias sret %scalar.result, <251 x fp128>* byval %a) { +define void @f128_spill_large(<251 x fp128>* noalias sret %scalar.result, <251 x fp128>* byval(<251 x fp128>) %a) { entry: %0 = load <251 x fp128>, <251 x fp128>* %a, align 8 call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() @@ -80,7 +80,7 @@ entry: ; HARD-NEXT: nop ; SOFT: _Q_cmp -define i32 @f128_compare(fp128* byval %f0, fp128* byval %f1, i32 %a, i32 %b) { +define i32 @f128_compare(fp128* byval(fp128) %f0, fp128* byval(fp128) %f1, i32 %a, i32 %b) { entry: %0 = load fp128, fp128* %f0, align 8 %1 = load fp128, fp128* %f1, align 8 @@ -95,7 +95,7 @@ entry: ; SOFT: _Q_cmp ; SOFT: cmp -define i32 @f128_compare2(fp128* byval %f0) { +define i32 @f128_compare2(fp128* byval(fp128) %f0) { entry: %0 = load fp128, fp128* %f0, align 8 %1 = fcmp ogt fp128 %0, 0xL00000000000000000000000000000000 @@ -115,7 +115,7 @@ entry: ; BE: fabss %f0, %f0 ; EL: fabss %f3, %f3 -define void @f128_abs(fp128* noalias sret %scalar.result, fp128* byval %a) { +define void @f128_abs(fp128* noalias sret %scalar.result, fp128* byval(fp128) %a) { entry: %0 = load fp128, fp128* %a, align 8 %1 = tail call fp128 @llvm.fabs.f128(fp128 %0) @@ -242,7 +242,7 @@ entry: ; BE: fnegs %f0, %f0 ; EL: fnegs %f3, %f3 -define void @f128_neg(fp128* noalias sret %scalar.result, fp128* byval %a) { +define void @f128_neg(fp128* noalias sret %scalar.result, fp128* byval(fp128) %a) { entry: %0 = load fp128, fp128* %a, align 8 %1 = fsub fp128 0xL00000000000000008000000000000000, %0 diff --git a/test/CodeGen/SPARC/setjmp.ll b/test/CodeGen/SPARC/setjmp.ll index 17519c51627..3f81876b3f8 100644 --- a/test/CodeGen/SPARC/setjmp.ll +++ b/test/CodeGen/SPARC/setjmp.ll @@ -24,7 +24,7 @@ ; V9: st %o0, [%[[R]]+{{.+}}] ; Function Attrs: nounwind -define i32 @foo(%struct.jmpbuf_env* byval %inbuf) #0 { +define i32 @foo(%struct.jmpbuf_env* byval(%struct.jmpbuf_env) %inbuf) #0 { entry: %0 = getelementptr inbounds %struct.jmpbuf_env, %struct.jmpbuf_env* %inbuf, i32 0, i32 0 store i32 0, i32* %0, align 4, !tbaa !4 diff --git a/test/CodeGen/SPARC/zerostructcall.ll b/test/CodeGen/SPARC/zerostructcall.ll index 0a8ff65e158..2aa5e56fe89 100644 --- a/test/CodeGen/SPARC/zerostructcall.ll +++ b/test/CodeGen/SPARC/zerostructcall.ll @@ -12,11 +12,11 @@ entry: %i.addr = alloca i32, align 4 store i32 %i, i32* %i.addr, align 4 %0 = bitcast i32* %i.addr to %struct.S* - call void @struct_ptr_fn(%struct.S* byval align 1 %0) + call void @struct_ptr_fn(%struct.S* byval(%struct.S) align 1 %0) ret void } -declare void @struct_ptr_fn(%struct.S* byval align 1) +declare void @struct_ptr_fn(%struct.S* byval(%struct.S) align 1) ; CHECK-LABEL: struct_test ; CHECK: call struct_fn @@ -29,7 +29,7 @@ declare void @struct_ptr_fn(%struct.S* byval align 1) define void @struct_test() { entry: - tail call void @struct_fn(%struct.U* byval align 1 getelementptr inbounds ([1 x %struct.U], [1 x %struct.U]* @a, i32 0, i32 0)) + tail call void @struct_fn(%struct.U* byval(%struct.U) align 1 getelementptr inbounds ([1 x %struct.U], [1 x %struct.U]* @a, i32 0, i32 0)) ret void } @@ -38,14 +38,14 @@ entry: ; CHECK-NEXT: nop ; CHECK-NEXT: ret -declare void @struct_fn(%struct.U* byval align 1) +declare void @struct_fn(%struct.U* byval(%struct.U) align 1) @b = internal global [1 x %struct.U] zeroinitializer, align 1 define void @struct_arg_test() { entry: - tail call void @struct_arg_fn(%struct.U* byval align 1 getelementptr inbounds ([1 x %struct.U], [1 x %struct.U]* @b, i32 0, i32 0)) + tail call void @struct_arg_fn(%struct.U* byval(%struct.U) align 1 getelementptr inbounds ([1 x %struct.U], [1 x %struct.U]* @b, i32 0, i32 0)) ret void } -declare void @struct_arg_fn(%struct.U* byval align 1) +declare void @struct_arg_fn(%struct.U* byval(%struct.U) align 1) diff --git a/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll b/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll index 1ba08591668..a9068f01a68 100644 --- a/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll +++ b/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll @@ -48,7 +48,7 @@ do.body: ; preds = %entry %tmp20 = bitcast %struct.RRRRRRRR* %agg.tmp16 to i8* %tmp21 = bitcast %struct.RRRRRRRR* %arrayidx19 to i8* call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %tmp20, i8* align 4 %tmp21, i32 312, i1 false) - call void (i8*, i32, i8*, i8*, ...) @CLLoggingLog(i8* %tmp, i32 2, i8* getelementptr inbounds ([62 x i8], [62 x i8]* @__PRETTY_FUNCTION__._ZN12CLGll, i32 0, i32 0), i8* getelementptr inbounds ([75 x i8], [75 x i8]* @.str, i32 0, i32 0), %struct.RRRRRRRR* byval %agg.tmp, %struct.RRRRRRRR* byval %agg.tmp4, %struct.RRRRRRRR* byval %agg.tmp10, %struct.RRRRRRRR* byval %agg.tmp16) + call void (i8*, i32, i8*, i8*, ...) @CLLoggingLog(i8* %tmp, i32 2, i8* getelementptr inbounds ([62 x i8], [62 x i8]* @__PRETTY_FUNCTION__._ZN12CLGll, i32 0, i32 0), i8* getelementptr inbounds ([75 x i8], [75 x i8]* @.str, i32 0, i32 0), %struct.RRRRRRRR* byval(%struct.RRRRRRRR) %agg.tmp, %struct.RRRRRRRR* byval(%struct.RRRRRRRR) %agg.tmp4, %struct.RRRRRRRR* byval(%struct.RRRRRRRR) %agg.tmp10, %struct.RRRRRRRR* byval(%struct.RRRRRRRR) %agg.tmp16) br label %do.end do.end: ; preds = %do.body diff --git a/test/CodeGen/Thumb/PR17309.ll b/test/CodeGen/Thumb/PR17309.ll index 9815f899ac8..804803ce934 100644 --- a/test/CodeGen/Thumb/PR17309.ll +++ b/test/CodeGen/Thumb/PR17309.ll @@ -12,7 +12,7 @@ entry: %c = alloca %struct.C, align 1 %0 = getelementptr inbounds %struct.C, %struct.C* %c, i32 0, i32 0, i32 0 call void @llvm.lifetime.start.p0i8(i64 1000, i8* %0) #1 - call void @use_C(%struct.C* byval %c) #3 + call void @use_C(%struct.C* byval(%struct.C) %c) #3 call void @llvm.lifetime.end.p0i8(i64 1000, i8* %0) #1 ret void } @@ -25,7 +25,7 @@ entry: %s = alloca %struct.S, align 2 %0 = bitcast %struct.S* %s to i8* call void @llvm.lifetime.start.p0i8(i64 2000, i8* %0) #1 - call void @use_S(%struct.S* byval %s) #3 + call void @use_S(%struct.S* byval(%struct.S) %s) #3 call void @llvm.lifetime.end.p0i8(i64 2000, i8* %0) #1 ret void } @@ -38,14 +38,14 @@ entry: %i = alloca %struct.I, align 4 %0 = bitcast %struct.I* %i to i8* call void @llvm.lifetime.start.p0i8(i64 4000, i8* %0) #1 - call void @use_I(%struct.I* byval %i) #3 + call void @use_I(%struct.I* byval(%struct.I) %i) #3 call void @llvm.lifetime.end.p0i8(i64 4000, i8* %0) #1 ret void } -declare void @use_C(%struct.C* byval) #2 -declare void @use_S(%struct.S* byval) #2 -declare void @use_I(%struct.I* byval) #2 +declare void @use_C(%struct.C* byval(%struct.C)) #2 +declare void @use_S(%struct.S* byval(%struct.S)) #2 +declare void @use_I(%struct.I* byval(%struct.I)) #2 declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1 declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1 diff --git a/test/CodeGen/Thumb/emergency-spill-slot.ll b/test/CodeGen/Thumb/emergency-spill-slot.ll index e11c5bb7178..972cab0e07e 100644 --- a/test/CodeGen/Thumb/emergency-spill-slot.ll +++ b/test/CodeGen/Thumb/emergency-spill-slot.ll @@ -164,7 +164,7 @@ entry: ret void } -define void @arg_emergency_spill(i32 %n, i32 %n2, i32 %n3, i32 %n4, [252 x i32]* byval %p) { +define void @arg_emergency_spill(i32 %n, i32 %n2, i32 %n3, i32 %n4, [252 x i32]* byval([252 x i32]) %p) { ; CHECK-LABEL: arg_emergency_spill: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: .save {r4, r5, r6, r7, lr} @@ -206,7 +206,7 @@ entry: ; We currently overestimate the amount of required stack space by 16 bytes, ; so this is the largest stack that doesn't require an emergency spill slot. -define void @arg_no_emergency_spill(i32 %n, i32 %n2, i32 %n3, i32 %n4, [248 x i32]* byval %p) { +define void @arg_no_emergency_spill(i32 %n, i32 %n2, i32 %n3, i32 %n4, [248 x i32]* byval([248 x i32]) %p) { ; CHECK-LABEL: arg_no_emergency_spill: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: .save {r4, r5, r6, r7, lr} @@ -235,7 +235,7 @@ entry: ret void } -define void @aligned_emergency_spill(i32 %n, i32 %n2, i32 %n3, i32 %n4, [31 x i32]* byval %p) { +define void @aligned_emergency_spill(i32 %n, i32 %n2, i32 %n3, i32 %n4, [31 x i32]* byval([31 x i32]) %p) { ; CHECK-LABEL: aligned_emergency_spill: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: .save {r4, r5, r6, r7, lr} @@ -286,7 +286,7 @@ entry: ; This function should have no emergency spill slot, so its stack should be ; smaller than @aligned_emergency_spill. -define void @aligned_no_emergency_spill(i32 %n, i32 %n2, i32 %n3, i32 %n4, [30 x i32]* byval %p) { +define void @aligned_no_emergency_spill(i32 %n, i32 %n2, i32 %n3, i32 %n4, [30 x i32]* byval([30 x i32]) %p) { ; CHECK-LABEL: aligned_no_emergency_spill: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: .save {r4, r5, r6, r7, lr} @@ -333,7 +333,7 @@ entry: ; so we don't generate code that requires an emergency spill slot we never ; allocated. If the store gets eliminated, this testcase probably needs ; to be rewritten.) -define void @aligned_out_of_range_access(i32 %n, i32 %n2, i32 %n3, i32 %n4, [30 x i32]* byval %p) { +define void @aligned_out_of_range_access(i32 %n, i32 %n2, i32 %n3, i32 %n4, [30 x i32]* byval([30 x i32]) %p) { ; CHECK-LABEL: aligned_out_of_range_access: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: .save {r4, r5, r6, r7, lr} diff --git a/test/CodeGen/Thumb/frame-access.ll b/test/CodeGen/Thumb/frame-access.ll index 8513982da9a..d3a5871d333 100644 --- a/test/CodeGen/Thumb/frame-access.ll +++ b/test/CodeGen/Thumb/frame-access.ll @@ -13,9 +13,9 @@ declare void @llvm.va_start(i8*) declare dso_local i32 @g(i32*, i32, i32, i32, i32, i32) local_unnamed_addr -declare dso_local i32 @f(i32*, i32, i32, i32, %struct.S* byval align 4) local_unnamed_addr +declare dso_local i32 @f(i32*, i32, i32, i32, %struct.S* byval(%struct.S) align 4) local_unnamed_addr declare dso_local i32 @h(i32*, i32*, i32*) local_unnamed_addr -declare dso_local i32 @u(i32*, i32*, i32*, %struct.S* byval align 4, %struct.S* byval align 4) local_unnamed_addr +declare dso_local i32 @u(i32*, i32*, i32*, %struct.S* byval(%struct.S) align 4, %struct.S* byval(%struct.S) align 4) local_unnamed_addr ; ; Test access to arguments, passed on stack (including varargs) @@ -187,7 +187,7 @@ entry: %arraydecay = getelementptr inbounds [4 x i32], [4 x i32]* %v, i32 0, i32 0 %add = add nsw i32 %c, %b %add1 = add nsw i32 %add, %d - %call = call i32 @f(i32* nonnull %arraydecay, i32 %a, i32 %add1, i32 %e, %struct.S* byval nonnull align 4 @s) + %call = call i32 @f(i32* nonnull %arraydecay, i32 %a, i32 %add1, i32 %e, %struct.S* byval(%struct.S) nonnull align 4 @s) %add.ptr = getelementptr inbounds [4 x i32], [4 x i32]* %v, i32 0, i32 1 %add.ptr5 = getelementptr inbounds [4 x i32], [4 x i32]* %v, i32 0, i32 2 %call6 = call i32 @h(i32* nonnull %arraydecay, i32* nonnull %add.ptr, i32* nonnull %add.ptr5) @@ -226,7 +226,7 @@ entry: %1 = bitcast %struct.__va_list* %ap to i8* call void @llvm.va_start(i8* nonnull %1) %arraydecay = getelementptr inbounds [4 x i32], [4 x i32]* %v, i32 0, i32 0 - %call = call i32 @f(i32* nonnull %arraydecay, i32 %a, i32 0, i32 0, %struct.S* byval nonnull align 4 @s) + %call = call i32 @f(i32* nonnull %arraydecay, i32 %a, i32 0, i32 0, %struct.S* byval(%struct.S) nonnull align 4 @s) %add.ptr = getelementptr inbounds [4 x i32], [4 x i32]* %v, i32 0, i32 1 %add.ptr5 = getelementptr inbounds [4 x i32], [4 x i32]* %v, i32 0, i32 2 %call6 = call i32 @h(i32* nonnull %arraydecay, i32* nonnull %add.ptr, i32* nonnull %add.ptr5) @@ -389,8 +389,8 @@ entry: %2 = bitcast i32* %y to i8* %3 = bitcast i32* %z to i8* %arraydecay = getelementptr inbounds [4 x i32], [4 x i32]* %v, i32 0, i32 0 - %call = call i32 @u(i32* nonnull %arraydecay, i32* nonnull %x, i32* nonnull %y, %struct.S* byval nonnull align 4 @s, %struct.S* byval nonnull align 4 @s) - %call2 = call i32 @u(i32* nonnull %arraydecay, i32* nonnull %y, i32* nonnull %z, %struct.S* byval nonnull align 4 @s, %struct.S* byval nonnull align 4 @s) + %call = call i32 @u(i32* nonnull %arraydecay, i32* nonnull %x, i32* nonnull %y, %struct.S* byval(%struct.S) nonnull align 4 @s, %struct.S* byval(%struct.S) nonnull align 4 @s) + %call2 = call i32 @u(i32* nonnull %arraydecay, i32* nonnull %y, i32* nonnull %z, %struct.S* byval(%struct.S) nonnull align 4 @s, %struct.S* byval(%struct.S) nonnull align 4 @s) %add = add nsw i32 %call2, %call ret i32 %add } diff --git a/test/CodeGen/WebAssembly/byval.ll b/test/CodeGen/WebAssembly/byval.ll index 821f8a36d4e..b3b6884fbd0 100644 --- a/test/CodeGen/WebAssembly/byval.ll +++ b/test/CodeGen/WebAssembly/byval.ll @@ -11,11 +11,11 @@ target triple = "wasm32-unknown-unknown" %EmptyStruct = type { } declare void @ext_func(%SmallStruct*) -declare void @ext_func_empty(%EmptyStruct* byval) -declare void @ext_byval_func(%SmallStruct* byval) -declare void @ext_byval_func_align8(%SmallStruct* byval align 8) -declare void @ext_byval_func_alignedstruct(%AlignedStruct* byval) -declare void @ext_byval_func_empty(%EmptyStruct* byval) +declare void @ext_func_empty(%EmptyStruct* byval(%EmptyStruct)) +declare void @ext_byval_func(%SmallStruct* byval(%SmallStruct)) +declare void @ext_byval_func_align8(%SmallStruct* byval(%SmallStruct) align 8) +declare void @ext_byval_func_alignedstruct(%AlignedStruct* byval(%AlignedStruct)) +declare void @ext_byval_func_empty(%EmptyStruct* byval(%EmptyStruct)) ; CHECK-LABEL: byval_arg define void @byval_arg(%SmallStruct* %ptr) { @@ -34,7 +34,7 @@ define void @byval_arg(%SmallStruct* %ptr) { ; CHECK-NEXT: i32.const $push[[L5:.+]]=, 12{{$}} ; CHECK-NEXT: i32.add $push[[ARG:.+]]=, $[[SP]], $pop[[L5]]{{$}} ; CHECK-NEXT: call ext_byval_func, $pop[[ARG]]{{$}} - call void @ext_byval_func(%SmallStruct* byval %ptr) + call void @ext_byval_func(%SmallStruct* byval(%SmallStruct) %ptr) ; Restore the stack ; CHECK-NEXT: i32.const $push[[L6:.+]]=, 16 ; CHECK-NEXT: i32.add $push[[L8:.+]]=, $[[SP]], $pop[[L6]] @@ -58,7 +58,7 @@ define void @byval_arg_align8(%SmallStruct* %ptr) { ; CHECK-NEXT: i32.const $push[[L5:.+]]=, 8{{$}} ; CHECK-NEXT: i32.add $push[[ARG:.+]]=, $[[SP]], $pop[[L5]]{{$}} ; CHECK-NEXT: call ext_byval_func_align8, $pop[[ARG]]{{$}} - call void @ext_byval_func_align8(%SmallStruct* byval align 8 %ptr) + call void @ext_byval_func_align8(%SmallStruct* byval(%SmallStruct) align 8 %ptr) ret void } @@ -76,12 +76,12 @@ define void @byval_arg_double(%AlignedStruct* %ptr) { ; CHECK-NEXT: i64.store 0($[[SP]]), $pop[[L4]] ; Pass a pointer to the stack slot to the function ; CHECK-NEXT: call ext_byval_func_alignedstruct, $[[SP]] - tail call void @ext_byval_func_alignedstruct(%AlignedStruct* byval %ptr) + tail call void @ext_byval_func_alignedstruct(%AlignedStruct* byval(%AlignedStruct) %ptr) ret void } ; CHECK-LABEL: byval_param -define void @byval_param(%SmallStruct* byval align 32 %ptr) { +define void @byval_param(%SmallStruct* byval(%SmallStruct) align 32 %ptr) { ; CHECK: .functype byval_param (i32) -> () ; %ptr is just a pointer to a struct, so pass it directly through ; CHECK: call ext_func, $0 @@ -93,12 +93,12 @@ define void @byval_param(%SmallStruct* byval align 32 %ptr) { define void @byval_empty_caller(%EmptyStruct* %ptr) { ; CHECK: .functype byval_empty_caller (i32) -> () ; CHECK: call ext_byval_func_empty, $0 - call void @ext_byval_func_empty(%EmptyStruct* byval %ptr) + call void @ext_byval_func_empty(%EmptyStruct* byval(%EmptyStruct) %ptr) ret void } ; CHECK-LABEL: byval_empty_callee -define void @byval_empty_callee(%EmptyStruct* byval %ptr) { +define void @byval_empty_callee(%EmptyStruct* byval(%EmptyStruct) %ptr) { ; CHECK: .functype byval_empty_callee (i32) -> () ; CHECK: call ext_func_empty, $0 call void @ext_func_empty(%EmptyStruct* %ptr) @@ -117,8 +117,8 @@ define void @byval_empty_callee(%EmptyStruct* byval %ptr) { ; CHECK-NEXT: local.tee $push[[L9:.+]]=, $[[SP:.+]]=, $pop[[L11]]{{$}} ; CHECK-NEXT: call big_byval_callee, %big = type [131072 x i8] -declare void @big_byval_callee(%big* byval align 1) -define void @big_byval(%big* byval align 1 %x) { - call void @big_byval_callee(%big* byval align 1 %x) +declare void @big_byval_callee(%big* byval(%big) align 1) +define void @big_byval(%big* byval(%big) align 1 %x) { + call void @big_byval_callee(%big* byval(%big) align 1 %x) ret void } diff --git a/test/CodeGen/WebAssembly/indirect-import.ll b/test/CodeGen/WebAssembly/indirect-import.ll index 2c7f17e48d0..afe1ebaa978 100644 --- a/test/CodeGen/WebAssembly/indirect-import.ll +++ b/test/CodeGen/WebAssembly/indirect-import.ll @@ -60,7 +60,7 @@ declare void @extern_v() #1 declare i32 @extern_ijidf(i64, i32, double, float) #1 -declare void @extern_struct(%struct.big* byval align 8) #1 +declare void @extern_struct(%struct.big* byval(%struct.big) align 8) #1 declare void @extern_sret(%struct.big* sret) #1 diff --git a/test/CodeGen/WebAssembly/tailcall.ll b/test/CodeGen/WebAssembly/tailcall.ll index 4272c0b01a2..149105b01b8 100644 --- a/test/CodeGen/WebAssembly/tailcall.ll +++ b/test/CodeGen/WebAssembly/tailcall.ll @@ -166,9 +166,9 @@ define float @mismatched_indirect_f32(%fn %f, i32 %x, i32 %y) { ; CHECK-LABEL: mismatched_byval: ; CHECK: i32.store ; CHECK: return_call quux, $pop{{[0-9]+}}{{$}} -declare i32 @quux(i32* byval) +declare i32 @quux(i32* byval(i32)) define i32 @mismatched_byval(i32* %x) { - %v = tail call i32 @quux(i32* byval %x) + %v = tail call i32 @quux(i32* byval(i32) %x) ret i32 %v } diff --git a/test/CodeGen/X86/2008-04-24-MemCpyBug.ll b/test/CodeGen/X86/2008-04-24-MemCpyBug.ll index fb6baa20077..a450e88b8f7 100644 --- a/test/CodeGen/X86/2008-04-24-MemCpyBug.ll +++ b/test/CodeGen/X86/2008-04-24-MemCpyBug.ll @@ -5,7 +5,7 @@ %struct.S63 = type { [63 x i8] } @g1s63 = external global %struct.S63 ; <%struct.S63*> [#uses=1] -declare void @test63(%struct.S63* byval align 4 ) nounwind +declare void @test63(%struct.S63* byval(%struct.S63) align 4 ) nounwind define void @testit63_entry_2E_ce() nounwind { ; CHECK-LABEL: testit63_entry_2E_ce: @@ -26,6 +26,6 @@ define void @testit63_entry_2E_ce() nounwind { ; CHECK-NEXT: popl %esi ; CHECK-NEXT: popl %edi ; CHECK-NEXT: retl - tail call void @test63( %struct.S63* byval align 4 @g1s63 ) nounwind + tail call void @test63(%struct.S63* byval(%struct.S63) align 4 @g1s63) nounwind ret void } diff --git a/test/CodeGen/X86/2009-04-14-IllegalRegs.ll b/test/CodeGen/X86/2009-04-14-IllegalRegs.ll index 3f4af707ff8..b400a8987ca 100644 --- a/test/CodeGen/X86/2009-04-14-IllegalRegs.ll +++ b/test/CodeGen/X86/2009-04-14-IllegalRegs.ll @@ -70,7 +70,7 @@ entry: store i8 %5, i8* %7, align 1 %8 = getelementptr %struct.X, %struct.X* %xxx, i32 0, i32 0 ; [#uses=1] store i8 15, i8* %8, align 1 - %9 = call i32 (...) bitcast (i32 (%struct.X*, %struct.X*)* @f to i32 (...)*)(%struct.X* byval align 4 %xxx, %struct.X* byval align 4 %xxx) nounwind ; [#uses=1] + %9 = call i32 (...) bitcast (i32 (%struct.X*, %struct.X*)* @f to i32 (...)*)(%struct.X* byval(%struct.X) align 4 %xxx, %struct.X* byval(%struct.X) align 4 %xxx) nounwind ; [#uses=1] store i32 %9, i32* %0, align 4 %10 = load i32, i32* %0, align 4 ; [#uses=1] store i32 %10, i32* %retval, align 4 @@ -81,4 +81,4 @@ return: ; preds = %entry ret i32 %retval1 } -declare i32 @f(%struct.X* byval align 4, %struct.X* byval align 4) nounwind ssp +declare i32 @f(%struct.X* byval(%struct.X) align 4, %struct.X* byval(%struct.X) align 4) nounwind ssp diff --git a/test/CodeGen/X86/2009-11-13-VirtRegRewriterBug.ll b/test/CodeGen/X86/2009-11-13-VirtRegRewriterBug.ll index 3608e09a22b..f7efd79a521 100644 --- a/test/CodeGen/X86/2009-11-13-VirtRegRewriterBug.ll +++ b/test/CodeGen/X86/2009-11-13-VirtRegRewriterBug.ll @@ -3,7 +3,7 @@ %struct.JVTLib_100487 = type <{ i8 }> -define i32 @_Z13JVTLib_10335613JVTLib_10266513JVTLib_100579S_S_S_jPhj(i16* nocapture %ResidualX_Array.0, %struct.JVTLib_100487* nocapture byval align 4 %xqp, i16* nocapture %ResidualL_Array.0, i16* %ResidualDCZ_Array.0, i16* nocapture %ResidualACZ_FOArray.0, i32 %useFRextDequant, i8* nocapture %JVTLib_103357, i32 %use_field_scan) ssp { +define i32 @_Z13JVTLib_10335613JVTLib_10266513JVTLib_100579S_S_S_jPhj(i16* nocapture %ResidualX_Array.0, %struct.JVTLib_100487* nocapture byval(%struct.JVTLib_100487) align 4 %xqp, i16* nocapture %ResidualL_Array.0, i16* %ResidualDCZ_Array.0, i16* nocapture %ResidualACZ_FOArray.0, i32 %useFRextDequant, i8* nocapture %JVTLib_103357, i32 %use_field_scan) ssp { bb.nph: %0 = shl i32 undef, 1 ; [#uses=2] %mask133.masked.masked.masked.masked.masked.masked = or i640 undef, undef ; [#uses=1] diff --git a/test/CodeGen/X86/2010-01-18-DbgValue.ll b/test/CodeGen/X86/2010-01-18-DbgValue.ll index e95a443a1cc..01c60d4ee39 100644 --- a/test/CodeGen/X86/2010-01-18-DbgValue.ll +++ b/test/CodeGen/X86/2010-01-18-DbgValue.ll @@ -11,7 +11,7 @@ %struct.Pt = type { double, double } %struct.Rect = type { %struct.Pt, %struct.Pt } -define double @foo(%struct.Rect* byval %my_r0) nounwind ssp !dbg !1 { +define double @foo(%struct.Rect* byval(%struct.Rect) %my_r0) nounwind ssp !dbg !1 { entry: %retval = alloca double ; [#uses=2] %0 = alloca double ; [#uses=2] diff --git a/test/CodeGen/X86/2010-04-30-LocalAlloc-LandingPad.ll b/test/CodeGen/X86/2010-04-30-LocalAlloc-LandingPad.ll index 615a5727439..b210eb0f320 100644 --- a/test/CodeGen/X86/2010-04-30-LocalAlloc-LandingPad.ll +++ b/test/CodeGen/X86/2010-04-30-LocalAlloc-LandingPad.ll @@ -14,7 +14,7 @@ target triple = "i386-apple-darwin10.0.0" ; CHECK: movl %[[reg]],{{.*}}(%ebp) ## 4-byte Spill ; CHECK: calll __Z6throwsv -define i8* @_Z4test1SiS_(%struct.S* byval %s1, i32 %n, %struct.S* byval %s2) ssp personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +define i8* @_Z4test1SiS_(%struct.S* byval(%struct.S) %s1, i32 %n, %struct.S* byval(%struct.S) %s2) ssp personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { entry: %retval = alloca i8*, align 4 ; [#uses=2] %n.addr = alloca i32, align 4 ; [#uses=1] diff --git a/test/CodeGen/X86/2011-03-30-CreateFixedObjCrash.ll b/test/CodeGen/X86/2011-03-30-CreateFixedObjCrash.ll index f829c05fc56..d1b4df68963 100644 --- a/test/CodeGen/X86/2011-03-30-CreateFixedObjCrash.ll +++ b/test/CodeGen/X86/2011-03-30-CreateFixedObjCrash.ll @@ -4,7 +4,7 @@ %struct.T0 = type {} -define void @fn4(%struct.T0* byval %arg0) nounwind ssp { +define void @fn4(%struct.T0* byval(%struct.T0) %arg0) nounwind ssp { entry: ret void } diff --git a/test/CodeGen/X86/GlobalISel/x86_64-fallback.ll b/test/CodeGen/X86/GlobalISel/x86_64-fallback.ll index 8083af34736..3f5548f919d 100644 --- a/test/CodeGen/X86/GlobalISel/x86_64-fallback.ll +++ b/test/CodeGen/X86/GlobalISel/x86_64-fallback.ll @@ -17,13 +17,13 @@ define void @test_x86_fp80_dump(x86_fp80* %ptr){ } ; Check that we fallback on byVal argument -; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to translate instruction: call: ' call void @ScaleObjectOverwrite_3(%struct.PointListStruct* %index, %struct.PointListStruct* byval %index)' (in function: ScaleObjectOverwrite_2) +; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to translate instruction: call: ' call void @ScaleObjectOverwrite_3(%struct.PointListStruct* %index, %struct.PointListStruct* byval(%struct.PointListStruct) %index)' (in function: ScaleObjectOverwrite_2) ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for ScaleObjectOverwrite_2 ; FALLBACK-WITH-REPORT-OUT-LABEL: ScaleObjectOverwrite_2: %struct.PointListStruct = type { i8*, i8* } -declare void @ScaleObjectOverwrite_3(%struct.PointListStruct* %index, %struct.PointListStruct* byval %index2) +declare void @ScaleObjectOverwrite_3(%struct.PointListStruct* %index, %struct.PointListStruct* byval(%struct.PointListStruct) %index2) define void @ScaleObjectOverwrite_2(%struct.PointListStruct* %index) { entry: - call void @ScaleObjectOverwrite_3(%struct.PointListStruct* %index, %struct.PointListStruct* byval %index) + call void @ScaleObjectOverwrite_3(%struct.PointListStruct* %index, %struct.PointListStruct* byval(%struct.PointListStruct) %index) ret void } diff --git a/test/CodeGen/X86/aligned-variadic.ll b/test/CodeGen/X86/aligned-variadic.ll index d8274443e3e..bf119286c68 100644 --- a/test/CodeGen/X86/aligned-variadic.ll +++ b/test/CodeGen/X86/aligned-variadic.ll @@ -5,7 +5,7 @@ %struct.__va_list_tag = type { i32, i32, i8*, i8* } ; Function Attrs: nounwind uwtable -define void @bar(%struct.Baz* byval nocapture readnone align 8 %x, ...) { +define void @bar(%struct.Baz* byval(%struct.Baz) nocapture readnone align 8 %x, ...) { entry: %va = alloca [1 x %struct.__va_list_tag], align 16 %arraydecay = getelementptr inbounds [1 x %struct.__va_list_tag], [1 x %struct.__va_list_tag]* %va, i64 0, i64 0 diff --git a/test/CodeGen/X86/arg-copy-elide.ll b/test/CodeGen/X86/arg-copy-elide.ll index 14db84fae44..159be2f9b3a 100644 --- a/test/CodeGen/X86/arg-copy-elide.ll +++ b/test/CodeGen/X86/arg-copy-elide.ll @@ -217,7 +217,7 @@ entry: ; CHECK: retl -define void @avoid_byval(i32* byval %x) { +define void @avoid_byval(i32* byval(i32) %x) { entry: %x.p.p = alloca i32* store i32* %x, i32** %x.p.p diff --git a/test/CodeGen/X86/avoid-sfb.ll b/test/CodeGen/X86/avoid-sfb.ll index 37f235288cc..ac1e47eb154 100644 --- a/test/CodeGen/X86/avoid-sfb.ll +++ b/test/CodeGen/X86/avoid-sfb.ll @@ -724,7 +724,7 @@ if.end: ; preds = %if.then, %entry %struct.S6 = type { [4 x i32], i32, i32, i32, i32 } ; Function Attrs: nounwind uwtable -define void @test_stack(%struct.S6* noalias nocapture sret %agg.result, %struct.S6* byval nocapture readnone align 8 %s1, %struct.S6* byval nocapture align 8 %s2, i32 %x) local_unnamed_addr #0 { +define void @test_stack(%struct.S6* noalias nocapture sret %agg.result, %struct.S6* byval(%struct.S6) nocapture readnone align 8 %s1, %struct.S6* byval(%struct.S6) nocapture align 8 %s2, i32 %x) local_unnamed_addr #0 { ; CHECK-LABEL: test_stack: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movq %rdi, %rax diff --git a/test/CodeGen/X86/byval-align.ll b/test/CodeGen/X86/byval-align.ll index 8366ae38333..5f03dc83256 100644 --- a/test/CodeGen/X86/byval-align.ll +++ b/test/CodeGen/X86/byval-align.ll @@ -7,7 +7,7 @@ @.str3 = private constant [7 x i8] c"test.c\00", align 1 ; <[7 x i8]*> [#uses=1] @__PRETTY_FUNCTION__.2067 = internal constant [13 x i8] c"aligned_func\00" ; <[13 x i8]*> [#uses=1] -define void @aligned_func(%struct.S* byval align 64 %obj) nounwind { +define void @aligned_func(%struct.S* byval(%struct.S) align 64 %obj) nounwind { entry: %ptr = alloca i8* ; [#uses=3] %p = alloca i64 ; [#uses=3] @@ -51,7 +51,7 @@ entry: %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] %0 = getelementptr inbounds %struct.S, %struct.S* %s1, i32 0, i32 0 ; [#uses=1] store i32 1, i32* %0, align 4 - call void @aligned_func(%struct.S* byval align 64 %s1) nounwind + call void @aligned_func(%struct.S* byval(%struct.S) align 64 %s1) nounwind br label %return return: ; preds = %entry diff --git a/test/CodeGen/X86/byval.ll b/test/CodeGen/X86/byval.ll index 079cd61f353..0e5f63cbdbf 100644 --- a/test/CodeGen/X86/byval.ll +++ b/test/CodeGen/X86/byval.ll @@ -5,7 +5,7 @@ %struct.s = type { i64, i64, i64 } -define i64 @f(%struct.s* byval %a) { +define i64 @f(%struct.s* byval(%struct.s) %a) { ; X64-LABEL: f: ; X64: # %bb.0: # %entry ; X64-NEXT: movq 8(%rsp), %rax diff --git a/test/CodeGen/X86/byval2.ll b/test/CodeGen/X86/byval2.ll index 8e5b92b58c5..181b1779314 100644 --- a/test/CodeGen/X86/byval2.ll +++ b/test/CodeGen/X86/byval2.ll @@ -76,9 +76,9 @@ entry: store i64 %b, i64* %tmp2, align 16 %tmp4 = getelementptr %struct.s, %struct.s* %d, i32 0, i32 2 store i64 %c, i64* %tmp4, align 16 - call void @f( %struct.s* byval %d ) - call void @f( %struct.s* byval %d ) + call void @f(%struct.s* byval(%struct.s) %d) + call void @f(%struct.s* byval(%struct.s) %d) ret void } -declare void @f(%struct.s* byval) +declare void @f(%struct.s* byval(%struct.s)) diff --git a/test/CodeGen/X86/byval3.ll b/test/CodeGen/X86/byval3.ll index 790c0130886..80f2ec7fd52 100644 --- a/test/CodeGen/X86/byval3.ll +++ b/test/CodeGen/X86/byval3.ll @@ -91,9 +91,9 @@ entry: store i32 %a5, i32* %tmp8, align 16 %tmp10 = getelementptr %struct.s, %struct.s* %d, i32 0, i32 5 store i32 %a6, i32* %tmp10, align 16 - call void @f( %struct.s* byval %d) - call void @f( %struct.s* byval %d) + call void @f(%struct.s* byval(%struct.s) %d) + call void @f(%struct.s* byval(%struct.s) %d) ret void } -declare void @f(%struct.s* byval) +declare void @f(%struct.s* byval(%struct.s)) diff --git a/test/CodeGen/X86/byval4.ll b/test/CodeGen/X86/byval4.ll index 8a8713e66bc..9e6be9bd86c 100644 --- a/test/CodeGen/X86/byval4.ll +++ b/test/CodeGen/X86/byval4.ll @@ -101,9 +101,9 @@ entry: store i16 %a5, i16* %tmp8, align 16 %tmp10 = getelementptr %struct.s, %struct.s* %a, i32 0, i32 5 store i16 %a6, i16* %tmp10, align 16 - call void @f( %struct.s* byval %a ) - call void @f( %struct.s* byval %a ) + call void @f(%struct.s* byval(%struct.s) %a) + call void @f(%struct.s* byval(%struct.s) %a) ret void } -declare void @f(%struct.s* byval) +declare void @f(%struct.s* byval(%struct.s)) diff --git a/test/CodeGen/X86/byval5.ll b/test/CodeGen/X86/byval5.ll index eda8fe5ff44..c976d0d814e 100644 --- a/test/CodeGen/X86/byval5.ll +++ b/test/CodeGen/X86/byval5.ll @@ -108,9 +108,9 @@ entry: store i8 %a5, i8* %tmp8, align 8 %tmp10 = getelementptr %struct.s, %struct.s* %a, i32 0, i32 5 store i8 %a6, i8* %tmp10, align 8 - call void @f( %struct.s* byval %a ) - call void @f( %struct.s* byval %a ) + call void @f(%struct.s* byval(%struct.s) %a) + call void @f(%struct.s* byval(%struct.s) %a) ret void } -declare void @f(%struct.s* byval) +declare void @f(%struct.s* byval(%struct.s)) diff --git a/test/CodeGen/X86/byval6.ll b/test/CodeGen/X86/byval6.ll index e7e29bf54ae..09f31527a22 100644 --- a/test/CodeGen/X86/byval6.ll +++ b/test/CodeGen/X86/byval6.ll @@ -46,8 +46,8 @@ define i32 @main() nounwind { ; CHECK-NEXT: popl %ebx ; CHECK-NEXT: retl entry: - tail call void (i32, ...) @bar( i32 3, %struct.W* byval @.cpx ) nounwind - tail call void (i32, ...) @baz( i32 3, %struct.W* byval @B ) nounwind + tail call void (i32, ...) @bar( i32 3, %struct.W* byval(%struct.W) @.cpx ) nounwind + tail call void (i32, ...) @baz( i32 3, %struct.W* byval(%struct.W) @B ) nounwind ret i32 undef } diff --git a/test/CodeGen/X86/byval7.ll b/test/CodeGen/X86/byval7.ll index 718cddd504e..35a7c768721 100644 --- a/test/CodeGen/X86/byval7.ll +++ b/test/CodeGen/X86/byval7.ll @@ -32,8 +32,8 @@ entry: %s = alloca %struct.S ; <%struct.S*> [#uses=2] %tmp15 = getelementptr %struct.S, %struct.S* %s, i32 0, i32 0 ; <<2 x i64>*> [#uses=1] store <2 x i64> < i64 8589934595, i64 1 >, <2 x i64>* %tmp15, align 16 - call void @t( i32 1, %struct.S* byval %s ) nounwind + call void @t( i32 1, %struct.S* byval(%struct.S) %s) nounwind ret i32 0 } -declare void @t(i32, %struct.S* byval ) +declare void @t(i32, %struct.S* byval(%struct.S)) diff --git a/test/CodeGen/X86/crash.ll b/test/CodeGen/X86/crash.ll index 537a09b1c60..b46856374fb 100644 --- a/test/CodeGen/X86/crash.ll +++ b/test/CodeGen/X86/crash.ll @@ -1,7 +1,7 @@ ; REQUIRES: asserts ; RUN: llc -mtriple=i686-- -no-integrated-as < %s -verify-machineinstrs -precompute-phys-liveness ; RUN: llc -mtriple=x86_64-- -no-integrated-as < %s -verify-machineinstrs -precompute-phys-liveness - + ; PR6497 ; Chain and flag folding issues. @@ -276,7 +276,7 @@ bb27: ; preds = %bb7 br label %bb29 bb28: ; preds = %bb7 - call void @_ZNSt6vectorIN4llvm11MachineMoveESaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(%t10* %tmp2, %t21* byval align 4 undef, %t13* undef) + call void @_ZNSt6vectorIN4llvm11MachineMoveESaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(%t10* %tmp2, %t21* byval(%t21) align 4 undef, %t13* undef) br label %bb29 bb29: ; preds = %bb28, %bb27 @@ -300,7 +300,7 @@ bb35: ; preds = %bb34 br label %bb37 bb36: ; preds = %bb34 - call void @_ZNSt6vectorIN4llvm11MachineMoveESaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(%t10* %tmp2, %t21* byval align 4 undef, %t13* undef) + call void @_ZNSt6vectorIN4llvm11MachineMoveESaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(%t10* %tmp2, %t21* byval(%t21) align 4 undef, %t13* undef) br label %bb37 bb37: ; preds = %bb36, %bb35, %bb31 @@ -312,7 +312,7 @@ bb37: ; preds = %bb36, %bb35, %bb31 declare %t14* @_ZN4llvm9MCContext16CreateTempSymbolEv(%t2*) -declare void @_ZNSt6vectorIN4llvm11MachineMoveESaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(%t10*, %t21* byval align 4, %t13*) +declare void @_ZNSt6vectorIN4llvm11MachineMoveESaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(%t10*, %t21* byval(%t21) align 4, %t13*) declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) nounwind diff --git a/test/CodeGen/X86/dbg-baseptr.ll b/test/CodeGen/X86/dbg-baseptr.ll index 159bae12d67..cf67a518bda 100644 --- a/test/CodeGen/X86/dbg-baseptr.ll +++ b/test/CodeGen/X86/dbg-baseptr.ll @@ -14,7 +14,7 @@ target triple = "x86_64--" ; CHECK-NOT: pushq ; CHECK: movl $42, %eax ; CHECK: retq -define i32 @f0(%struct.s* byval align 8 %input) !dbg !8 { +define i32 @f0(%struct.s* byval(%struct.s) align 8 %input) !dbg !8 { call void @llvm.dbg.declare(metadata %struct.s* %input, metadata !4, metadata !17), !dbg !18 ret i32 42, !dbg !18 } @@ -36,7 +36,7 @@ define i32 @f0(%struct.s* byval align 8 %input) !dbg !8 { ; CHECK: movl $42, %eax ; CHECK: popq %rbp ; CHECK: retq -define i32 @f1(%struct.s* byval align 8 %input) !dbg !19 { +define i32 @f1(%struct.s* byval(%struct.s) align 8 %input) !dbg !19 { %val = load i64, i64* @glob ; this alloca should force FP usage. %stackspace = alloca i32, i64 %val, align 1 @@ -61,7 +61,7 @@ define i32 @f1(%struct.s* byval align 8 %input) !dbg !19 { ; CHECK: andq $-64, %rsp ; CHECK: subq $64, %rsp ; CHECK: movq %rsp, %rbx -define i32 @f2(%struct.s* byval align 8 %input) !dbg !22 { +define i32 @f2(%struct.s* byval(%struct.s) align 8 %input) !dbg !22 { %val = load i64, i64* @glob %stackspace = alloca i32, i64 %val, align 64 store i32* %stackspace, i32** @ptr diff --git a/test/CodeGen/X86/dynamic-allocas-VLAs.ll b/test/CodeGen/X86/dynamic-allocas-VLAs.ll index 37de41ea7db..cf5e2f7537c 100644 --- a/test/CodeGen/X86/dynamic-allocas-VLAs.ll +++ b/test/CodeGen/X86/dynamic-allocas-VLAs.ll @@ -152,14 +152,14 @@ declare void @t6_helper2(<8 x float>) ; the base pointer we use the original adjustment. %struct.struct_t = type { [5 x i32] } -define void @t7(i32 %size, %struct.struct_t* byval align 8 %arg1) nounwind uwtable { +define void @t7(i32 %size, %struct.struct_t* byval(%struct.struct_t) align 8 %arg1) nounwind uwtable { entry: %x = alloca i32, align 32 store i32 0, i32* %x, align 32 %0 = zext i32 %size to i64 %vla = alloca i32, i64 %0, align 16 %1 = load i32, i32* %x, align 32 - call void @bar(i32 %1, i32* %vla, %struct.struct_t* byval align 8 %arg1) + call void @bar(i32 %1, i32* %vla, %struct.struct_t* byval(%struct.struct_t) align 8 %arg1) ret void ; CHECK: _t7 @@ -181,7 +181,7 @@ entry: declare i8* @llvm.stacksave() nounwind -declare void @bar(i32, i32*, %struct.struct_t* byval align 8) +declare void @bar(i32, i32*, %struct.struct_t* byval(%struct.struct_t) align 8) declare void @llvm.stackrestore(i8*) nounwind diff --git a/test/CodeGen/X86/extract-extract.ll b/test/CodeGen/X86/extract-extract.ll index 88c735e2a08..c8870838c46 100644 --- a/test/CodeGen/X86/extract-extract.ll +++ b/test/CodeGen/X86/extract-extract.ll @@ -10,7 +10,7 @@ %crd = type { i64, %cr* } %pp = type { %cc } -define fastcc void @foo(%pp* nocapture byval %p_arg) { +define fastcc void @foo(%pp* nocapture byval(%pp) %p_arg) { ; CHECK-LABEL: foo: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: retl diff --git a/test/CodeGen/X86/fast-isel-args-fail2.ll b/test/CodeGen/X86/fast-isel-args-fail2.ll index 007ac1d9a3c..b99123d13d4 100644 --- a/test/CodeGen/X86/fast-isel-args-fail2.ll +++ b/test/CodeGen/X86/fast-isel-args-fail2.ll @@ -3,7 +3,7 @@ %struct.s0 = type { x86_fp80, x86_fp80 } ; FastISel cannot handle this case yet. Make sure that we abort. -define i8* @args_fail(%struct.s0* byval nocapture readonly align 16 %y) { +define i8* @args_fail(%struct.s0* byval(%struct.s0) nocapture readonly align 16 %y) { %1 = bitcast %struct.s0* %y to i8* ret i8* %1 } diff --git a/test/CodeGen/X86/fast-isel-call.ll b/test/CodeGen/X86/fast-isel-call.ll index 2f3f4151424..9eed939147f 100644 --- a/test/CodeGen/X86/fast-isel-call.ll +++ b/test/CodeGen/X86/fast-isel-call.ll @@ -17,10 +17,10 @@ BB2: } declare zeroext i1 @foo() nounwind -declare void @foo2(%struct.s* byval) +declare void @foo2(%struct.s* byval(%struct.s)) define void @test2(%struct.s* %d) nounwind { - call void @foo2(%struct.s* byval %d ) + call void @foo2(%struct.s* byval(%struct.s) %d ) ret void ; CHECK-LABEL: test2: ; CHECK: movl (%eax), %ecx diff --git a/test/CodeGen/X86/fast-isel-x86.ll b/test/CodeGen/X86/fast-isel-x86.ll index 3923cf9bb92..f5bc648d0bb 100644 --- a/test/CodeGen/X86/fast-isel-x86.ll +++ b/test/CodeGen/X86/fast-isel-x86.ll @@ -34,7 +34,7 @@ define x86_thiscallcc i32 @thiscallfun(i32* %this, i32 %a, i32 %b) nounwind { ; CHECK-NEXT: addl $65536, %esp ; CHECK-NEXT: pushl %ecx ; CHECK-NEXT: retl -define x86_thiscallcc void @thiscall_large(i32* %this, [65533 x i8]* byval %b) nounwind { +define x86_thiscallcc void @thiscall_large(i32* %this, [65533 x i8]* byval([65533 x i8]) %b) nounwind { ret void } diff --git a/test/CodeGen/X86/fastcc-byval.ll b/test/CodeGen/X86/fastcc-byval.ll index 1706de46111..913b7baa671 100644 --- a/test/CodeGen/X86/fastcc-byval.ll +++ b/test/CodeGen/X86/fastcc-byval.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -tailcallopt=false | FileCheck %s -; CHECK: movl 8(%esp), %eax -; CHECK: movl 8(%esp), %eax -; CHECK-NOT: movl 8(%esp), %eax +; CHECK: movl 8(%esp), %eax +; CHECK: movl 8(%esp), %eax +; CHECK-NOT: movl 8(%esp), %eax ; PR3122 ; rdar://6400815 @@ -16,9 +16,9 @@ define fastcc i32 @bar() nounwind { %V = alloca %struct.MVT %a = getelementptr %struct.MVT, %struct.MVT* %V, i32 0, i32 0 store i32 1, i32* %a - call fastcc void @foo(%struct.MVT* byval %V) nounwind + call fastcc void @foo(%struct.MVT* byval(%struct.MVT) %V) nounwind %t = load i32, i32* %a ret i32 %t } -declare fastcc void @foo(%struct.MVT* byval) +declare fastcc void @foo(%struct.MVT* byval(%struct.MVT)) diff --git a/test/CodeGen/X86/fixed-stack-di-mir.ll b/test/CodeGen/X86/fixed-stack-di-mir.ll index 30d18630083..55e7cd125d0 100644 --- a/test/CodeGen/X86/fixed-stack-di-mir.ll +++ b/test/CodeGen/X86/fixed-stack-di-mir.ll @@ -7,7 +7,7 @@ target triple = "x86_64-apple-unknown" declare void @llvm.dbg.declare(metadata, metadata, metadata) #0 -define hidden void @foo(i32* byval %dstRect) { +define hidden void @foo(i32* byval(i32) %dstRect) { ; CHECK-LABEL: name: foo entry: call void @llvm.dbg.declare(metadata i32* %dstRect, metadata !3, metadata !DIExpression()), !dbg !5 diff --git a/test/CodeGen/X86/fp-stack-retcopy.ll b/test/CodeGen/X86/fp-stack-retcopy.ll index c58b00cb0be..3fa5784e548 100644 --- a/test/CodeGen/X86/fp-stack-retcopy.ll +++ b/test/CodeGen/X86/fp-stack-retcopy.ll @@ -5,7 +5,7 @@ declare double @foo() -define double @carg({ double, double }* byval %z) nounwind { +define double @carg({ double, double }* byval({ double, double }) %z) nounwind { ; CHECK-LABEL: carg: ; CHECK: ## %bb.0: ## %entry ; CHECK-NEXT: jmp _foo ## TAILCALL diff --git a/test/CodeGen/X86/fp128-i128.ll b/test/CodeGen/X86/fp128-i128.ll index 0c6b5b55522..453e81fcfd7 100644 --- a/test/CodeGen/X86/fp128-i128.ll +++ b/test/CodeGen/X86/fp128-i128.ll @@ -440,7 +440,7 @@ declare fp128 @fabsl(fp128) #1 declare fp128 @copysignl(fp128, fp128) #1 ; Test more complicated logical operations generated from copysignl. -define void @TestCopySign({ fp128, fp128 }* noalias nocapture sret %agg.result, { fp128, fp128 }* byval nocapture readonly align 16 %z) #0 { +define void @TestCopySign({ fp128, fp128 }* noalias nocapture sret %agg.result, { fp128, fp128 }* byval({ fp128, fp128 }) nocapture readonly align 16 %z) #0 { ; SSE-LABEL: TestCopySign: ; SSE: # %bb.0: # %entry ; SSE-NEXT: pushq %rbp diff --git a/test/CodeGen/X86/frame-lowering-debug-intrinsic.ll b/test/CodeGen/X86/frame-lowering-debug-intrinsic.ll index de9d6bf93d6..973d95dffba 100644 --- a/test/CodeGen/X86/frame-lowering-debug-intrinsic.ll +++ b/test/CodeGen/X86/frame-lowering-debug-intrinsic.ll @@ -25,7 +25,7 @@ define i64 @fn1WithDebug(i64 %a) !dbg !4 { %struct.Buffer = type { i8, [63 x i8] } -define void @fn2NoDebug(%struct.Buffer* byval align 64 %p1) { +define void @fn2NoDebug(%struct.Buffer* byval(%struct.Buffer) align 64 %p1) { ret void } @@ -38,7 +38,7 @@ define void @fn2NoDebug(%struct.Buffer* byval align 64 %p1) { ; CHECK-NEXT: .cfi_def_cfa %rsp, 8 ; CHECK-NEXT: ret -define void @fn2WithDebug(%struct.Buffer* byval align 64 %p1) !dbg !8 { +define void @fn2WithDebug(%struct.Buffer* byval(%struct.Buffer) align 64 %p1) !dbg !8 { call void @llvm.dbg.declare(metadata %struct.Buffer* %p1, metadata !9, metadata !6), !dbg !10 ret void } diff --git a/test/CodeGen/X86/inline-asm-sp-clobber-memcpy.ll b/test/CodeGen/X86/inline-asm-sp-clobber-memcpy.ll index 970b9943948..006d87eaab8 100644 --- a/test/CodeGen/X86/inline-asm-sp-clobber-memcpy.ll +++ b/test/CodeGen/X86/inline-asm-sp-clobber-memcpy.ll @@ -2,12 +2,12 @@ %struct.foo = type { [88 x i8] } -declare void @bar(i8* nocapture, %struct.foo* align 4 byval) nounwind +declare void @bar(i8* nocapture, %struct.foo* align 4 byval(%struct.foo)) nounwind ; PR19012 ; Don't clobber %esi if we have inline asm that clobbers %esp. define void @test1(%struct.foo* nocapture %x, i32 %y, i8* %z) nounwind { - call void @bar(i8* %z, %struct.foo* align 4 byval %x) + call void @bar(i8* %z, %struct.foo* align 4 byval(%struct.foo) %x) call void asm sideeffect inteldialect "xor esp, esp", "=*m,~{flags},~{esp},~{esp},~{dirflag},~{fpsr},~{flags}"(i8* %z) ret void diff --git a/test/CodeGen/X86/mcu-abi.ll b/test/CodeGen/X86/mcu-abi.ll index 927f12e86bf..8a9a466d0a6 100644 --- a/test/CodeGen/X86/mcu-abi.ll +++ b/test/CodeGen/X86/mcu-abi.ll @@ -61,7 +61,7 @@ entry: ret double %rd } -define void @ret_large_struct(%struct.st12_t* noalias nocapture sret %agg.result, %struct.st12_t* byval nocapture readonly align 4 %r) #0 { +define void @ret_large_struct(%struct.st12_t* noalias nocapture sret(%struct.st12_t) %agg.result, %struct.st12_t* byval(%struct.st12_t) nocapture readonly align 4 %r) #0 { ; CHECK-LABEL: ret_large_struct: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: pushl %esi diff --git a/test/CodeGen/X86/memcpy-inline-fsrm.ll b/test/CodeGen/X86/memcpy-inline-fsrm.ll index 54f7973dea3..9480d74723f 100644 --- a/test/CodeGen/X86/memcpy-inline-fsrm.ll +++ b/test/CodeGen/X86/memcpy-inline-fsrm.ll @@ -24,8 +24,8 @@ define void @test1(i8* %a, i8* %b, i64 %s) nounwind { ; Check that we don't crash due to a memcpy size type mismatch error ("Cannot ; emit physreg copy instruction") in X86InstrInfo::copyPhysReg. %struct = type { [4096 x i8] } -declare void @foo(%struct* byval) +declare void @foo(%struct* byval(%struct)) define void @test2(%struct* %x) { - call void @foo(%struct* byval %x) + call void @foo(%struct* byval(%struct) %x) ret void } diff --git a/test/CodeGen/X86/memcpy-struct-by-value.ll b/test/CodeGen/X86/memcpy-struct-by-value.ll index 9ebe9d3b6ab..bca99064d5d 100644 --- a/test/CodeGen/X86/memcpy-struct-by-value.ll +++ b/test/CodeGen/X86/memcpy-struct-by-value.ll @@ -12,7 +12,7 @@ %struct.large = type { [4096 x i8] } -declare void @foo(%struct.large* align 8 byval) nounwind +declare void @foo(%struct.large* align 8 byval(%struct.large)) nounwind define void @test1(%struct.large* nocapture %x) nounwind { ; NOFAST32-LABEL: test1: @@ -66,7 +66,7 @@ define void @test1(%struct.large* nocapture %x) nounwind { ; FAST-NEXT: callq foo ; FAST-NEXT: addq $4104, %rsp # imm = 0x1008 ; FAST-NEXT: retq - call void @foo(%struct.large* align 8 byval %x) + call void @foo(%struct.large* align 8 byval(%struct.large) %x) ret void } @@ -123,14 +123,14 @@ define void @test2(%struct.large* nocapture %x) nounwind minsize { ; FAST-NEXT: callq foo ; FAST-NEXT: addq $4104, %rsp # imm = 0x1008 ; FAST-NEXT: retq - call void @foo(%struct.large* align 8 byval %x) + call void @foo(%struct.large* align 8 byval(%struct.large) %x) ret void } %struct.large_oddsize = type { [4095 x i8] } -declare void @foo_oddsize(%struct.large_oddsize* align 8 byval) nounwind +declare void @foo_oddsize(%struct.large_oddsize* align 8 byval(%struct.large_oddsize)) nounwind define void @test3(%struct.large_oddsize* nocapture %x) nounwind minsize { ; NOFAST32-LABEL: test3: @@ -184,7 +184,7 @@ define void @test3(%struct.large_oddsize* nocapture %x) nounwind minsize { ; FAST-NEXT: callq foo_oddsize ; FAST-NEXT: addq $4104, %rsp # imm = 0x1008 ; FAST-NEXT: retq - call void @foo_oddsize(%struct.large_oddsize* align 8 byval %x) + call void @foo_oddsize(%struct.large_oddsize* align 8 byval(%struct.large_oddsize) %x) ret void } diff --git a/test/CodeGen/X86/misched-aa-colored.ll b/test/CodeGen/X86/misched-aa-colored.ll index e118b00fd09..6c9ba57cebe 100644 --- a/test/CodeGen/X86/misched-aa-colored.ll +++ b/test/CodeGen/X86/misched-aa-colored.ll @@ -137,7 +137,7 @@ target triple = "x86_64-unknown-linux-gnu" @.str100 = external hidden unnamed_addr constant [50 x i8], align 1 @__PRETTY_FUNCTION__._ZNK4llvm6SDNode10getOperandEj = external hidden unnamed_addr constant [66 x i8], align 1 -declare { %"class.llvm::SDNode.10.610.970.1930.2050.2290.4090"*, i32 } @_ZN4llvm12SelectionDAG7getNodeEjNS_5SDLocENS_3EVTENS_7SDValueES3_(%"class.llvm::SelectionDAG.104.704.1064.2024.2144.2384.4184"*, i32, i8*, i32, i32, %"class.llvm::Type.7.607.967.1927.2047.2287.4087"*, %"class.llvm::SDValue.3.603.963.1923.2043.2283.4083"* byval align 8, %"class.llvm::SDValue.3.603.963.1923.2043.2283.4083"* byval align 8) +declare { %"class.llvm::SDNode.10.610.970.1930.2050.2290.4090"*, i32 } @_ZN4llvm12SelectionDAG7getNodeEjNS_5SDLocENS_3EVTENS_7SDValueES3_(%"class.llvm::SelectionDAG.104.704.1064.2024.2144.2384.4184"*, i32, i8*, i32, i32, %"class.llvm::Type.7.607.967.1927.2047.2287.4087"*, %"class.llvm::SDValue.3.603.963.1923.2043.2283.4083"* byval(%"class.llvm::SDValue.3.603.963.1923.2043.2283.4083") align 8, %"class.llvm::SDValue.3.603.963.1923.2043.2283.4083"* byval(%"class.llvm::SDValue.3.603.963.1923.2043.2283.4083") align 8) ; Function Attrs: noreturn nounwind declare void @__assert_fail(i8*, i8*, i32, i8*) #0 @@ -172,7 +172,7 @@ entry: ; CHECK: movl $-1, %ecx ; CHECK: callq _ZN4llvm12SelectionDAG7getNodeEjNS_5SDLocENS_3EVTENS_7SDValueES3_ - %call18 = call { %"class.llvm::SDNode.10.610.970.1930.2050.2290.4090"*, i32 } @_ZN4llvm12SelectionDAG7getNodeEjNS_5SDLocENS_3EVTENS_7SDValueES3_(%"class.llvm::SelectionDAG.104.704.1064.2024.2144.2384.4184"* undef, i32 undef, i8* undef, i32 -1, i32 %retval.sroa.0.0.copyload.i37, %"class.llvm::Type.7.607.967.1927.2047.2287.4087"* undef, %"class.llvm::SDValue.3.603.963.1923.2043.2283.4083"* byval align 8 undef, %"class.llvm::SDValue.3.603.963.1923.2043.2283.4083"* byval align 8 undef) #1 + %call18 = call { %"class.llvm::SDNode.10.610.970.1930.2050.2290.4090"*, i32 } @_ZN4llvm12SelectionDAG7getNodeEjNS_5SDLocENS_3EVTENS_7SDValueES3_(%"class.llvm::SelectionDAG.104.704.1064.2024.2144.2384.4184"* undef, i32 undef, i8* undef, i32 -1, i32 %retval.sroa.0.0.copyload.i37, %"class.llvm::Type.7.607.967.1927.2047.2287.4087"* undef, %"class.llvm::SDValue.3.603.963.1923.2043.2283.4083"* byval(%"class.llvm::SDValue.3.603.963.1923.2043.2283.4083") align 8 undef, %"class.llvm::SDValue.3.603.963.1923.2043.2283.4083"* byval(%"class.llvm::SDValue.3.603.963.1923.2043.2283.4083") align 8 undef) #1 ret { %"class.llvm::SDNode.10.610.970.1930.2050.2290.4090"*, i32 } %call18 } diff --git a/test/CodeGen/X86/movtopush.ll b/test/CodeGen/X86/movtopush.ll index 9f301a22a48..184127b8f53 100644 --- a/test/CodeGen/X86/movtopush.ll +++ b/test/CodeGen/X86/movtopush.ll @@ -14,7 +14,7 @@ declare void @oneparam(i32 %a) declare void @eightparams(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h) declare void @eightparams16(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 %f, i16 %g, i16 %h) declare void @eightparams64(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f, i64 %g, i64 %h) -declare void @struct(%struct.s* byval %a, i32 %b, i32 %c, i32 %d) +declare void @struct(%struct.s* byval(%struct.s) %a, i32 %b, i32 %c, i32 %d) declare void @inalloca(<{ %struct.s }>* inalloca) declare i8* @llvm.stacksave() @@ -169,7 +169,7 @@ entry: ret void } -; Check that pushing the addresses of globals (Or generally, things that +; Check that pushing the addresses of globals (Or generally, things that ; aren't exactly immediates) isn't broken. ; Fixes PR21878. ; NORMAL-LABEL: test6: @@ -224,7 +224,7 @@ entry: ; (because it has frame-index references), then we must resolve ; these references correctly. ; NORMAL-LABEL: test9: -; NORMAL-NOT: leal (%esp), +; NORMAL-NOT: leal (%esp), ; NORMAL: pushl $4 ; NORMAL-NEXT: pushl $3 ; NORMAL-NEXT: pushl $2 @@ -250,7 +250,7 @@ entry: call void @good(i32 1, i32 2, i32 3, i32 4) %pv = ptrtoint i32* %p to i32 %qv = ptrtoint i32* %q to i32 - call void @struct(%struct.s* byval %s, i32 6, i32 %qv, i32 %pv) + call void @struct(%struct.s* byval(%struct.s) %s, i32 6, i32 %qv, i32 %pv) ret void } @@ -277,7 +277,7 @@ define void @test10() optsize { ret void } -; We can't fold the load from the global into the push because of +; We can't fold the load from the global into the push because of ; interference from the store ; NORMAL-LABEL: test11: ; NORMAL: movl _the_global, [[EAX:%e..]] @@ -296,7 +296,7 @@ define void @test11() optsize { ret void } -; Converting one mov into a push isn't worth it when +; Converting one mov into a push isn't worth it when ; doing so forces too much overhead for other calls. ; NORMAL-LABEL: test12: ; NORMAL: pushl $8 @@ -306,7 +306,7 @@ define void @test11() optsize { ; NORMAL-NEXT: calll _good define void @test12() optsize { entry: - %s = alloca %struct.s, align 4 + %s = alloca %struct.s, align 4 call void @struct(%struct.s* %s, i32 2, i32 3, i32 4) call void @good(i32 5, i32 6, i32 7, i32 8) call void @struct(%struct.s* %s, i32 10, i32 11, i32 12) @@ -338,8 +338,8 @@ entry: ; NORMAL=NEXT: addl $16, %esp define void @test12b() optsize { entry: - %s = alloca %struct.s, align 4 - call void @good(i32 1, i32 2, i32 3, i32 4) + %s = alloca %struct.s, align 4 + call void @good(i32 1, i32 2, i32 3, i32 4) call void @struct(%struct.s* %s, i32 6, i32 7, i32 8) call void @good(i32 9, i32 10, i32 11, i32 12) ret void @@ -402,7 +402,7 @@ entry: ; NORMAL: retl %struct.A = type { i32, i32 } %struct.B = type { i8 } -declare x86_thiscallcc %struct.B* @B_ctor(%struct.B* returned, %struct.A* byval) +declare x86_thiscallcc %struct.B* @B_ctor(%struct.B* returned, %struct.A* byval(%struct.A)) declare void @B_func(%struct.B* sret, %struct.B*, i32) define void @test14(%struct.A* %a) { entry: @@ -413,7 +413,7 @@ entry: %0 = bitcast %struct.A* %a to i64* %1 = load i64, i64* %0, align 4 store i64 %1, i64* %agg.tmp, align 4 - %call = call x86_thiscallcc %struct.B* @B_ctor(%struct.B* %ref.tmp, %struct.A* byval %tmpcast) + %call = call x86_thiscallcc %struct.B* @B_ctor(%struct.B* %ref.tmp, %struct.A* byval(%struct.A) %tmpcast) %2 = getelementptr inbounds %struct.B, %struct.B* %tmp, i32 0, i32 0 call void @B_func(%struct.B* sret %tmp, %struct.B* %ref.tmp, i32 1) ret void @@ -433,17 +433,17 @@ entry: ; NORMAL-NEXT: addl $32, %esp ; ; NOPUSH-LABEL: pr34863_16 -; NOPUSH: subl $32, %esp -; NOPUSH-NEXT: movl 36(%esp), %eax -; NOPUSH-NEXT: movl %eax, 20(%esp) -; NOPUSH-NEXT: movl %eax, 16(%esp) -; NOPUSH-NEXT: movl %eax, 12(%esp) -; NOPUSH-NEXT: movl %eax, 8(%esp) -; NOPUSH-NEXT: movl %eax, 4(%esp) -; NOPUSH-NEXT: movl %eax, (%esp) +; NOPUSH: subl $32, %esp +; NOPUSH-NEXT: movl 36(%esp), %eax +; NOPUSH-NEXT: movl %eax, 20(%esp) +; NOPUSH-NEXT: movl %eax, 16(%esp) +; NOPUSH-NEXT: movl %eax, 12(%esp) +; NOPUSH-NEXT: movl %eax, 8(%esp) +; NOPUSH-NEXT: movl %eax, 4(%esp) +; NOPUSH-NEXT: movl %eax, (%esp) ; NOPUSH-NEXT: movl $65535, 28(%esp) -; NOPUSH-NEXT: andl $0, 24(%esp) -; NOPUSH-NEXT: calll _eightparams16 +; NOPUSH-NEXT: andl $0, 24(%esp) +; NOPUSH-NEXT: calll _eightparams16 ; NOPUSH-NEXT: addl $32, %esp define void @pr34863_16(i16 %x) minsize nounwind { entry: @@ -465,18 +465,18 @@ entry: ; NORMAL-NEXT: addl $32, %esp ; ; NOPUSH-LABEL: pr34863_32 -; NOPUSH: subl $32, %esp +; NOPUSH: subl $32, %esp ; NOPUSH-NEXT: movl 36(%esp), %eax ; NOPUSH-NEXT: movl %eax, 20(%esp) ; NOPUSH-NEXT: movl %eax, 16(%esp) ; NOPUSH-NEXT: movl %eax, 12(%esp) -; NOPUSH-NEXT: movl %eax, 8(%esp) -; NOPUSH-NEXT: movl %eax, 4(%esp) -; NOPUSH-NEXT: movl %eax, (%esp) -; NOPUSH-NEXT: orl $-1, 28(%esp) -; NOPUSH-NEXT: andl $0, 24(%esp) -; NOPUSH-NEXT: calll _eightparams -; NOPUSH-NEXT: addl $32, %esp +; NOPUSH-NEXT: movl %eax, 8(%esp) +; NOPUSH-NEXT: movl %eax, 4(%esp) +; NOPUSH-NEXT: movl %eax, (%esp) +; NOPUSH-NEXT: orl $-1, 28(%esp) +; NOPUSH-NEXT: andl $0, 24(%esp) +; NOPUSH-NEXT: calll _eightparams +; NOPUSH-NEXT: addl $32, %esp define void @pr34863_32(i32 %x) minsize nounwind { entry: tail call void @eightparams(i32 %x, i32 %x, i32 %x, i32 %x, i32 %x, i32 %x, i32 0, i32 -1) @@ -506,7 +506,7 @@ entry: ; NORMAL-NEXT: addl $64, %esp ; ; NOPUSH-LABEL: pr34863_64 -; NOPUSH: subl $64, %esp +; NOPUSH: subl $64, %esp ; NOPUSH-NEXT: movl 68(%esp), %eax ; NOPUSH-NEXT: movl 72(%esp), %ecx ; NOPUSH-NEXT: movl %ecx, 44(%esp) @@ -518,15 +518,15 @@ entry: ; NOPUSH-NEXT: movl %ecx, 20(%esp) ; NOPUSH-NEXT: movl %eax, 16(%esp) ; NOPUSH-NEXT: movl %ecx, 12(%esp) -; NOPUSH-NEXT: movl %eax, 8(%esp) -; NOPUSH-NEXT: movl %ecx, 4(%esp) -; NOPUSH-NEXT: movl %eax, (%esp) -; NOPUSH-NEXT: orl $-1, 60(%esp) -; NOPUSH-NEXT: orl $-1, 56(%esp) -; NOPUSH-NEXT: andl $0, 52(%esp) -; NOPUSH-NEXT: andl $0, 48(%esp) +; NOPUSH-NEXT: movl %eax, 8(%esp) +; NOPUSH-NEXT: movl %ecx, 4(%esp) +; NOPUSH-NEXT: movl %eax, (%esp) +; NOPUSH-NEXT: orl $-1, 60(%esp) +; NOPUSH-NEXT: orl $-1, 56(%esp) +; NOPUSH-NEXT: andl $0, 52(%esp) +; NOPUSH-NEXT: andl $0, 48(%esp) ; NOPUSH-NEXT: calll _eightparams64 -; NOPUSH-NEXT: addl $64, %esp +; NOPUSH-NEXT: addl $64, %esp define void @pr34863_64(i64 %x) minsize nounwind { entry: tail call void @eightparams64(i64 %x, i64 %x, i64 %x, i64 %x, i64 %x, i64 %x, i64 0, i64 -1) diff --git a/test/CodeGen/X86/movtopush.mir b/test/CodeGen/X86/movtopush.mir index 3d286bb498d..051b505813e 100644 --- a/test/CodeGen/X86/movtopush.mir +++ b/test/CodeGen/X86/movtopush.mir @@ -9,7 +9,7 @@ declare void @good(i32, i32, i32, i32) - declare void @struct(%struct.s* byval, i32, i32, i32) + declare void @struct(%struct.s* byval(%struct.s), i32, i32, i32) ; Function Attrs: optsize define void @test9() #0 { @@ -20,7 +20,7 @@ call void @good(i32 1, i32 2, i32 3, i32 4) %pv = ptrtoint i32* %p to i32 %qv = ptrtoint i32* %q to i32 - call void @struct(%struct.s* byval %s, i32 6, i32 %qv, i32 %pv) + call void @struct(%struct.s* byval(%struct.s) %s, i32 6, i32 %qv, i32 %pv) ret void } diff --git a/test/CodeGen/X86/negate-add-zero.ll b/test/CodeGen/X86/negate-add-zero.ll index 26fac9b5129..d12662ad5e0 100644 --- a/test/CodeGen/X86/negate-add-zero.ll +++ b/test/CodeGen/X86/negate-add-zero.ll @@ -983,7 +983,7 @@ declare void @_ZmiI4Mat311FixedMatrixIdLi6ELi6ELi0ELi0EEET_RK9SubMatrixIT0_ERKS3 declare %"struct.FixedMatrixBase"* @_ZN15FixedMatrixBaseIdLi6ELi6EEmIERKS0_(%"struct.FixedMatrixBase"*, %"struct.FixedMatrixBase"*) -declare void @_ZN13CDSVectorBaseI4Vec3N3CDS12DefaultAllocEEC2EiS2_(%"struct.CDSVectorBase"*, i32, %"struct.CDS::DefaultAlloc"* byval align 4) +declare void @_ZN13CDSVectorBaseI4Vec3N3CDS12DefaultAllocEEC2EiS2_(%"struct.CDSVectorBase"*, i32, %"struct.CDS::DefaultAlloc"* byval(%"struct.CDS::DefaultAlloc") align 4) declare void @_ZN13CDSVectorBaseI4Vec3N3CDS12DefaultAllocEED2Ev(%"struct.CDSVectorBase"*) diff --git a/test/CodeGen/X86/nomovtopush.ll b/test/CodeGen/X86/nomovtopush.ll index f690c2377dd..391cc3a16e7 100644 --- a/test/CodeGen/X86/nomovtopush.ll +++ b/test/CodeGen/X86/nomovtopush.ll @@ -45,13 +45,13 @@ entry: %2 = load i32, i32* @g_b, align 4, !tbaa !3 %3 = load i32, i32* @g_a, align 4, !tbaa !3 %call = tail call i32 @bar(i32 %3, i32 %2, i32 %1, i32 %0) #2 - tail call void @foo(%struct._param_str* byval nonnull align 4 @g_param) #2 + tail call void @foo(%struct._param_str* byval(%struct._param_str) nonnull align 4 @g_param) #2 ret i32 0 } declare dso_local i32 @bar(i32, i32, i32, i32) local_unnamed_addr -declare dso_local void @foo(%struct._param_str* byval align 4) local_unnamed_addr +declare dso_local void @foo(%struct._param_str* byval(%struct._param_str) align 4) local_unnamed_addr !3 = !{!4, !4, i64 0} !4 = !{!"int", !5, i64 0} diff --git a/test/CodeGen/X86/pr2656.ll b/test/CodeGen/X86/pr2656.ll index e86f55b1521..d4ab0b4d074 100644 --- a/test/CodeGen/X86/pr2656.ll +++ b/test/CodeGen/X86/pr2656.ll @@ -13,7 +13,7 @@ target triple = "i686-apple-darwin9.4.0" ; We can fold the 16-byte constant load into either 'xor' instruction, ; but we do not. It has more than one use, so it gets loaded into a register. -define void @foo(%struct.anon* byval %p) nounwind { +define void @foo(%struct.anon* byval(%struct.anon) %p) nounwind { ; CHECK-LABEL: foo: ; CHECK: ## %bb.0: ## %entry ; CHECK-NEXT: subl $28, %esp diff --git a/test/CodeGen/X86/pr30290.ll b/test/CodeGen/X86/pr30290.ll index 12b3a88eafe..5c0118a0701 100644 --- a/test/CodeGen/X86/pr30290.ll +++ b/test/CodeGen/X86/pr30290.ll @@ -12,10 +12,10 @@ target triple = "x86_64-pc-linux-gnu" %struct.face = type { [7 x i32] } ; Function Attrs: noinline nounwind uwtable -declare void @bar(%struct.face* byval nocapture readonly align 8); +declare void @bar(%struct.face* byval(%struct.face) nocapture readonly align 8); ; Function Attrs: noinline nounwind uwtable -define void @foo(%struct.face* byval nocapture align 8) local_unnamed_addr { +define void @foo(%struct.face* byval(%struct.face) nocapture align 8) local_unnamed_addr { ; CHECK-LABEL: foo: ; CHECK: # %bb.0: ; CHECK-NEXT: subq $40, %rsp @@ -35,6 +35,6 @@ define void @foo(%struct.face* byval nocapture align 8) local_unnamed_addr { store <4 x i32> , <4 x i32>* %2, align 8 %3 = getelementptr inbounds %struct.face, %struct.face* %0, i64 0, i32 0, i64 4 store i32 1, i32* %3, align 8 - call void @bar(%struct.face* byval nonnull align 8 %0) + call void @bar(%struct.face* byval(%struct.face) nonnull align 8 %0) ret void } diff --git a/test/CodeGen/X86/pr38865.ll b/test/CodeGen/X86/pr38865.ll index 1fa59aeadec..5a85ed42bf3 100644 --- a/test/CodeGen/X86/pr38865.ll +++ b/test/CodeGen/X86/pr38865.ll @@ -38,10 +38,10 @@ entry: %byval-temp = alloca %struct.a, align 8 %0 = bitcast %struct.a* %byval-temp to i8* call void @llvm.memcpy.p0i8.p0i8.i32(i8* nonnull align 8 %0, i8* align 4 bitcast (%struct.a* @c to i8*), i32 260, i1 false) - call void @d(%struct.a* byval nonnull align 8 %byval-temp) + call void @d(%struct.a* byval(%struct.a) nonnull align 8 %byval-temp) ret void } -declare void @d(%struct.a* byval align 8) local_unnamed_addr #1 +declare void @d(%struct.a* byval(%struct.a) align 8) local_unnamed_addr #1 declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture writeonly, i8* nocapture readonly, i32, i1) diff --git a/test/CodeGen/X86/sibcall-byval.ll b/test/CodeGen/X86/sibcall-byval.ll index 8f5833adf5a..999e12334c6 100644 --- a/test/CodeGen/X86/sibcall-byval.ll +++ b/test/CodeGen/X86/sibcall-byval.ll @@ -3,20 +3,20 @@ %struct.p = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } -define i32 @f(%struct.p* byval align 4 %q) nounwind ssp { +define i32 @f(%struct.p* byval(%struct.p) align 4 %q) nounwind ssp { entry: ; 32: _f: ; 32: jmp _g ; 64: _f: ; 64: jmp _g - %call = tail call i32 @g(%struct.p* byval align 4 %q) nounwind + %call = tail call i32 @g(%struct.p* byval(%struct.p) align 4 %q) nounwind ret i32 %call } -declare i32 @g(%struct.p* byval align 4) +declare i32 @g(%struct.p* byval(%struct.p) align 4) -define i32 @h(%struct.p* byval align 4 %q, i32 %r) nounwind ssp { +define i32 @h(%struct.p* byval(%struct.p) align 4 %q, i32 %r) nounwind ssp { entry: ; 32: _h: ; 32: jmp _i @@ -24,8 +24,8 @@ entry: ; 64: _h: ; 64: jmp _i - %call = tail call i32 @i(%struct.p* byval align 4 %q, i32 %r) nounwind + %call = tail call i32 @i(%struct.p* byval(%struct.p) align 4 %q, i32 %r) nounwind ret i32 %call } -declare i32 @i(%struct.p* byval align 4, i32) +declare i32 @i(%struct.p* byval(%struct.p) align 4, i32) diff --git a/test/CodeGen/X86/sibcall.ll b/test/CodeGen/X86/sibcall.ll index 98e17b1aa60..45f7a581a37 100644 --- a/test/CodeGen/X86/sibcall.ll +++ b/test/CodeGen/X86/sibcall.ll @@ -307,7 +307,7 @@ declare i32 @foo5(i32, i32, i32, i32, i32) %struct.t = type { i32, i32, i32, i32, i32 } -define i32 @t12(i32 %x, i32 %y, %struct.t* byval align 4 %z) nounwind ssp { +define i32 @t12(i32 %x, i32 %y, %struct.t* byval(%struct.t) align 4 %z) nounwind ssp { ; X86-LABEL: t12: ; X86: # %bb.0: # %entry ; X86-NEXT: cmpl $0, {{[0-9]+}}(%esp) @@ -342,14 +342,14 @@ entry: br i1 %0, label %bb2, label %bb bb: - %1 = tail call i32 @foo6(i32 %x, i32 %y, %struct.t* byval align 4 %z) nounwind + %1 = tail call i32 @foo6(i32 %x, i32 %y, %struct.t* byval(%struct.t) align 4 %z) nounwind ret i32 %1 bb2: ret i32 0 } -declare i32 @foo6(i32, i32, %struct.t* byval align 4) +declare i32 @foo6(i32, i32, %struct.t* byval(%struct.t) align 4) ; rdar://r7717598 %struct.ns = type { i32, i32 } @@ -403,13 +403,13 @@ define %struct.ns* @t13(%struct.cp* %yy) nounwind ssp { ; X32-NEXT: popq %rcx ; X32-NEXT: retq entry: - %0 = tail call fastcc %struct.ns* @foo7(%struct.cp* byval align 4 %yy, i8 signext 0) nounwind + %0 = tail call fastcc %struct.ns* @foo7(%struct.cp* byval(%struct.cp) align 4 %yy, i8 signext 0) nounwind ret %struct.ns* %0 } ; rdar://6195379 ; llvm can't do sibcall for this in 32-bit mode (yet). -declare fastcc %struct.ns* @foo7(%struct.cp* byval align 4, i8 signext) nounwind ssp +declare fastcc %struct.ns* @foo7(%struct.cp* byval(%struct.cp) align 4, i8 signext) nounwind ssp %struct.__block_descriptor = type { i64, i64 } %struct.__block_descriptor_withcopydispose = type { i64, i64, i8*, i8* } diff --git a/test/CodeGen/X86/sjlj-baseptr.ll b/test/CodeGen/X86/sjlj-baseptr.ll index 93ff0eb8abf..c32d5c5480c 100644 --- a/test/CodeGen/X86/sjlj-baseptr.ll +++ b/test/CodeGen/X86/sjlj-baseptr.ll @@ -11,7 +11,7 @@ declare void @whatever(i64, %Foo*, i8**, i8*, i8*, i32) #0 attributes #0 = { nounwind uwtable "frame-pointer"="all" } -define i32 @test1(i64 %n, %Foo* byval nocapture readnone align 8 %f) #0 { +define i32 @test1(i64 %n, %Foo* byval(%Foo) nocapture readnone align 8 %f) #0 { entry: %buf = alloca [5 x i8*], align 16 %p = alloca i8*, align 8 diff --git a/test/CodeGen/X86/ssp-data-layout.ll b/test/CodeGen/X86/ssp-data-layout.ll index 409dd7cb853..3826d942f8b 100644 --- a/test/CodeGen/X86/ssp-data-layout.ll +++ b/test/CodeGen/X86/ssp-data-layout.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -stack-symbol-ordering=0 -frame-pointer=all -mtriple=x86_64-pc-linux-gnu -mcpu=corei7 -o - | FileCheck %s ; This test is fairly fragile. The goal is to ensure that "large" stack -; objects are allocated closest to the stack protector (i.e., farthest away +; objects are allocated closest to the stack protector (i.e., farthest away ; from the Stack Pointer.) In standard SSP mode this means that large (>= ; ssp-buffer-size) arrays and structures containing such arrays are ; closet to the protector. With sspstrong and sspreq this means large @@ -165,7 +165,7 @@ entry: %coerce.dive26 = getelementptr %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d, i32 0, i32 0 %7 = bitcast [2 x i16]* %coerce.dive26 to i32* %8 = load i32, i32* %7, align 1 - call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval align 8 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2) + call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval(%struct.struct_large_nonchar) align 8 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2) ret void } @@ -176,7 +176,7 @@ entry: ; -56 large_char . arrays >= ssp-buffer-size ; -64 struct_large_char . ; -96 struct_large_nonchar . -; -100 small_non_char | Group 2, nested arrays, +; -100 small_non_char | Group 2, nested arrays, ; -102 small_char | arrays < ssp-buffer-size ; -104 struct_small_char | ; -112 struct_small_nonchar | @@ -184,7 +184,7 @@ entry: ; -120 scalar + Group 4, everything else ; -124 scalar + ; -128 scalar + -; +; ; CHECK: layout_sspstrong: ; CHECK: call{{l|q}} get_scalar1 ; CHECK: movl %eax, -120( @@ -309,14 +309,14 @@ entry: %coerce.dive26 = getelementptr %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d, i32 0, i32 0 %7 = bitcast [2 x i16]* %coerce.dive26 to i32* %8 = load i32, i32* %7, align 1 - call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval align 8 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2) + call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval(%struct.struct_large_nonchar) align 8 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2) ret void } define void @layout_sspreq() nounwind uwtable sspreq { entry: ; Expected stack layout for sspreq is the same as sspstrong -; +; ; CHECK: layout_sspreq: ; CHECK: call{{l|q}} get_scalar1 ; CHECK: movl %eax, -120( @@ -441,7 +441,7 @@ entry: %coerce.dive26 = getelementptr %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d, i32 0, i32 0 %7 = bitcast [2 x i16]* %coerce.dive26 to i32* %8 = load i32, i32* %7, align 1 - call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval align 8 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2) + call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval(%struct.struct_large_nonchar) align 8 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2) ret void } @@ -506,5 +506,5 @@ declare void @end_struct_large_nonchar() declare signext i16 @get_struct_small_nonchar() declare void @end_struct_small_nonchar() -declare void @takes_all(i64, i16, %struct.struct_large_nonchar* byval align 8, i32, i8*, i8*, i32*, i16*, i32*, i32, i32, i32) +declare void @takes_all(i64, i16, %struct.struct_large_nonchar* byval(%struct.struct_large_nonchar) align 8, i32, i8*, i8*, i32*, i16*, i32*, i32, i32, i32) declare void @takes_two(i32, i8*) diff --git a/test/CodeGen/X86/stack-align-memcpy.ll b/test/CodeGen/X86/stack-align-memcpy.ll index 25d36176621..0dbab832156 100644 --- a/test/CodeGen/X86/stack-align-memcpy.ll +++ b/test/CodeGen/X86/stack-align-memcpy.ll @@ -3,7 +3,7 @@ %struct.foo = type { [88 x i8] } -declare void @bar(i8* nocapture, %struct.foo* align 4 byval) nounwind +declare void @bar(i8* nocapture, %struct.foo* align 4 byval(%struct.foo)) nounwind declare void @baz(i8*) nounwind ; PR15249 @@ -99,7 +99,7 @@ define void @test1(%struct.foo* nocapture %x, i32 %y) nounwind { ; CHECK-NEXT: popl %ebp ; CHECK-NEXT: retl %dynalloc = alloca i8, i32 %y, align 1 - call void @bar(i8* %dynalloc, %struct.foo* align 4 byval %x) + call void @bar(i8* %dynalloc, %struct.foo* align 4 byval(%struct.foo) %x) ret void } @@ -199,7 +199,7 @@ define void @test2(%struct.foo* nocapture %x, i32 %y, i8* %z) nounwind { ; CHECK-NEXT: popl %ebx ; CHECK-NEXT: popl %ebp ; CHECK-NEXT: retl - call void @bar(i8* %z, %struct.foo* align 4 byval %x) + call void @bar(i8* %z, %struct.foo* align 4 byval(%struct.foo) %x) %dynalloc = alloca i8, i32 %y, align 1 call void @baz(i8* %dynalloc) ret void @@ -230,7 +230,7 @@ define void @test3(%struct.foo* nocapture %x, i32 %y, i8* %z) nounwind { ; CHECK-NEXT: popl %edi ; CHECK-NEXT: popl %ebp ; CHECK-NEXT: retl - call void @bar(i8* %z, %struct.foo* align 4 byval %x) + call void @bar(i8* %z, %struct.foo* align 4 byval(%struct.foo) %x) %statalloc = alloca i8, i32 8, align 1 call void @baz(i8* %statalloc) ret void diff --git a/test/CodeGen/X86/stack-align.ll b/test/CodeGen/X86/stack-align.ll index 5987828f6fd..6b11efd4d6c 100644 --- a/test/CodeGen/X86/stack-align.ll +++ b/test/CodeGen/X86/stack-align.ll @@ -10,7 +10,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3 target triple = "i686-apple-darwin8" @G = external global double -define void @test({ double, double }* byval %z, double* %P) nounwind { +define void @test({ double, double }* byval({ double, double }) %z, double* %P) nounwind { entry: %tmp3 = load double, double* @G, align 16 ; [#uses=1] %tmp4 = tail call double @fabs( double %tmp3 ) readnone ; [#uses=1] @@ -66,7 +66,7 @@ entry: ; Accessing stack parameters shouldn't assume stack alignment. Here we should ; emit two 8-byte loads, followed by two 8-byte stores. -define x86_stdcallcc void @test5(%struct.sixteen* byval nocapture readonly align 4 %s) #0 { +define x86_stdcallcc void @test5(%struct.sixteen* byval(%struct.sixteen) nocapture readonly align 4 %s) #0 { %d.sroa.0 = alloca [16 x i8], align 1 %1 = getelementptr inbounds [16 x i8], [16 x i8]* %d.sroa.0, i32 0, i32 0 call void @llvm.lifetime.start.p0i8(i64 16, i8* %1) diff --git a/test/CodeGen/X86/statepoint-call-lowering.ll b/test/CodeGen/X86/statepoint-call-lowering.ll index 3fac4b784a4..a371db4c0bb 100644 --- a/test/CodeGen/X86/statepoint-call-lowering.ll +++ b/test/CodeGen/X86/statepoint-call-lowering.ll @@ -204,9 +204,9 @@ right: %struct2 = type { i64, i64, i64 } -declare void @consume_attributes(i32, i8* nest, i32, %struct2* byval) +declare void @consume_attributes(i32, i8* nest, i32, %struct2* byval(%struct2)) -define void @test_attributes(%struct2* byval %s) gc "statepoint-example" { +define void @test_attributes(%struct2* byval(%struct2) %s) gc "statepoint-example" { ; CHECK-LABEL: test_attributes: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: pushq %rax @@ -235,7 +235,7 @@ define void @test_attributes(%struct2* byval %s) gc "statepoint-example" { entry: ; Check that arguments with attributes are lowered correctly. ; We call a function that has a nest argument and a byval argument. - %statepoint_token = call token (i64, i32, void (i32, i8*, i32, %struct2*)*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidi32p0i8i32p0s_struct2sf(i64 0, i32 0, void (i32, i8*, i32, %struct2*)* @consume_attributes, i32 4, i32 0, i32 42, i8* nest null, i32 17, %struct2* byval %s, i32 0, i32 0) + %statepoint_token = call token (i64, i32, void (i32, i8*, i32, %struct2*)*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidi32p0i8i32p0s_struct2sf(i64 0, i32 0, void (i32, i8*, i32, %struct2*)* @consume_attributes, i32 4, i32 0, i32 42, i8* nest null, i32 17, %struct2* byval(%struct2) %s, i32 0, i32 0) ret void } diff --git a/test/CodeGen/X86/statepoint-stackmap-format.ll b/test/CodeGen/X86/statepoint-stackmap-format.ll index 896aedfaeb2..370b8006b96 100644 --- a/test/CodeGen/X86/statepoint-stackmap-format.ll +++ b/test/CodeGen/X86/statepoint-stackmap-format.ll @@ -103,7 +103,7 @@ define i32 @test_spadj(i32 addrspace(1)* %p) gc "statepoint-example" { declare void @use(%struct*) -define void @test_fixed_arg(%struct* byval %x) gc "statepoint-example" { +define void @test_fixed_arg(%struct* byval(%struct) %x) gc "statepoint-example" { ; CHECK-LABEL: test_fixed_arg ; CHECK: pushq %rax ; CHECK: leaq 16(%rsp), %rdi diff --git a/test/CodeGen/X86/tailcallbyval.ll b/test/CodeGen/X86/tailcallbyval.ll index 8a0113a645a..66d88d05c48 100644 --- a/test/CodeGen/X86/tailcallbyval.ll +++ b/test/CodeGen/X86/tailcallbyval.ll @@ -3,7 +3,7 @@ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } -define fastcc i32 @tailcallee(%struct.s* byval %a) nounwind { +define fastcc i32 @tailcallee(%struct.s* byval(%struct.s) %a) nounwind { entry: %tmp2 = getelementptr %struct.s, %struct.s* %a, i32 0, i32 0 %tmp3 = load i32, i32* %tmp2 @@ -12,9 +12,9 @@ entry: ; CHECK: movl 4(%esp), %eax } -define fastcc i32 @tailcaller(%struct.s* byval %a) nounwind { +define fastcc i32 @tailcaller(%struct.s* byval(%struct.s) %a) nounwind { entry: - %tmp4 = tail call fastcc i32 @tailcallee(%struct.s* byval %a ) + %tmp4 = tail call fastcc i32 @tailcallee(%struct.s* byval(%struct.s) %a ) ret i32 %tmp4 ; CHECK: tailcaller ; CHECK: jmp tailcallee diff --git a/test/CodeGen/X86/tailcallbyval64.ll b/test/CodeGen/X86/tailcallbyval64.ll index 9df1470c67f..66ef5969317 100644 --- a/test/CodeGen/X86/tailcallbyval64.ll +++ b/test/CodeGen/X86/tailcallbyval64.ll @@ -12,7 +12,7 @@ ; A sequence of copyto/copyfrom virtual registers is used to deal with byval ; lowering appearing after moving arguments to registers. The following two ; checks verify that the register allocator changes those sequences to direct -; moves to argument register where it can (for registers that are not used in +; moves to argument register where it can (for registers that are not used in ; byval lowering - not rsi, not rdi, not rcx). ; Expect argument 4 to be moved directly to register edx. ; CHECK: movl $7, %edx @@ -30,13 +30,13 @@ i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64 } -declare fastcc i64 @tailcallee(%struct.s* byval %a, i64 %val, i64 %val2, i64 %val3, i64 %val4, i64 %val5) +declare fastcc i64 @tailcallee(%struct.s* byval(%struct.s) %a, i64 %val, i64 %val2, i64 %val3, i64 %val4, i64 %val5) -define fastcc i64 @tailcaller(i64 %b, %struct.s* byval %a) { +define fastcc i64 @tailcaller(i64 %b, %struct.s* byval(%struct.s) %a) { entry: %tmp2 = getelementptr %struct.s, %struct.s* %a, i32 0, i32 1 %tmp3 = load i64, i64* %tmp2, align 8 - %tmp4 = tail call fastcc i64 @tailcallee(%struct.s* byval %a , i64 %tmp3, i64 %b, i64 7, i64 13, i64 17) + %tmp4 = tail call fastcc i64 @tailcallee(%struct.s* byval(%struct.s) %a , i64 %tmp3, i64 %b, i64 7, i64 13, i64 17) ret i64 %tmp4 } diff --git a/test/CodeGen/X86/tailccbyval.ll b/test/CodeGen/X86/tailccbyval.ll index dbde868e511..cdb492569bf 100644 --- a/test/CodeGen/X86/tailccbyval.ll +++ b/test/CodeGen/X86/tailccbyval.ll @@ -3,7 +3,7 @@ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } -define tailcc i32 @tailcallee(%struct.s* byval %a) nounwind { +define tailcc i32 @tailcallee(%struct.s* byval(%struct.s) %a) nounwind { entry: %tmp2 = getelementptr %struct.s, %struct.s* %a, i32 0, i32 0 %tmp3 = load i32, i32* %tmp2 @@ -12,9 +12,9 @@ entry: ; CHECK: movl 4(%esp), %eax } -define tailcc i32 @tailcaller(%struct.s* byval %a) nounwind { +define tailcc i32 @tailcaller(%struct.s* byval(%struct.s) %a) nounwind { entry: - %tmp4 = tail call tailcc i32 @tailcallee(%struct.s* byval %a ) + %tmp4 = tail call tailcc i32 @tailcallee(%struct.s* byval(%struct.s) %a ) ret i32 %tmp4 ; CHECK: tailcaller ; CHECK: jmp tailcallee diff --git a/test/CodeGen/X86/tailccbyval64.ll b/test/CodeGen/X86/tailccbyval64.ll index 47d20ea972a..3363b319e37 100644 --- a/test/CodeGen/X86/tailccbyval64.ll +++ b/test/CodeGen/X86/tailccbyval64.ll @@ -12,7 +12,7 @@ ; A sequence of copyto/copyfrom virtual registers is used to deal with byval ; lowering appearing after moving arguments to registers. The following two ; checks verify that the register allocator changes those sequences to direct -; moves to argument register where it can (for registers that are not used in +; moves to argument register where it can (for registers that are not used in ; byval lowering - not rsi, not rdi, not rcx). ; Expect argument 4 to be moved directly to register edx. ; CHECK: movl $7, %edx @@ -30,13 +30,13 @@ i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64 } -declare tailcc i64 @tailcallee(%struct.s* byval %a, i64 %val, i64 %val2, i64 %val3, i64 %val4, i64 %val5) +declare tailcc i64 @tailcallee(%struct.s* byval(%struct.s) %a, i64 %val, i64 %val2, i64 %val3, i64 %val4, i64 %val5) -define tailcc i64 @tailcaller(i64 %b, %struct.s* byval %a) { +define tailcc i64 @tailcaller(i64 %b, %struct.s* byval(%struct.s) %a) { entry: %tmp2 = getelementptr %struct.s, %struct.s* %a, i32 0, i32 1 %tmp3 = load i64, i64* %tmp2, align 8 - %tmp4 = tail call tailcc i64 @tailcallee(%struct.s* byval %a , i64 %tmp3, i64 %b, i64 7, i64 13, i64 17) + %tmp4 = tail call tailcc i64 @tailcallee(%struct.s* byval(%struct.s) %a , i64 %tmp3, i64 %b, i64 7, i64 13, i64 17) ret i64 %tmp4 } diff --git a/test/CodeGen/X86/win64-byval.ll b/test/CodeGen/X86/win64-byval.ll index af2af4e6e9b..61d4b90b96f 100644 --- a/test/CodeGen/X86/win64-byval.ll +++ b/test/CodeGen/X86/win64-byval.ll @@ -1,6 +1,6 @@ ; RUN: llc -mtriple x86_64-w64-mingw32 %s -o - | FileCheck %s -declare void @foo({ float, double }* byval) +declare void @foo({ float, double }* byval({ float, double })) @G = external constant { float, double } define void @bar() @@ -14,11 +14,11 @@ define void @bar() ; CHECK: movq %rax, 40(%rsp) ; CHECK: movq %rcx, 32(%rsp) ; CHECK: leaq 32(%rsp), %rcx - call void @foo({ float, double }* byval @G) + call void @foo({ float, double }* byval({ float, double }) @G) ret void } -define void @baz({ float, double }* byval %arg) +define void @baz({ float, double }* byval({ float, double }) %arg) { ; On Win64 the byval is effectively ignored on declarations, since we do ; pass a real pointer in registers. However, by our semantics if we pass @@ -29,11 +29,11 @@ define void @baz({ float, double }* byval %arg) ; CHECK: movq %rcx, 40(%rsp) ; CHECK: movq %rax, 32(%rsp) ; CHECK: leaq 32(%rsp), %rcx - call void @foo({ float, double }* byval %arg) + call void @foo({ float, double }* byval({ float, double }) %arg) ret void } -declare void @foo2({ float, double }* byval, { float, double }* byval, { float, double }* byval, { float, double }* byval, { float, double }* byval, i64 %f) +declare void @foo2({ float, double }* byval({ float, double }), { float, double }* byval({ float, double }), { float, double }* byval({ float, double }), { float, double }* byval({ float, double }), { float, double }* byval({ float, double }), i64 %f) @data = external constant { float, double } define void @test() { @@ -57,6 +57,6 @@ define void @test() { ; CHECK-NEXT: leaq 96(%rsp), %rdx ; CHECK-NEXT: leaq 80(%rsp), %r8 ; CHECK-NEXT: leaq 64(%rsp), %r9 - call void @foo2({ float, double }* byval @G, { float, double }* byval @G, { float, double }* byval @G, { float, double }* byval @G, { float, double }* byval @G, i64 10) + call void @foo2({ float, double }* byval({ float, double }) @G, { float, double }* byval({ float, double }) @G, { float, double }* byval({ float, double }) @G, { float, double }* byval({ float, double }) @G, { float, double }* byval({ float, double }) @G, i64 10) ret void } diff --git a/test/CodeGen/X86/x86-big-ret.ll b/test/CodeGen/X86/x86-big-ret.ll index b7fed33f396..a5ad4b07205 100644 --- a/test/CodeGen/X86/x86-big-ret.ll +++ b/test/CodeGen/X86/x86-big-ret.ll @@ -2,7 +2,7 @@ target datalayout = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" target triple = "i386-pc-windows-msvc" -define x86_fastcallcc i32 @test1(i32 inreg %V, [65533 x i8]* byval %p_arg) { +define x86_fastcallcc i32 @test1(i32 inreg %V, [65533 x i8]* byval([65533 x i8]) %p_arg) { ret i32 %V } ; CHECK-LABEL: @test1@65540: @@ -12,7 +12,7 @@ define x86_fastcallcc i32 @test1(i32 inreg %V, [65533 x i8]* byval %p_arg) { ; CHECK-NEXT: pushl %ecx ; CHECK-NEXT: retl -define x86_stdcallcc void @test2([65533 x i8]* byval %p_arg) { +define x86_stdcallcc void @test2([65533 x i8]* byval([65533 x i8]) %p_arg) { ret void } ; CHECK-LABEL: _test2@65536: diff --git a/test/CodeGen/XCore/byVal.ll b/test/CodeGen/XCore/byVal.ll index fde63f41e0d..71182f359f8 100644 --- a/test/CodeGen/XCore/byVal.ll +++ b/test/CodeGen/XCore/byVal.ll @@ -6,7 +6,7 @@ ; CHECK: retsp 1 %struct.st0 = type { [0 x i32] } declare void @f0(%struct.st0*) nounwind -define void @f0Test(%struct.st0* byval %s0) nounwind { +define void @f0Test(%struct.st0* byval(%struct.st0) %s0) nounwind { entry: call void @f0(%struct.st0* %s0) nounwind ret void @@ -29,7 +29,7 @@ entry: ; CHECK: retsp 13 %struct.st1 = type { [10 x i32] } declare void @f1(%struct.st1*) nounwind -define i32 @f1Test(i32 %i, %struct.st1* byval %s1) nounwind { +define i32 @f1Test(i32 %i, %struct.st1* byval(%struct.st1) %s1) nounwind { entry: call void @f1(%struct.st1* %s1) nounwind ret i32 %i @@ -51,7 +51,7 @@ entry: ; CHECK: retsp 0 %struct.st2 = type { i32 } declare void @f2(i32, %struct.st2*) nounwind -define void @f2Test(%struct.st2* byval %s2, i32 %i, ...) nounwind { +define void @f2Test(%struct.st2* byval(%struct.st2) %s2, i32 %i, ...) nounwind { entry: call void @f2(i32 %i, %struct.st2* %s2) ret void @@ -66,7 +66,7 @@ entry: ; CHECK: bl f ; CHECK: retsp 2 declare void @f3(i8*) nounwind -define void @f3Test(i8* byval %v) nounwind { +define void @f3Test(i8* byval(i8) %v) nounwind { entry: call void @f3(i8* %v) nounwind ret void diff --git a/test/DebugInfo/Generic/2010-10-01-crash.ll b/test/DebugInfo/Generic/2010-10-01-crash.ll index 3e5f4db7d75..4c513890462 100644 --- a/test/DebugInfo/Generic/2010-10-01-crash.ll +++ b/test/DebugInfo/Generic/2010-10-01-crash.ll @@ -1,6 +1,6 @@ ; RUN: llc -O0 %s -o /dev/null -define void @CGRectStandardize(i32* sret %agg.result, i32* byval %rect) nounwind ssp !dbg !0 { +define void @CGRectStandardize(i32* sret %agg.result, i32* byval(i32) %rect) nounwind ssp !dbg !0 { entry: call void @llvm.dbg.declare(metadata i32* %rect, metadata !23, metadata !DIExpression()), !dbg !24 ret void diff --git a/test/DebugInfo/X86/byvalstruct.ll b/test/DebugInfo/X86/byvalstruct.ll index 9db9d733e8a..63f6e8a4c75 100644 --- a/test/DebugInfo/X86/byvalstruct.ll +++ b/test/DebugInfo/X86/byvalstruct.ll @@ -58,7 +58,7 @@ target triple = "x86_64-apple-macosx10.8.0" @llvm.used = appending global [5 x i8*] [i8* getelementptr inbounds ([7 x i8], [7 x i8]* @"\01L_OBJC_CLASS_NAME_", i32 0, i32 0), i8* getelementptr inbounds ([32 x i8], [32 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i32 0, i32 0), i8* getelementptr inbounds ([23 x i8], [23 x i8]* @"\01L_OBJC_METH_VAR_TYPE_", i32 0, i32 0), i8* bitcast ({ i32, i32, [1 x %struct._objc_method] }* @"\01l_OBJC_$_INSTANCE_METHODS_Bitmap" to i8*), i8* bitcast ([1 x i8*]* @"\01L_OBJC_LABEL_CLASS_$" to i8*)], section "llvm.metadata" ; Function Attrs: ssp uwtable -define internal i8* @"\01-[Bitmap initWithCopy:andInfo:andLength:]"(%0* %self, i8* %_cmd, %0* %otherBitmap, %struct.ImageInfo* byval align 8 %info, i64 %length) #0 !dbg !7 { +define internal i8* @"\01-[Bitmap initWithCopy:andInfo:andLength:]"(%0* %self, i8* %_cmd, %0* %otherBitmap, %struct.ImageInfo* byval(%struct.ImageInfo) align 8 %info, i64 %length) #0 !dbg !7 { entry: %retval = alloca i8*, align 8 %self.addr = alloca %0*, align 8 diff --git a/test/DebugInfo/X86/dbg-byval-parameter.ll b/test/DebugInfo/X86/dbg-byval-parameter.ll index fdf5d49b31a..52519424de4 100644 --- a/test/DebugInfo/X86/dbg-byval-parameter.ll +++ b/test/DebugInfo/X86/dbg-byval-parameter.ll @@ -4,7 +4,7 @@ %struct.Pt = type { double, double } %struct.Rect = type { %struct.Pt, %struct.Pt } -define double @foo(%struct.Rect* byval %my_r0) nounwind ssp !dbg !1 { +define double @foo(%struct.Rect* byval(%struct.Rect) %my_r0) nounwind ssp !dbg !1 { entry: %retval = alloca double ; [#uses=2] %0 = alloca double ; [#uses=2] diff --git a/test/DebugInfo/X86/double-declare.ll b/test/DebugInfo/X86/double-declare.ll index da6c4d04ebb..303d86353b7 100644 --- a/test/DebugInfo/X86/double-declare.ll +++ b/test/DebugInfo/X86/double-declare.ll @@ -8,7 +8,7 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) -define void @f(i32* byval %p, i1 %c) !dbg !5 { +define void @f(i32* byval(i32) %p, i1 %c) !dbg !5 { br i1 %c, label %x, label %y x: diff --git a/test/DebugInfo/X86/pieces-2.ll b/test/DebugInfo/X86/pieces-2.ll index 55ada6e472a..80003a3f5e7 100644 --- a/test/DebugInfo/X86/pieces-2.ll +++ b/test/DebugInfo/X86/pieces-2.ll @@ -29,7 +29,7 @@ target triple = "x86_64-apple-macosx10.9.0" %struct.Inner = type { i32, i64 } ; Function Attrs: nounwind ssp uwtable -define i32 @foo(%struct.Outer* byval align 8 %outer) #0 !dbg !4 { +define i32 @foo(%struct.Outer* byval(%struct.Outer) align 8 %outer) #0 !dbg !4 { entry: call void @llvm.dbg.declare(metadata %struct.Outer* %outer, metadata !25, metadata !DIExpression()), !dbg !26 %i1.sroa.0.0..sroa_idx = getelementptr inbounds %struct.Outer, %struct.Outer* %outer, i64 0, i32 0, i64 1, i32 0, !dbg !27 diff --git a/test/DebugInfo/X86/safestack-byval.ll b/test/DebugInfo/X86/safestack-byval.ll index a653cd78b91..7e4d9fc5ab5 100644 --- a/test/DebugInfo/X86/safestack-byval.ll +++ b/test/DebugInfo/X86/safestack-byval.ll @@ -21,7 +21,7 @@ @__safestack_unsafe_stack_ptr = external thread_local(initialexec) global i8* ; Function Attrs: norecurse nounwind readonly safestack uwtable -define i32 @_Z1f1Sm(%struct.S* byval nocapture readonly align 8 %zzz, i64 %len) #0 !dbg !12 { +define i32 @_Z1f1Sm(%struct.S* byval(%struct.S) nocapture readonly align 8 %zzz, i64 %len) #0 !dbg !12 { entry: %unsafe_stack_ptr = load i8*, i8** @__safestack_unsafe_stack_ptr, !dbg !22 %unsafe_stack_static_top = getelementptr i8, i8* %unsafe_stack_ptr, i32 -400, !dbg !22 diff --git a/test/DebugInfo/X86/sroasplit-1.ll b/test/DebugInfo/X86/sroasplit-1.ll index 2372ab6428c..0ec368130da 100644 --- a/test/DebugInfo/X86/sroasplit-1.ll +++ b/test/DebugInfo/X86/sroasplit-1.ll @@ -34,7 +34,7 @@ target triple = "x86_64-apple-macosx10.9.0" %struct.Inner = type { i32, i64 } ; Function Attrs: nounwind ssp uwtable -define i32 @foo(%struct.Outer* byval align 8 %outer) #0 !dbg !4 { +define i32 @foo(%struct.Outer* byval(%struct.Outer) align 8 %outer) #0 !dbg !4 { entry: %i1 = alloca %struct.Inner, align 8 call void @llvm.dbg.declare(metadata %struct.Outer* %outer, metadata !25, metadata !2), !dbg !26 diff --git a/test/DebugInfo/X86/sroasplit-4.ll b/test/DebugInfo/X86/sroasplit-4.ll index 6e47cb7d869..0d5594ef867 100644 --- a/test/DebugInfo/X86/sroasplit-4.ll +++ b/test/DebugInfo/X86/sroasplit-4.ll @@ -78,7 +78,7 @@ if.end: ; preds = %entry %4 = bitcast %struct.r* %agg.tmp to i8*, !dbg !33 %5 = bitcast %struct.r* %r to i8*, !dbg !33 call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %4, i8* align 8 %5, i64 40, i1 false), !dbg !33 - %call4 = call i32 @_Z7call_me1r(%struct.r* byval align 8 %agg.tmp), !dbg !33 + %call4 = call i32 @_Z7call_me1r(%struct.r* byval(%struct.r) align 8 %agg.tmp), !dbg !33 store i32 %call4, i32* %retval, !dbg !33 br label %return, !dbg !33 @@ -95,7 +95,7 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) #2 ; Function Attrs: nounwind declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i1) #3 -declare i32 @_Z7call_me1r(%struct.r* byval align 8) +declare i32 @_Z7call_me1r(%struct.r* byval(%struct.r) align 8) attributes #0 = { nounwind } attributes #2 = { nounwind readnone } diff --git a/test/Instrumentation/AddressSanitizer/stack-poisoning-byval-args.ll b/test/Instrumentation/AddressSanitizer/stack-poisoning-byval-args.ll index 616c18ea09d..986dfcb5198 100644 --- a/test/Instrumentation/AddressSanitizer/stack-poisoning-byval-args.ll +++ b/test/Instrumentation/AddressSanitizer/stack-poisoning-byval-args.ll @@ -18,7 +18,7 @@ declare i32 @bar(%struct.A*) ; Test behavior for named argument with explicit alignment. The memcpy and ; alloca alignments should match the explicit alignment of 64. -define void @foo(%struct.A* byval align 64 %a) sanitize_address { +define void @foo(%struct.A* byval(%struct.A) align 64 %a) sanitize_address { entry: ; CHECK-LABEL: foo ; CHECK: call i64 @__asan_stack_malloc @@ -39,7 +39,7 @@ entry: ; minimum alignment of 4 bytes since struct.A contains i32s which have 4-byte ; alignment. However, the alloca alignment will be 32 since that is the value ; passed via the -asan-realign-stack option, which is greater than 4. -define void @baz(%struct.A* byval) sanitize_address { +define void @baz(%struct.A* byval(%struct.A)) sanitize_address { entry: ; CHECK-LABEL: baz ; CHECK: call i64 @__asan_stack_malloc diff --git a/test/Instrumentation/BoundsChecking/simple.ll b/test/Instrumentation/BoundsChecking/simple.ll index c95bfbdd4fe..994a5dc2271 100644 --- a/test/Instrumentation/BoundsChecking/simple.ll +++ b/test/Instrumentation/BoundsChecking/simple.ll @@ -133,7 +133,7 @@ define void @f10(i64 %x, i64 %y) nounwind { } ; CHECK: @f11 -define void @f11(i128* byval %x) nounwind { +define void @f11(i128* byval(i128) %x) nounwind { %1 = bitcast i128* %x to i8* %2 = getelementptr inbounds i8, i8* %1, i64 16 ; CHECK: br label @@ -142,7 +142,7 @@ define void @f11(i128* byval %x) nounwind { } ; CHECK: @f11_as1 -define void @f11_as1(i128 addrspace(1)* byval %x) nounwind { +define void @f11_as1(i128 addrspace(1)* byval(i128) %x) nounwind { %1 = bitcast i128 addrspace(1)* %x to i8 addrspace(1)* %2 = getelementptr inbounds i8, i8 addrspace(1)* %1, i16 16 ; CHECK: br label diff --git a/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64.ll b/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64.ll index 33f3d82c368..4c68d4439a6 100644 --- a/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64.ll +++ b/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64.ll @@ -77,7 +77,7 @@ define i32 @bar5() { ; Check 8-aligned byval. define i32 @bar6([2 x i64]* %arg) { - %1 = call i32 (i32, ...) @foo(i32 0, [2 x i64]* byval align 8 %arg) + %1 = call i32 (i32, ...) @foo(i32 0, [2 x i64]* byval([2 x i64]) align 8 %arg) ret i32 %1 } @@ -87,7 +87,7 @@ define i32 @bar6([2 x i64]* %arg) { ; Check 16-aligned byval. define i32 @bar7([4 x i64]* %arg) { - %1 = call i32 (i32, ...) @foo(i32 0, [4 x i64]* byval align 16 %arg) + %1 = call i32 (i32, ...) @foo(i32 0, [4 x i64]* byval([4 x i64]) align 16 %arg) ret i32 %1 } diff --git a/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64le.ll b/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64le.ll index ac8df55fee4..87b429aa5ef 100644 --- a/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64le.ll +++ b/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64le.ll @@ -76,7 +76,7 @@ define i32 @bar5() { ; Check 8-aligned byval. define i32 @bar6([2 x i64]* %arg) { - %1 = call i32 (i32, ...) @foo(i32 0, [2 x i64]* byval align 8 %arg) + %1 = call i32 (i32, ...) @foo(i32 0, [2 x i64]* byval([2 x i64]) align 8 %arg) ret i32 %1 } @@ -86,7 +86,7 @@ define i32 @bar6([2 x i64]* %arg) { ; Check 16-aligned byval. define i32 @bar7([4 x i64]* %arg) { - %1 = call i32 (i32, ...) @foo(i32 0, [4 x i64]* byval align 16 %arg) + %1 = call i32 (i32, ...) @foo(i32 0, [4 x i64]* byval([4 x i64]) align 16 %arg) ret i32 %1 } diff --git a/test/Instrumentation/MemorySanitizer/byval-alignment.ll b/test/Instrumentation/MemorySanitizer/byval-alignment.ll index acf9c27fb5b..71db2356ac2 100644 --- a/test/Instrumentation/MemorySanitizer/byval-alignment.ll +++ b/test/Instrumentation/MemorySanitizer/byval-alignment.ll @@ -14,8 +14,8 @@ target triple = "x86_64-unknown-linux-gnu" define void @Caller() sanitize_memory { entry: %agg.tmp = alloca %struct.S, align 16 - call void @Callee(i32 1, %struct.S* byval align 16 %agg.tmp) + call void @Callee(i32 1, %struct.S* byval(%struct.S) align 16 %agg.tmp) ret void } -declare void @Callee(i32, %struct.S* byval align 16) +declare void @Callee(i32, %struct.S* byval(%struct.S) align 16) diff --git a/test/Instrumentation/MemorySanitizer/check_access_address.ll b/test/Instrumentation/MemorySanitizer/check_access_address.ll index c4c295c7972..d69d898369e 100644 --- a/test/Instrumentation/MemorySanitizer/check_access_address.ll +++ b/test/Instrumentation/MemorySanitizer/check_access_address.ll @@ -8,7 +8,7 @@ target triple = "x86_64-unknown-linux-gnu" ; Test byval argument shadow alignment -define <2 x i64> @ByValArgumentShadowLargeAlignment(<2 x i64>* byval %p) sanitize_memory { +define <2 x i64> @ByValArgumentShadowLargeAlignment(<2 x i64>* byval(<2 x i64>) %p) sanitize_memory { entry: %x = load <2 x i64>, <2 x i64>* %p ret <2 x i64> %x @@ -19,7 +19,7 @@ entry: ; CHECK: ret <2 x i64> -define i16 @ByValArgumentShadowSmallAlignment(i16* byval %p) sanitize_memory { +define i16 @ByValArgumentShadowSmallAlignment(i16* byval(i16) %p) sanitize_memory { entry: %x = load i16, i16* %p ret i16 %x diff --git a/test/Instrumentation/MemorySanitizer/msan_basic.ll b/test/Instrumentation/MemorySanitizer/msan_basic.ll index 6abdb4486a4..6a33b398ef6 100644 --- a/test/Instrumentation/MemorySanitizer/msan_basic.ll +++ b/test/Instrumentation/MemorySanitizer/msan_basic.ll @@ -94,7 +94,7 @@ declare void @foo(...) ; CHECK-ORIGINS: %[[ORIGIN:.*]] = load ; CHECK: call void @__msan_warning_with_origin_noreturn(i32 ; CHECK-ORIGINS-SAME %[[ORIGIN]]) -; CHECK-CONT: +; CHECK-CONT: ; CHECK-NEXT: unreachable ; CHECK: br i1 %tobool ; CHECK: ret void @@ -920,7 +920,7 @@ entry: %agg.tmp.sroa.2.0.copyload = load i64, i64* %agg.tmp.sroa.2.0..sroa_cast, align 4 %1 = bitcast %struct.StructByVal* %agg.tmp2 to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %1, i8* align 4 %0, i64 16, i1 false) - call void (i32, ...) @VAArgStructFn(i32 undef, i64 %agg.tmp.sroa.0.0.copyload, i64 %agg.tmp.sroa.2.0.copyload, i64 %agg.tmp.sroa.0.0.copyload, i64 %agg.tmp.sroa.2.0.copyload, %struct.StructByVal* byval align 8 %agg.tmp2) + call void (i32, ...) @VAArgStructFn(i32 undef, i64 %agg.tmp.sroa.0.0.copyload, i64 %agg.tmp.sroa.2.0.copyload, i64 %agg.tmp.sroa.0.0.copyload, i64 %agg.tmp.sroa.2.0.copyload, %struct.StructByVal* byval(%struct.StructByVal) align 8 %agg.tmp2) ret void } @@ -955,7 +955,7 @@ entry: %agg.tmp.sroa.2.0.copyload = load i64, i64* %agg.tmp.sroa.2.0..sroa_cast, align 4 %1 = bitcast %struct.StructByVal* %agg.tmp2 to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %1, i8* align 4 %0, i64 16, i1 false) - call void (i32, ...) @VAArgStructFn(i32 undef, i64 %agg.tmp.sroa.0.0.copyload, i64 %agg.tmp.sroa.2.0.copyload, i64 %agg.tmp.sroa.0.0.copyload, i64 %agg.tmp.sroa.2.0.copyload, %struct.StructByVal* byval align 8 %agg.tmp2) + call void (i32, ...) @VAArgStructFn(i32 undef, i64 %agg.tmp.sroa.0.0.copyload, i64 %agg.tmp.sroa.2.0.copyload, i64 %agg.tmp.sroa.0.0.copyload, i64 %agg.tmp.sroa.2.0.copyload, %struct.StructByVal* byval(%struct.StructByVal) align 8 %agg.tmp2) ret void } diff --git a/test/Linker/func-attrs-a.ll b/test/Linker/func-attrs-a.ll index d5495e1e3fd..4f43c6dbc53 100644 --- a/test/Linker/func-attrs-a.ll +++ b/test/Linker/func-attrs-a.ll @@ -1,13 +1,13 @@ ; RUN: llvm-link %s %p/func-attrs-b.ll -S -o - | FileCheck %s ; PR2382 -; CHECK: call void @check0(%struct.S0* sret null, %struct.S0* byval align 4 null, %struct.S0* align 4 null, %struct.S0* byval align 4 null) -; CHECK: define void @check0(%struct.S0* sret %agg.result, %struct.S0* byval %arg0, %struct.S0* %arg1, %struct.S0* byval %arg2) +; CHECK: call void @check0(%struct.S0* sret null, %struct.S0* byval(%struct.S0) align 4 null, %struct.S0* align 4 null, %struct.S0* byval(%struct.S0) align 4 null) +; CHECK: define void @check0(%struct.S0* sret %agg.result, %struct.S0* byval(%struct.S0) %arg0, %struct.S0* %arg1, %struct.S0* byval(%struct.S0) %arg2) %struct.S0 = type <{ i8, i8, i8, i8 }> define void @a() { - call void @check0(%struct.S0* sret null, %struct.S0* byval align 4 null, %struct.S0* align 4 null, %struct.S0* byval align 4 null) + call void @check0(%struct.S0* sret null, %struct.S0* byval(%struct.S0) align 4 null, %struct.S0* align 4 null, %struct.S0* byval(%struct.S0) align 4 null) ret void } diff --git a/test/Linker/func-attrs-b.ll b/test/Linker/func-attrs-b.ll index df78e5f54ab..fad59c22925 100644 --- a/test/Linker/func-attrs-b.ll +++ b/test/Linker/func-attrs-b.ll @@ -3,6 +3,6 @@ %struct.S0 = type <{ i8, i8, i8, i8 }> -define void @check0(%struct.S0* sret %agg.result, %struct.S0* byval %arg0, %struct.S0* %arg1, %struct.S0* byval %arg2) { +define void @check0(%struct.S0* sret %agg.result, %struct.S0* byval(%struct.S0) %arg0, %struct.S0* %arg1, %struct.S0* byval(%struct.S0) %arg2) { ret void } diff --git a/test/Transforms/ArgumentPromotion/attrs.ll b/test/Transforms/ArgumentPromotion/attrs.ll index 07b96038d62..9fc5023e786 100644 --- a/test/Transforms/ArgumentPromotion/attrs.ll +++ b/test/Transforms/ArgumentPromotion/attrs.ll @@ -5,9 +5,9 @@ %struct.ss = type { i32, i64 } ; Don't drop 'byval' on %X here. -define internal void @f(%struct.ss* byval %b, i32* byval %X, i32 %i) nounwind { +define internal void @f(%struct.ss* byval(%struct.ss) %b, i32* byval(i32) %X, i32 %i) nounwind { ; CHECK-LABEL: define {{[^@]+}}@f -; CHECK-SAME: (i32 [[B_0:%.*]], i64 [[B_1:%.*]], i32* byval [[X:%.*]], i32 [[I:%.*]]) +; CHECK-SAME: (i32 [[B_0:%.*]], i64 [[B_1:%.*]], i32* byval(i32) [[X:%.*]], i32 [[I:%.*]]) ; CHECK-NEXT: entry: ; CHECK-NEXT: [[B:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 ; CHECK-NEXT: [[DOT0:%.*]] = getelementptr [[STRUCT_SS]], %struct.ss* [[B]], i32 0, i32 0 @@ -46,7 +46,7 @@ define i32 @test(i32* %X) { ; CHECK-NEXT: [[S_0_VAL:%.*]] = load i32, i32* [[S_0]], align 4 ; CHECK-NEXT: [[S_1:%.*]] = getelementptr [[STRUCT_SS]], %struct.ss* [[S]], i32 0, i32 1 ; CHECK-NEXT: [[S_1_VAL:%.*]] = load i64, i64* [[S_1]], align 4 -; CHECK-NEXT: call void @f(i32 [[S_0_VAL]], i64 [[S_1_VAL]], i32* byval [[X]], i32 zeroext 0) +; CHECK-NEXT: call void @f(i32 [[S_0_VAL]], i64 [[S_1_VAL]], i32* byval(i32) [[X]], i32 zeroext 0) ; CHECK-NEXT: ret i32 0 ; entry: @@ -56,7 +56,7 @@ entry: %tmp4 = getelementptr %struct.ss, %struct.ss* %S, i32 0, i32 1 store i64 2, i64* %tmp4, align 4 - call void @f( %struct.ss* byval %S, i32* byval %X, i32 zeroext 0) + call void @f(%struct.ss* byval(%struct.ss) %S, i32* byval(i32) %X, i32 zeroext 0) ret i32 0 } diff --git a/test/Transforms/ArgumentPromotion/byval-2.ll b/test/Transforms/ArgumentPromotion/byval-2.ll index f95493f6068..cab1957c246 100644 --- a/test/Transforms/ArgumentPromotion/byval-2.ll +++ b/test/Transforms/ArgumentPromotion/byval-2.ll @@ -7,9 +7,9 @@ %struct.ss = type { i32, i64 } -define internal void @f(%struct.ss* byval %b, i32* byval %X) nounwind { +define internal void @f(%struct.ss* byval(%struct.ss) %b, i32* byval(i32) %X) nounwind { ; CHECK-LABEL: define {{[^@]+}}@f -; CHECK-SAME: (i32 [[B_0:%.*]], i64 [[B_1:%.*]], i32* byval [[X:%.*]]) +; CHECK-SAME: (i32 [[B_0:%.*]], i64 [[B_1:%.*]], i32* byval(i32) [[X:%.*]]) ; CHECK-NEXT: entry: ; CHECK-NEXT: [[B:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 ; CHECK-NEXT: [[DOT0:%.*]] = getelementptr [[STRUCT_SS]], %struct.ss* [[B]], i32 0, i32 0 @@ -46,7 +46,7 @@ define i32 @test(i32* %X) { ; CHECK-NEXT: [[S_0_VAL:%.*]] = load i32, i32* [[S_0]], align 4 ; CHECK-NEXT: [[S_1:%.*]] = getelementptr [[STRUCT_SS]], %struct.ss* [[S]], i32 0, i32 1 ; CHECK-NEXT: [[S_1_VAL:%.*]] = load i64, i64* [[S_1]], align 4 -; CHECK-NEXT: call void @f(i32 [[S_0_VAL]], i64 [[S_1_VAL]], i32* byval [[X]]) +; CHECK-NEXT: call void @f(i32 [[S_0_VAL]], i64 [[S_1_VAL]], i32* byval(i32) [[X]]) ; CHECK-NEXT: ret i32 0 ; entry: @@ -55,6 +55,6 @@ entry: store i32 1, i32* %tmp1, align 8 %tmp4 = getelementptr %struct.ss, %struct.ss* %S, i32 0, i32 1 store i64 2, i64* %tmp4, align 4 - call void @f( %struct.ss* byval %S, i32* byval %X) + call void @f(%struct.ss* byval(%struct.ss) %S, i32* byval(i32) %X) ret i32 0 } diff --git a/test/Transforms/ArgumentPromotion/byval.ll b/test/Transforms/ArgumentPromotion/byval.ll index 359ce4ef848..1c7f8224c6d 100644 --- a/test/Transforms/ArgumentPromotion/byval.ll +++ b/test/Transforms/ArgumentPromotion/byval.ll @@ -6,7 +6,7 @@ target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:1 %struct.ss = type { i32, i64 } -define internal void @f(%struct.ss* byval %b) nounwind { +define internal void @f(%struct.ss* byval(%struct.ss) %b) nounwind { ; CHECK-LABEL: define {{[^@]+}}@f ; CHECK-SAME: (i32 [[B_0:%.*]], i64 [[B_1:%.*]]) ; CHECK-NEXT: entry: @@ -30,7 +30,7 @@ entry: } -define internal void @g(%struct.ss* byval align 32 %b) nounwind { +define internal void @g(%struct.ss* byval(%struct.ss) align 32 %b) nounwind { ; CHECK-LABEL: define {{[^@]+}}@g ; CHECK-SAME: (i32 [[B_0:%.*]], i64 [[B_1:%.*]]) ; CHECK-NEXT: entry: @@ -80,8 +80,8 @@ entry: store i32 1, i32* %tmp1, align 8 %tmp4 = getelementptr %struct.ss, %struct.ss* %S, i32 0, i32 1 store i64 2, i64* %tmp4, align 4 - call void @f(%struct.ss* byval %S) nounwind - call void @g(%struct.ss* byval %S) nounwind + call void @f(%struct.ss* byval(%struct.ss) %S) nounwind + call void @g(%struct.ss* byval(%struct.ss) %S) nounwind ret i32 0 } diff --git a/test/Transforms/ArgumentPromotion/dbg.ll b/test/Transforms/ArgumentPromotion/dbg.ll index 1da97c3144e..56f0fe4f132 100644 --- a/test/Transforms/ArgumentPromotion/dbg.ll +++ b/test/Transforms/ArgumentPromotion/dbg.ll @@ -18,7 +18,7 @@ define internal void @test(i32** %X) !dbg !2 { %struct.pair = type { i32, i32 } -define internal void @test_byval(%struct.pair* byval %P) { +define internal void @test_byval(%struct.pair* byval(%struct.pair) %P) { ; CHECK-LABEL: define {{[^@]+}}@test_byval ; CHECK-SAME: (i32 [[P_0:%.*]], i32 [[P_1:%.*]]) ; CHECK-NEXT: [[P:%.*]] = alloca [[STRUCT_PAIR:%.*]], align 8 diff --git a/test/Transforms/ArgumentPromotion/fp80.ll b/test/Transforms/ArgumentPromotion/fp80.ll index dd7cebf5a1c..7f39f7e7c5f 100644 --- a/test/Transforms/ArgumentPromotion/fp80.ll +++ b/test/Transforms/ArgumentPromotion/fp80.ll @@ -16,7 +16,7 @@ target triple = "x86_64-unknown-linux-gnu" define void @run() { ; CHECK-LABEL: define {{[^@]+}}@run() ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = tail call i8 @UseLongDoubleUnsafely(%union.u* byval align 16 bitcast (%struct.s* @b to %union.u*)) +; CHECK-NEXT: [[TMP0:%.*]] = tail call i8 @UseLongDoubleUnsafely(%union.u* byval(%union.u) align 16 bitcast (%struct.s* @b to %union.u*)) ; CHECK-NEXT: [[DOT0:%.*]] = getelementptr [[UNION_U:%.*]], %union.u* bitcast (%struct.s* @b to %union.u*), i32 0, i32 0 ; CHECK-NEXT: [[DOT0_VAL:%.*]] = load x86_fp80, x86_fp80* [[DOT0]] ; CHECK-NEXT: [[TMP1:%.*]] = tail call x86_fp80 @UseLongDoubleSafely(x86_fp80 [[DOT0_VAL]]) @@ -25,16 +25,16 @@ define void @run() { ; CHECK-NEXT: ret void ; entry: - tail call i8 @UseLongDoubleUnsafely(%union.u* byval align 16 bitcast (%struct.s* @b to %union.u*)) - tail call x86_fp80 @UseLongDoubleSafely(%union.u* byval align 16 bitcast (%struct.s* @b to %union.u*)) + tail call i8 @UseLongDoubleUnsafely(%union.u* byval(%union.u) align 16 bitcast (%struct.s* @b to %union.u*)) + tail call x86_fp80 @UseLongDoubleSafely(%union.u* byval(%union.u) align 16 bitcast (%struct.s* @b to %union.u*)) call i64 @AccessPaddingOfStruct(%struct.Foo* @a) call i64 @CaptureAStruct(%struct.Foo* @a) ret void } -define internal i8 @UseLongDoubleUnsafely(%union.u* byval align 16 %arg) { +define internal i8 @UseLongDoubleUnsafely(%union.u* byval(%union.u) align 16 %arg) { ; CHECK-LABEL: define {{[^@]+}}@UseLongDoubleUnsafely -; CHECK-SAME: (%union.u* byval align 16 [[ARG:%.*]]) +; CHECK-SAME: (%union.u* byval(%union.u) align 16 [[ARG:%.*]]) ; CHECK-NEXT: entry: ; CHECK-NEXT: [[BITCAST:%.*]] = bitcast %union.u* [[ARG]] to %struct.s* ; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.s* [[BITCAST]], i64 0, i32 2 @@ -48,7 +48,7 @@ entry: ret i8 %result } -define internal x86_fp80 @UseLongDoubleSafely(%union.u* byval align 16 %arg) { +define internal x86_fp80 @UseLongDoubleSafely(%union.u* byval(%union.u) align 16 %arg) { ; CHECK-LABEL: define {{[^@]+}}@UseLongDoubleSafely ; CHECK-SAME: (x86_fp80 [[ARG_0:%.*]]) ; CHECK-NEXT: [[ARG:%.*]] = alloca [[UNION_U:%.*]], align 16 @@ -63,9 +63,9 @@ define internal x86_fp80 @UseLongDoubleSafely(%union.u* byval align 16 %arg) { ret x86_fp80 %fp80 } -define internal i64 @AccessPaddingOfStruct(%struct.Foo* byval %a) { +define internal i64 @AccessPaddingOfStruct(%struct.Foo* byval(%struct.Foo) %a) { ; CHECK-LABEL: define {{[^@]+}}@AccessPaddingOfStruct -; CHECK-SAME: (%struct.Foo* byval [[A:%.*]]) +; CHECK-SAME: (%struct.Foo* byval(%struct.Foo) [[A:%.*]]) ; CHECK-NEXT: [[P:%.*]] = bitcast %struct.Foo* [[A]] to i64* ; CHECK-NEXT: [[V:%.*]] = load i64, i64* [[P]] ; CHECK-NEXT: ret i64 [[V]] @@ -75,9 +75,9 @@ define internal i64 @AccessPaddingOfStruct(%struct.Foo* byval %a) { ret i64 %v } -define internal i64 @CaptureAStruct(%struct.Foo* byval %a) { +define internal i64 @CaptureAStruct(%struct.Foo* byval(%struct.Foo) %a) { ; CHECK-LABEL: define {{[^@]+}}@CaptureAStruct -; CHECK-SAME: (%struct.Foo* byval [[A:%.*]]) +; CHECK-SAME: (%struct.Foo* byval(%struct.Foo) [[A:%.*]]) ; CHECK-NEXT: entry: ; CHECK-NEXT: [[A_PTR:%.*]] = alloca %struct.Foo* ; CHECK-NEXT: br label [[LOOP:%.*]] diff --git a/test/Transforms/ArgumentPromotion/tail.ll b/test/Transforms/ArgumentPromotion/tail.ll index 62c6f202dc7..4c1d435fa28 100644 --- a/test/Transforms/ArgumentPromotion/tail.ll +++ b/test/Transforms/ArgumentPromotion/tail.ll @@ -9,7 +9,7 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" declare i8* @foo(%pair*) -define internal void @bar(%pair* byval %Data) { +define internal void @bar(%pair* byval(%pair) %Data) { ; CHECK-LABEL: define {{[^@]+}}@bar ; CHECK-SAME: (i32 [[DATA_0:%.*]], i32 [[DATA_1:%.*]]) ; CHECK-NEXT: [[DATA:%.*]] = alloca [[PAIR:%.*]], align 8 @@ -24,9 +24,9 @@ define internal void @bar(%pair* byval %Data) { ret void } -define void @zed(%pair* byval %Data) { +define void @zed(%pair* byval(%pair) %Data) { ; CHECK-LABEL: define {{[^@]+}}@zed -; CHECK-SAME: (%pair* byval [[DATA:%.*]]) +; CHECK-SAME: (%pair* byval(%pair) [[DATA:%.*]]) ; CHECK-NEXT: [[DATA_0:%.*]] = getelementptr [[PAIR:%.*]], %pair* [[DATA]], i32 0, i32 0 ; CHECK-NEXT: [[DATA_0_VAL:%.*]] = load i32, i32* [[DATA_0]], align 4 ; CHECK-NEXT: [[DATA_1:%.*]] = getelementptr [[PAIR]], %pair* [[DATA]], i32 0, i32 1 @@ -34,6 +34,6 @@ define void @zed(%pair* byval %Data) { ; CHECK-NEXT: call void @bar(i32 [[DATA_0_VAL]], i32 [[DATA_1_VAL]]) ; CHECK-NEXT: ret void ; - call void @bar(%pair* byval %Data) + call void @bar(%pair* byval(%pair) %Data) ret void } diff --git a/test/Transforms/ArgumentPromotion/variadic.ll b/test/Transforms/ArgumentPromotion/variadic.ll index 2b35c5aceb9..98e9afc3528 100644 --- a/test/Transforms/ArgumentPromotion/variadic.ll +++ b/test/Transforms/ArgumentPromotion/variadic.ll @@ -19,11 +19,11 @@ define i32 @main(i32 %argc, i8** nocapture readnone %argv) #0 { ; CHECK-LABEL: define {{[^@]+}}@main ; CHECK-SAME: (i32 [[ARGC:%.*]], i8** nocapture readnone [[ARGV:%.*]]) ; CHECK-NEXT: entry: -; CHECK-NEXT: tail call void (i8*, i8*, i8*, i8*, i8*, ...) @callee_t0f(i8* undef, i8* undef, i8* undef, i8* undef, i8* undef, %struct.tt0* byval align 8 @t45) +; CHECK-NEXT: tail call void (i8*, i8*, i8*, i8*, i8*, ...) @callee_t0f(i8* undef, i8* undef, i8* undef, i8* undef, i8* undef, %struct.tt0* byval(%struct.tt0) align 8 @t45) ; CHECK-NEXT: ret i32 0 ; entry: - tail call void (i8*, i8*, i8*, i8*, i8*, ...) @callee_t0f(i8* undef, i8* undef, i8* undef, i8* undef, i8* undef, %struct.tt0* byval align 8 @t45) + tail call void (i8*, i8*, i8*, i8*, i8*, ...) @callee_t0f(i8* undef, i8* undef, i8* undef, i8* undef, i8* undef, %struct.tt0* byval(%struct.tt0) align 8 @t45) ret i32 0 } diff --git a/test/Transforms/Attributor/ArgumentPromotion/attrs.ll b/test/Transforms/Attributor/ArgumentPromotion/attrs.ll index 5b17d8b29d4..034151a0f17 100644 --- a/test/Transforms/Attributor/ArgumentPromotion/attrs.ll +++ b/test/Transforms/Attributor/ArgumentPromotion/attrs.ll @@ -7,11 +7,11 @@ %struct.ss = type { i32, i64 } ; Don't drop 'byval' on %X here. -define internal i32 @f(%struct.ss* byval %b, i32* byval %X, i32 %i) nounwind { +define internal i32 @f(%struct.ss* byval(%struct.ss) %b, i32* byval(i32) %X, i32 %i) nounwind { ; ; IS__TUNIT_OPM: Function Attrs: nofree nosync nounwind readnone willreturn ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@f -; IS__TUNIT_OPM-SAME: (%struct.ss* noalias nocapture nofree noundef nonnull byval align 8 dereferenceable(12) [[B:%.*]], i32* noalias nocapture nofree nonnull byval align 4 dereferenceable(4) [[X:%.*]], i32 noundef [[I:%.*]]) [[ATTR0:#.*]] { +; IS__TUNIT_OPM-SAME: (%struct.ss* noalias nocapture nofree noundef nonnull byval(%struct.ss) align 8 dereferenceable(12) [[B:%.*]], i32* noalias nocapture nofree nonnull byval(i32) align 4 dereferenceable(4) [[X:%.*]], i32 noundef [[I:%.*]]) [[ATTR0:#.*]] { ; IS__TUNIT_OPM-NEXT: entry: ; IS__TUNIT_OPM-NEXT: [[TMP:%.*]] = getelementptr [[STRUCT_SS:%.*]], %struct.ss* [[B]], i32 0, i32 0 ; IS__TUNIT_OPM-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP]], align 8 @@ -44,7 +44,7 @@ define internal i32 @f(%struct.ss* byval %b, i32* byval %X, i32 %i) nounwind { ; ; IS__CGSCC_OPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@f -; IS__CGSCC_OPM-SAME: (%struct.ss* noalias nocapture nofree noundef nonnull byval align 8 dereferenceable(12) [[B:%.*]], i32* noalias nocapture nofree nonnull byval align 4 dereferenceable(4) [[X:%.*]]) [[ATTR0:#.*]] { +; IS__CGSCC_OPM-SAME: (%struct.ss* noalias nocapture nofree noundef nonnull byval(%struct.ss) align 8 dereferenceable(12) [[B:%.*]], i32* noalias nocapture nofree nonnull byval(i32) align 4 dereferenceable(4) [[X:%.*]]) [[ATTR0:#.*]] { ; IS__CGSCC_OPM-NEXT: entry: ; IS__CGSCC_OPM-NEXT: [[TMP:%.*]] = getelementptr [[STRUCT_SS:%.*]], %struct.ss* [[B]], i32 0, i32 0 ; IS__CGSCC_OPM-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP]], align 8 @@ -100,7 +100,7 @@ define i32 @test(i32* %X) { ; IS__TUNIT_OPM-NEXT: store i32 1, i32* [[TMP1]], align 8 ; IS__TUNIT_OPM-NEXT: [[TMP4:%.*]] = getelementptr [[STRUCT_SS]], %struct.ss* [[S]], i32 0, i32 1 ; IS__TUNIT_OPM-NEXT: store i64 2, i64* [[TMP4]], align 4 -; IS__TUNIT_OPM-NEXT: [[C:%.*]] = call i32 @f(%struct.ss* noalias nocapture nofree noundef nonnull readonly byval align 8 dereferenceable(12) [[S]], i32* nocapture nofree readonly byval align 4 [[X]], i32 noundef zeroext 0) [[ATTR0]] +; IS__TUNIT_OPM-NEXT: [[C:%.*]] = call i32 @f(%struct.ss* noalias nocapture nofree noundef nonnull readonly byval(%struct.ss) align 8 dereferenceable(12) [[S]], i32* nocapture nofree readonly byval(i32) align 4 [[X]], i32 noundef zeroext 0) [[ATTR0]] ; IS__TUNIT_OPM-NEXT: ret i32 [[C]] ; ; IS__TUNIT_NPM: Function Attrs: nofree nosync nounwind readnone willreturn @@ -129,7 +129,7 @@ define i32 @test(i32* %X) { ; IS__CGSCC_OPM-NEXT: store i32 1, i32* [[TMP1]], align 8 ; IS__CGSCC_OPM-NEXT: [[TMP4:%.*]] = getelementptr [[STRUCT_SS]], %struct.ss* [[S]], i32 0, i32 1 ; IS__CGSCC_OPM-NEXT: store i64 2, i64* [[TMP4]], align 4 -; IS__CGSCC_OPM-NEXT: [[C:%.*]] = call i32 @f(%struct.ss* noalias nocapture nofree noundef nonnull readnone byval align 8 dereferenceable(12) [[S]], i32* noalias nocapture nofree nonnull readnone byval align 4 dereferenceable(4) [[X]]) [[ATTR1:#.*]] +; IS__CGSCC_OPM-NEXT: [[C:%.*]] = call i32 @f(%struct.ss* noalias nocapture nofree noundef nonnull readnone byval(%struct.ss) align 8 dereferenceable(12) [[S]], i32* noalias nocapture nofree nonnull readnone byval(i32) align 4 dereferenceable(4) [[X]]) [[ATTR1:#.*]] ; IS__CGSCC_OPM-NEXT: ret i32 [[C]] ; ; IS__CGSCC_NPM: Function Attrs: argmemonly nofree norecurse nosync nounwind willreturn @@ -156,7 +156,7 @@ entry: %tmp4 = getelementptr %struct.ss, %struct.ss* %S, i32 0, i32 1 store i64 2, i64* %tmp4, align 4 - %c = call i32 @f( %struct.ss* byval %S, i32* byval %X, i32 zeroext 0) + %c = call i32 @f(%struct.ss* byval(%struct.ss) %S, i32* byval(i32) %X, i32 zeroext 0) ret i32 %c } diff --git a/test/Transforms/Attributor/ArgumentPromotion/byval-2.ll b/test/Transforms/Attributor/ArgumentPromotion/byval-2.ll index 898c6abb2e4..1728b3c6ecc 100644 --- a/test/Transforms/Attributor/ArgumentPromotion/byval-2.ll +++ b/test/Transforms/Attributor/ArgumentPromotion/byval-2.ll @@ -6,10 +6,10 @@ %struct.ss = type { i32, i64 } -define internal void @f(%struct.ss* byval %b, i32* byval %X) nounwind { +define internal void @f(%struct.ss* byval(%struct.ss) %b, i32* byval(i32) %X) nounwind { ; IS__CGSCC_OPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@f -; IS__CGSCC_OPM-SAME: (%struct.ss* noalias nocapture nofree noundef nonnull byval align 8 dereferenceable(12) [[B:%.*]], i32* noalias nocapture nofree nonnull writeonly byval align 4 dereferenceable(4) [[X:%.*]]) [[ATTR0:#.*]] { +; IS__CGSCC_OPM-SAME: (%struct.ss* noalias nocapture nofree noundef nonnull byval(%struct.ss) align 8 dereferenceable(12) [[B:%.*]], i32* noalias nocapture nofree nonnull writeonly byval(i32) align 4 dereferenceable(4) [[X:%.*]]) [[ATTR0:#.*]] { ; IS__CGSCC_OPM-NEXT: entry: ; IS__CGSCC_OPM-NEXT: [[TMP:%.*]] = getelementptr [[STRUCT_SS:%.*]], %struct.ss* [[B]], i32 0, i32 0 ; IS__CGSCC_OPM-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP]], align 8 @@ -87,6 +87,6 @@ entry: store i32 1, i32* %tmp1, align 8 %tmp4 = getelementptr %struct.ss, %struct.ss* %S, i32 0, i32 1 store i64 2, i64* %tmp4, align 4 - call void @f( %struct.ss* byval %S, i32* byval %X) + call void @f(%struct.ss* byval(%struct.ss) %S, i32* byval(i32) %X) ret i32 0 } diff --git a/test/Transforms/Attributor/ArgumentPromotion/byval.ll b/test/Transforms/Attributor/ArgumentPromotion/byval.ll index f9ada827e25..4332e7fed5f 100644 --- a/test/Transforms/Attributor/ArgumentPromotion/byval.ll +++ b/test/Transforms/Attributor/ArgumentPromotion/byval.ll @@ -8,10 +8,10 @@ target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:1 %struct.ss = type { i32, i64 } -define internal i32 @f(%struct.ss* byval %b) nounwind { +define internal i32 @f(%struct.ss* byval(%struct.ss) %b) nounwind { ; IS__TUNIT_OPM: Function Attrs: nofree nosync nounwind readnone willreturn ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@f -; IS__TUNIT_OPM-SAME: (%struct.ss* noalias nocapture nofree noundef nonnull byval align 8 dereferenceable(12) [[B:%.*]]) [[ATTR0:#.*]] { +; IS__TUNIT_OPM-SAME: (%struct.ss* noalias nocapture nofree noundef nonnull byval(%struct.ss) align 8 dereferenceable(12) [[B:%.*]]) [[ATTR0:#.*]] { ; IS__TUNIT_OPM-NEXT: entry: ; IS__TUNIT_OPM-NEXT: [[TMP:%.*]] = getelementptr [[STRUCT_SS:%.*]], %struct.ss* [[B]], i32 0, i32 0 ; IS__TUNIT_OPM-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP]], align 8 @@ -36,7 +36,7 @@ define internal i32 @f(%struct.ss* byval %b) nounwind { ; ; IS__CGSCC_OPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@f -; IS__CGSCC_OPM-SAME: (%struct.ss* noalias nocapture nofree noundef nonnull byval align 32 dereferenceable(12) [[B:%.*]]) [[ATTR0:#.*]] { +; IS__CGSCC_OPM-SAME: (%struct.ss* noalias nocapture nofree noundef nonnull byval(%struct.ss) align 32 dereferenceable(12) [[B:%.*]]) [[ATTR0:#.*]] { ; IS__CGSCC_OPM-NEXT: entry: ; IS__CGSCC_OPM-NEXT: [[TMP:%.*]] = getelementptr [[STRUCT_SS:%.*]], %struct.ss* [[B]], i32 0, i32 0 ; IS__CGSCC_OPM-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP]], align 32 @@ -68,10 +68,10 @@ entry: } -define internal i32 @g(%struct.ss* byval align 32 %b) nounwind { +define internal i32 @g(%struct.ss* byval(%struct.ss) align 32 %b) nounwind { ; IS__TUNIT_OPM: Function Attrs: nofree nosync nounwind readnone willreturn ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@g -; IS__TUNIT_OPM-SAME: (%struct.ss* noalias nocapture nofree noundef nonnull byval align 32 dereferenceable(12) [[B:%.*]]) [[ATTR0]] { +; IS__TUNIT_OPM-SAME: (%struct.ss* noalias nocapture nofree noundef nonnull byval(%struct.ss) align 32 dereferenceable(12) [[B:%.*]]) [[ATTR0]] { ; IS__TUNIT_OPM-NEXT: entry: ; IS__TUNIT_OPM-NEXT: [[TMP:%.*]] = getelementptr [[STRUCT_SS:%.*]], %struct.ss* [[B]], i32 0, i32 0 ; IS__TUNIT_OPM-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP]], align 32 @@ -96,7 +96,7 @@ define internal i32 @g(%struct.ss* byval align 32 %b) nounwind { ; ; IS__CGSCC_OPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@g -; IS__CGSCC_OPM-SAME: (%struct.ss* noalias nocapture nofree noundef nonnull byval align 32 dereferenceable(12) [[B:%.*]]) [[ATTR0]] { +; IS__CGSCC_OPM-SAME: (%struct.ss* noalias nocapture nofree noundef nonnull byval(%struct.ss) align 32 dereferenceable(12) [[B:%.*]]) [[ATTR0]] { ; IS__CGSCC_OPM-NEXT: entry: ; IS__CGSCC_OPM-NEXT: [[TMP:%.*]] = getelementptr [[STRUCT_SS:%.*]], %struct.ss* [[B]], i32 0, i32 0 ; IS__CGSCC_OPM-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP]], align 32 @@ -138,8 +138,8 @@ define i32 @main() nounwind { ; IS__TUNIT_OPM-NEXT: store i32 1, i32* [[TMP1]], align 8 ; IS__TUNIT_OPM-NEXT: [[TMP4:%.*]] = getelementptr [[STRUCT_SS]], %struct.ss* [[S]], i32 0, i32 1 ; IS__TUNIT_OPM-NEXT: store i64 2, i64* [[TMP4]], align 4 -; IS__TUNIT_OPM-NEXT: [[C0:%.*]] = call i32 @f(%struct.ss* noalias nocapture nofree noundef nonnull readonly byval align 8 dereferenceable(12) [[S]]) [[ATTR0]] -; IS__TUNIT_OPM-NEXT: [[C1:%.*]] = call i32 @g(%struct.ss* noalias nocapture nofree noundef nonnull readonly byval align 32 dereferenceable(12) [[S]]) [[ATTR0]] +; IS__TUNIT_OPM-NEXT: [[C0:%.*]] = call i32 @f(%struct.ss* noalias nocapture nofree noundef nonnull readonly byval(%struct.ss) align 8 dereferenceable(12) [[S]]) [[ATTR0]] +; IS__TUNIT_OPM-NEXT: [[C1:%.*]] = call i32 @g(%struct.ss* noalias nocapture nofree noundef nonnull readonly byval(%struct.ss) align 32 dereferenceable(12) [[S]]) [[ATTR0]] ; IS__TUNIT_OPM-NEXT: [[A:%.*]] = add i32 [[C0]], [[C1]] ; IS__TUNIT_OPM-NEXT: ret i32 [[A]] ; @@ -174,8 +174,8 @@ define i32 @main() nounwind { ; IS__CGSCC_OPM-NEXT: store i32 1, i32* [[TMP1]], align 32 ; IS__CGSCC_OPM-NEXT: [[TMP4:%.*]] = getelementptr [[STRUCT_SS]], %struct.ss* [[S]], i32 0, i32 1 ; IS__CGSCC_OPM-NEXT: store i64 2, i64* [[TMP4]], align 4 -; IS__CGSCC_OPM-NEXT: [[C0:%.*]] = call i32 @f(%struct.ss* noalias nocapture nofree noundef nonnull readnone byval align 32 dereferenceable(12) [[S]]) [[ATTR1:#.*]] -; IS__CGSCC_OPM-NEXT: [[C1:%.*]] = call i32 @g(%struct.ss* noalias nocapture nofree noundef nonnull readnone byval align 32 dereferenceable(12) [[S]]) [[ATTR1]] +; IS__CGSCC_OPM-NEXT: [[C0:%.*]] = call i32 @f(%struct.ss* noalias nocapture nofree noundef nonnull readnone byval(%struct.ss) align 32 dereferenceable(12) [[S]]) [[ATTR1:#.*]] +; IS__CGSCC_OPM-NEXT: [[C1:%.*]] = call i32 @g(%struct.ss* noalias nocapture nofree noundef nonnull readnone byval(%struct.ss) align 32 dereferenceable(12) [[S]]) [[ATTR1]] ; IS__CGSCC_OPM-NEXT: [[A:%.*]] = add i32 [[C0]], [[C1]] ; IS__CGSCC_OPM-NEXT: ret i32 [[A]] ; @@ -207,8 +207,8 @@ entry: store i32 1, i32* %tmp1, align 8 %tmp4 = getelementptr %struct.ss, %struct.ss* %S, i32 0, i32 1 store i64 2, i64* %tmp4, align 4 - %c0 = call i32 @f(%struct.ss* byval %S) nounwind - %c1 = call i32 @g(%struct.ss* byval %S) nounwind + %c0 = call i32 @f(%struct.ss* byval(%struct.ss) %S) nounwind + %c1 = call i32 @g(%struct.ss* byval(%struct.ss) %S) nounwind %a = add i32 %c0, %c1 ret i32 %a } diff --git a/test/Transforms/Attributor/ArgumentPromotion/dbg.ll b/test/Transforms/Attributor/ArgumentPromotion/dbg.ll index 64d5adaa750..bd14a2b636a 100644 --- a/test/Transforms/Attributor/ArgumentPromotion/dbg.ll +++ b/test/Transforms/Attributor/ArgumentPromotion/dbg.ll @@ -22,7 +22,7 @@ define internal void @test(i32** %X) !dbg !2 { %struct.pair = type { i32, i32 } -define internal void @test_byval(%struct.pair* byval %P) { +define internal void @test_byval(%struct.pair* byval(%struct.pair) %P) { ; CHECK-LABEL: define {{[^@]+}}@test_byval() { ; CHECK-NEXT: call void @sink(i32 noundef 0) ; CHECK-NEXT: ret void diff --git a/test/Transforms/Attributor/ArgumentPromotion/fp80.ll b/test/Transforms/Attributor/ArgumentPromotion/fp80.ll index 6dffe1e893e..47c5eba84b7 100644 --- a/test/Transforms/Attributor/ArgumentPromotion/fp80.ll +++ b/test/Transforms/Attributor/ArgumentPromotion/fp80.ll @@ -30,14 +30,14 @@ define void @run() { ; IS__CGSCC____-NEXT: unreachable ; entry: - tail call i8 @UseLongDoubleUnsafely(%union.u* byval align 16 bitcast (%struct.s* @b to %union.u*)) - tail call x86_fp80 @UseLongDoubleSafely(%union.u* byval align 16 bitcast (%struct.s* @b to %union.u*)) + tail call i8 @UseLongDoubleUnsafely(%union.u* byval(%union.u) align 16 bitcast (%struct.s* @b to %union.u*)) + tail call x86_fp80 @UseLongDoubleSafely(%union.u* byval(%union.u) align 16 bitcast (%struct.s* @b to %union.u*)) call i64 @AccessPaddingOfStruct(%struct.Foo* @a) call i64 @CaptureAStruct(%struct.Foo* @a) ret void } -define internal i8 @UseLongDoubleUnsafely(%union.u* byval align 16 %arg) { +define internal i8 @UseLongDoubleUnsafely(%union.u* byval(%union.u) align 16 %arg) { ; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@UseLongDoubleUnsafely ; IS__CGSCC____-SAME: () [[ATTR1:#.*]] { @@ -51,7 +51,7 @@ entry: ret i8 %result } -define internal x86_fp80 @UseLongDoubleSafely(%union.u* byval align 16 %arg) { +define internal x86_fp80 @UseLongDoubleSafely(%union.u* byval(%union.u) align 16 %arg) { ; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@UseLongDoubleSafely ; IS__CGSCC____-SAME: () [[ATTR1]] { @@ -62,7 +62,7 @@ define internal x86_fp80 @UseLongDoubleSafely(%union.u* byval align 16 %arg) { ret x86_fp80 %fp80 } -define internal i64 @AccessPaddingOfStruct(%struct.Foo* byval %a) { +define internal i64 @AccessPaddingOfStruct(%struct.Foo* byval(%struct.Foo) %a) { ; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@AccessPaddingOfStruct ; IS__CGSCC____-SAME: () [[ATTR1]] { @@ -73,9 +73,9 @@ define internal i64 @AccessPaddingOfStruct(%struct.Foo* byval %a) { ret i64 %v } -define internal i64 @CaptureAStruct(%struct.Foo* byval %a) { +define internal i64 @CaptureAStruct(%struct.Foo* byval(%struct.Foo) %a) { ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@CaptureAStruct -; IS__CGSCC_OPM-SAME: (%struct.Foo* noalias nofree byval [[A:%.*]]) +; IS__CGSCC_OPM-SAME: (%struct.Foo* noalias nofree byval(%struct.Foo) [[A:%.*]]) ; IS__CGSCC_OPM-NEXT: entry: ; IS__CGSCC_OPM-NEXT: [[A_PTR:%.*]] = alloca %struct.Foo* ; IS__CGSCC_OPM-NEXT: br label [[LOOP:%.*]] diff --git a/test/Transforms/Attributor/ArgumentPromotion/tail.ll b/test/Transforms/Attributor/ArgumentPromotion/tail.ll index c8c4dc4fb52..7aa467a780c 100644 --- a/test/Transforms/Attributor/ArgumentPromotion/tail.ll +++ b/test/Transforms/Attributor/ArgumentPromotion/tail.ll @@ -11,9 +11,9 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" declare i8* @foo(%pair*) -define internal void @bar(%pair* byval %Data) { +define internal void @bar(%pair* byval(%pair) %Data) { ; IS________OPM-LABEL: define {{[^@]+}}@bar -; IS________OPM-SAME: (%pair* noalias nonnull byval dereferenceable(8) [[DATA:%.*]]) { +; IS________OPM-SAME: (%pair* noalias nonnull byval(%pair) dereferenceable(8) [[DATA:%.*]]) { ; IS________OPM-NEXT: [[TMP1:%.*]] = tail call i8* @foo(%pair* nonnull dereferenceable(8) [[DATA]]) ; IS________OPM-NEXT: ret void ; @@ -41,14 +41,14 @@ define internal void @bar(%pair* byval %Data) { ret void } -define void @zed(%pair* byval %Data) { +define void @zed(%pair* byval(%pair) %Data) { ; IS________OPM-LABEL: define {{[^@]+}}@zed -; IS________OPM-SAME: (%pair* noalias nocapture nonnull readonly byval dereferenceable(8) [[DATA:%.*]]) { -; IS________OPM-NEXT: call void @bar(%pair* noalias nocapture nonnull readonly byval dereferenceable(8) [[DATA]]) +; IS________OPM-SAME: (%pair* noalias nocapture nonnull readonly byval(%pair) dereferenceable(8) [[DATA:%.*]]) { +; IS________OPM-NEXT: call void @bar(%pair* noalias nocapture nonnull readonly byval(%pair) dereferenceable(8) [[DATA]]) ; IS________OPM-NEXT: ret void ; ; IS________NPM-LABEL: define {{[^@]+}}@zed -; IS________NPM-SAME: (%pair* noalias nocapture nonnull readonly byval dereferenceable(8) [[DATA:%.*]]) { +; IS________NPM-SAME: (%pair* noalias nocapture nonnull readonly byval(%pair) dereferenceable(8) [[DATA:%.*]]) { ; IS________NPM-NEXT: [[DATA_CAST:%.*]] = bitcast %pair* [[DATA]] to i32* ; IS________NPM-NEXT: [[TMP1:%.*]] = load i32, i32* [[DATA_CAST]], align 1 ; IS________NPM-NEXT: [[DATA_0_1:%.*]] = getelementptr [[PAIR:%.*]], %pair* [[DATA]], i32 0, i32 1 @@ -56,6 +56,6 @@ define void @zed(%pair* byval %Data) { ; IS________NPM-NEXT: call void @bar(i32 [[TMP1]], i32 [[TMP2]]) ; IS________NPM-NEXT: ret void ; - call void @bar(%pair* byval %Data) + call void @bar(%pair* byval(%pair) %Data) ret void } diff --git a/test/Transforms/Attributor/ArgumentPromotion/variadic.ll b/test/Transforms/Attributor/ArgumentPromotion/variadic.ll index e33c5e5e651..39672674f10 100644 --- a/test/Transforms/Attributor/ArgumentPromotion/variadic.ll +++ b/test/Transforms/Attributor/ArgumentPromotion/variadic.ll @@ -21,11 +21,11 @@ define i32 @main(i32 %argc, i8** nocapture readnone %argv) #0 { ; CHECK-LABEL: define {{[^@]+}}@main ; CHECK-SAME: (i32 [[ARGC:%.*]], i8** nocapture nofree readnone [[ARGV:%.*]]) { ; CHECK-NEXT: entry: -; CHECK-NEXT: tail call void (i8*, i8*, i8*, i8*, i8*, ...) @callee_t0f(i8* undef, i8* undef, i8* undef, i8* undef, i8* undef, %struct.tt0* noundef nonnull byval align 8 dereferenceable(16) @t45) +; CHECK-NEXT: tail call void (i8*, i8*, i8*, i8*, i8*, ...) @callee_t0f(i8* undef, i8* undef, i8* undef, i8* undef, i8* undef, %struct.tt0* noundef nonnull byval(%struct.tt0) align 8 dereferenceable(16) @t45) ; CHECK-NEXT: ret i32 0 ; entry: - tail call void (i8*, i8*, i8*, i8*, i8*, ...) @callee_t0f(i8* undef, i8* undef, i8* undef, i8* undef, i8* undef, %struct.tt0* byval align 8 @t45) + tail call void (i8*, i8*, i8*, i8*, i8*, ...) @callee_t0f(i8* undef, i8* undef, i8* undef, i8* undef, i8* undef, %struct.tt0* byval(%struct.tt0) align 8 @t45) ret i32 0 } diff --git a/test/Transforms/Attributor/IPConstantProp/2009-09-24-byval-ptr.ll b/test/Transforms/Attributor/IPConstantProp/2009-09-24-byval-ptr.ll index 8334ae066a6..e2fbaa8ec28 100644 --- a/test/Transforms/Attributor/IPConstantProp/2009-09-24-byval-ptr.ll +++ b/test/Transforms/Attributor/IPConstantProp/2009-09-24-byval-ptr.ll @@ -8,10 +8,10 @@ ; PR5038 %struct.MYstr = type { i8, i32 } @mystr = internal global %struct.MYstr zeroinitializer ; <%struct.MYstr*> [#uses=3] -define internal void @vfu1(%struct.MYstr* byval align 4 %u) nounwind { +define internal void @vfu1(%struct.MYstr* byval(%struct.MYstr) align 4 %u) nounwind { ; IS__CGSCC_OPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@vfu1 -; IS__CGSCC_OPM-SAME: (%struct.MYstr* noalias nocapture nofree noundef nonnull writeonly byval align 8 dereferenceable(8) [[U:%.*]]) [[ATTR0:#.*]] { +; IS__CGSCC_OPM-SAME: (%struct.MYstr* noalias nocapture nofree noundef nonnull writeonly byval(%struct.MYstr) align 8 dereferenceable(8) [[U:%.*]]) [[ATTR0:#.*]] { ; IS__CGSCC_OPM-NEXT: entry: ; IS__CGSCC_OPM-NEXT: [[TMP0:%.*]] = getelementptr [[STRUCT_MYSTR:%.*]], %struct.MYstr* [[U]], i32 0, i32 1 ; IS__CGSCC_OPM-NEXT: store i32 99, i32* [[TMP0]], align 4 @@ -49,10 +49,10 @@ return: ; preds = %entry ret void } -define internal i32 @vfu2(%struct.MYstr* byval align 4 %u) nounwind readonly { +define internal i32 @vfu2(%struct.MYstr* byval(%struct.MYstr) align 4 %u) nounwind readonly { ; IS__TUNIT_OPM: Function Attrs: nofree nosync nounwind readonly willreturn ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@vfu2 -; IS__TUNIT_OPM-SAME: (%struct.MYstr* noalias nocapture nofree noundef nonnull readonly byval align 8 dereferenceable(8) [[U:%.*]]) [[ATTR0:#.*]] { +; IS__TUNIT_OPM-SAME: (%struct.MYstr* noalias nocapture nofree noundef nonnull readonly byval(%struct.MYstr) align 8 dereferenceable(8) [[U:%.*]]) [[ATTR0:#.*]] { ; IS__TUNIT_OPM-NEXT: entry: ; IS__TUNIT_OPM-NEXT: [[TMP0:%.*]] = getelementptr [[STRUCT_MYSTR:%.*]], %struct.MYstr* @mystr, i32 0, i32 1 ; IS__TUNIT_OPM-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -106,7 +106,7 @@ define i32 @unions() nounwind { ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@unions ; IS__TUNIT_OPM-SAME: () [[ATTR1:#.*]] { ; IS__TUNIT_OPM-NEXT: entry: -; IS__TUNIT_OPM-NEXT: [[RESULT:%.*]] = call i32 @vfu2(%struct.MYstr* nocapture nofree noundef nonnull readonly byval align 8 dereferenceable(8) @mystr) [[ATTR0]] +; IS__TUNIT_OPM-NEXT: [[RESULT:%.*]] = call i32 @vfu2(%struct.MYstr* nocapture nofree noundef nonnull readonly byval(%struct.MYstr) align 8 dereferenceable(8) @mystr) [[ATTR0]] ; IS__TUNIT_OPM-NEXT: ret i32 [[RESULT]] ; ; IS__TUNIT_NPM: Function Attrs: nofree nosync nounwind willreturn @@ -128,15 +128,15 @@ define i32 @unions() nounwind { ; IS__CGSCC____-NEXT: ret i32 [[RESULT]] ; entry: - call void @vfu1(%struct.MYstr* byval align 4 @mystr) nounwind - %result = call i32 @vfu2(%struct.MYstr* byval align 4 @mystr) nounwind + call void @vfu1(%struct.MYstr* byval(%struct.MYstr) align 4 @mystr) nounwind + %result = call i32 @vfu2(%struct.MYstr* byval(%struct.MYstr) align 4 @mystr) nounwind ret i32 %result } -define internal i32 @vfu2_v2(%struct.MYstr* byval align 4 %u) nounwind readonly { +define internal i32 @vfu2_v2(%struct.MYstr* byval(%struct.MYstr) align 4 %u) nounwind readonly { ; IS__TUNIT_OPM: Function Attrs: nofree nosync nounwind readnone willreturn ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@vfu2_v2 -; IS__TUNIT_OPM-SAME: (%struct.MYstr* noalias nocapture nofree noundef nonnull byval align 8 dereferenceable(8) [[U:%.*]]) [[ATTR2:#.*]] { +; IS__TUNIT_OPM-SAME: (%struct.MYstr* noalias nocapture nofree noundef nonnull byval(%struct.MYstr) align 8 dereferenceable(8) [[U:%.*]]) [[ATTR2:#.*]] { ; IS__TUNIT_OPM-NEXT: entry: ; IS__TUNIT_OPM-NEXT: [[Z:%.*]] = getelementptr [[STRUCT_MYSTR:%.*]], %struct.MYstr* [[U]], i32 0, i32 1 ; IS__TUNIT_OPM-NEXT: store i32 99, i32* [[Z]], align 4 @@ -169,7 +169,7 @@ define internal i32 @vfu2_v2(%struct.MYstr* byval align 4 %u) nounwind readonly ; ; IS__CGSCC_OPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@vfu2_v2 -; IS__CGSCC_OPM-SAME: (%struct.MYstr* noalias nocapture nofree noundef nonnull byval align 8 dereferenceable(8) [[U:%.*]]) [[ATTR0]] { +; IS__CGSCC_OPM-SAME: (%struct.MYstr* noalias nocapture nofree noundef nonnull byval(%struct.MYstr) align 8 dereferenceable(8) [[U:%.*]]) [[ATTR0]] { ; IS__CGSCC_OPM-NEXT: entry: ; IS__CGSCC_OPM-NEXT: [[Z:%.*]] = getelementptr [[STRUCT_MYSTR:%.*]], %struct.MYstr* [[U]], i32 0, i32 1 ; IS__CGSCC_OPM-NEXT: store i32 99, i32* [[Z]], align 4 @@ -217,7 +217,7 @@ define i32 @unions_v2() nounwind { ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@unions_v2 ; IS__TUNIT_OPM-SAME: () [[ATTR2]] { ; IS__TUNIT_OPM-NEXT: entry: -; IS__TUNIT_OPM-NEXT: [[RESULT:%.*]] = call i32 @vfu2_v2(%struct.MYstr* nocapture nofree noundef nonnull readonly byval align 8 dereferenceable(8) @mystr) [[ATTR2]] +; IS__TUNIT_OPM-NEXT: [[RESULT:%.*]] = call i32 @vfu2_v2(%struct.MYstr* nocapture nofree noundef nonnull readonly byval(%struct.MYstr) align 8 dereferenceable(8) @mystr) [[ATTR2]] ; IS__TUNIT_OPM-NEXT: ret i32 [[RESULT]] ; ; IS__TUNIT_NPM: Function Attrs: nofree nosync nounwind readnone willreturn @@ -235,7 +235,7 @@ define i32 @unions_v2() nounwind { ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@unions_v2 ; IS__CGSCC_OPM-SAME: () [[ATTR0]] { ; IS__CGSCC_OPM-NEXT: entry: -; IS__CGSCC_OPM-NEXT: [[RESULT:%.*]] = call i32 @vfu2_v2(%struct.MYstr* noalias nocapture nofree noundef nonnull readnone byval align 8 dereferenceable(8) @mystr) [[ATTR3:#.*]] +; IS__CGSCC_OPM-NEXT: [[RESULT:%.*]] = call i32 @vfu2_v2(%struct.MYstr* noalias nocapture nofree noundef nonnull readnone byval(%struct.MYstr) align 8 dereferenceable(8) @mystr) [[ATTR3:#.*]] ; IS__CGSCC_OPM-NEXT: ret i32 [[RESULT]] ; ; IS__CGSCC_NPM: Function Attrs: nofree norecurse nosync nounwind readonly willreturn @@ -250,7 +250,7 @@ define i32 @unions_v2() nounwind { ; IS__CGSCC_NPM-NEXT: ret i32 [[RESULT]] ; entry: - call void @vfu1(%struct.MYstr* byval align 4 @mystr) nounwind - %result = call i32 @vfu2_v2(%struct.MYstr* byval align 4 @mystr) nounwind + call void @vfu1(%struct.MYstr* byval(%struct.MYstr) align 4 @mystr) nounwind + %result = call i32 @vfu2_v2(%struct.MYstr* byval(%struct.MYstr) align 4 @mystr) nounwind ret i32 %result } diff --git a/test/Transforms/Attributor/readattrs.ll b/test/Transforms/Attributor/readattrs.ll index c70cd1f5a67..e7e02c791b7 100644 --- a/test/Transforms/Attributor/readattrs.ll +++ b/test/Transforms/Attributor/readattrs.ll @@ -292,10 +292,10 @@ define void @unsound_readonly(i8* %ignored, i8* %escaped_then_written) { ;{ declare void @escape_i8(i8* %ptr) -define void @byval_not_readonly_1(i8* byval %written) readonly { +define void @byval_not_readonly_1(i8* byval(i8) %written) readonly { ; CHECK: Function Attrs: readonly ; CHECK-LABEL: define {{[^@]+}}@byval_not_readonly_1 -; CHECK-SAME: (i8* noalias nonnull byval dereferenceable(1) [[WRITTEN:%.*]]) [[ATTR2]] { +; CHECK-SAME: (i8* noalias nonnull byval(i8) dereferenceable(1) [[WRITTEN:%.*]]) [[ATTR2]] { ; CHECK-NEXT: call void @escape_i8(i8* nonnull dereferenceable(1) [[WRITTEN]]) ; CHECK-NEXT: ret void ; @@ -303,16 +303,16 @@ define void @byval_not_readonly_1(i8* byval %written) readonly { ret void } -define void @byval_not_readonly_2(i8* byval %written) readonly { +define void @byval_not_readonly_2(i8* byval(i8) %written) readonly { ; IS__TUNIT____: Function Attrs: nofree nosync nounwind readnone willreturn ; IS__TUNIT____-LABEL: define {{[^@]+}}@byval_not_readonly_2 -; IS__TUNIT____-SAME: (i8* noalias nocapture nofree nonnull writeonly byval dereferenceable(1) [[WRITTEN:%.*]]) [[ATTR1]] { +; IS__TUNIT____-SAME: (i8* noalias nocapture nofree nonnull writeonly byval(i8) dereferenceable(1) [[WRITTEN:%.*]]) [[ATTR1]] { ; IS__TUNIT____-NEXT: store i8 0, i8* [[WRITTEN]], align 1 ; IS__TUNIT____-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@byval_not_readonly_2 -; IS__CGSCC____-SAME: (i8* noalias nocapture nofree nonnull writeonly byval dereferenceable(1) [[WRITTEN:%.*]]) [[ATTR1]] { +; IS__CGSCC____-SAME: (i8* noalias nocapture nofree nonnull writeonly byval(i8) dereferenceable(1) [[WRITTEN:%.*]]) [[ATTR1]] { ; IS__CGSCC____-NEXT: store i8 0, i8* [[WRITTEN]], align 1 ; IS__CGSCC____-NEXT: ret void ; @@ -320,10 +320,10 @@ define void @byval_not_readonly_2(i8* byval %written) readonly { ret void } -define void @byval_not_readnone_1(i8* byval %written) readnone { +define void @byval_not_readnone_1(i8* byval(i8) %written) readnone { ; CHECK: Function Attrs: readnone ; CHECK-LABEL: define {{[^@]+}}@byval_not_readnone_1 -; CHECK-SAME: (i8* noalias nonnull byval dereferenceable(1) [[WRITTEN:%.*]]) [[ATTR9:#.*]] { +; CHECK-SAME: (i8* noalias nonnull byval(i8) dereferenceable(1) [[WRITTEN:%.*]]) [[ATTR9:#.*]] { ; CHECK-NEXT: call void @escape_i8(i8* nonnull dereferenceable(1) [[WRITTEN]]) ; CHECK-NEXT: ret void ; @@ -331,16 +331,16 @@ define void @byval_not_readnone_1(i8* byval %written) readnone { ret void } -define void @byval_not_readnone_2(i8* byval %written) readnone { +define void @byval_not_readnone_2(i8* byval(i8) %written) readnone { ; IS__TUNIT____: Function Attrs: nofree nosync nounwind readnone willreturn ; IS__TUNIT____-LABEL: define {{[^@]+}}@byval_not_readnone_2 -; IS__TUNIT____-SAME: (i8* noalias nocapture nofree nonnull writeonly byval dereferenceable(1) [[WRITTEN:%.*]]) [[ATTR1]] { +; IS__TUNIT____-SAME: (i8* noalias nocapture nofree nonnull writeonly byval(i8) dereferenceable(1) [[WRITTEN:%.*]]) [[ATTR1]] { ; IS__TUNIT____-NEXT: store i8 0, i8* [[WRITTEN]], align 1 ; IS__TUNIT____-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@byval_not_readnone_2 -; IS__CGSCC____-SAME: (i8* noalias nocapture nofree nonnull writeonly byval dereferenceable(1) [[WRITTEN:%.*]]) [[ATTR1]] { +; IS__CGSCC____-SAME: (i8* noalias nocapture nofree nonnull writeonly byval(i8) dereferenceable(1) [[WRITTEN:%.*]]) [[ATTR1]] { ; IS__CGSCC____-NEXT: store i8 0, i8* [[WRITTEN]], align 1 ; IS__CGSCC____-NEXT: ret void ; @@ -348,16 +348,16 @@ define void @byval_not_readnone_2(i8* byval %written) readnone { ret void } -define void @byval_no_fnarg(i8* byval %written) { +define void @byval_no_fnarg(i8* byval(i8) %written) { ; IS__TUNIT____: Function Attrs: nofree nosync nounwind readnone willreturn ; IS__TUNIT____-LABEL: define {{[^@]+}}@byval_no_fnarg -; IS__TUNIT____-SAME: (i8* noalias nocapture nofree nonnull writeonly byval dereferenceable(1) [[WRITTEN:%.*]]) [[ATTR1]] { +; IS__TUNIT____-SAME: (i8* noalias nocapture nofree nonnull writeonly byval(i8) dereferenceable(1) [[WRITTEN:%.*]]) [[ATTR1]] { ; IS__TUNIT____-NEXT: store i8 0, i8* [[WRITTEN]], align 1 ; IS__TUNIT____-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@byval_no_fnarg -; IS__CGSCC____-SAME: (i8* noalias nocapture nofree nonnull writeonly byval dereferenceable(1) [[WRITTEN:%.*]]) [[ATTR1]] { +; IS__CGSCC____-SAME: (i8* noalias nocapture nofree nonnull writeonly byval(i8) dereferenceable(1) [[WRITTEN:%.*]]) [[ATTR1]] { ; IS__CGSCC____-NEXT: store i8 0, i8* [[WRITTEN]], align 1 ; IS__CGSCC____-NEXT: ret void ; diff --git a/test/Transforms/Attributor/value-simplify.ll b/test/Transforms/Attributor/value-simplify.ll index ae96761507b..586f3486c6f 100644 --- a/test/Transforms/Attributor/value-simplify.ll +++ b/test/Transforms/Attributor/value-simplify.ll @@ -490,10 +490,10 @@ define %struct.X* @complicated_args_nest() { } @S = external global %struct.X -define internal void @test_byval(%struct.X* byval %a) { +define internal void @test_byval(%struct.X* byval(%struct.X) %a) { ; IS__CGSCC_OPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@test_byval -; IS__CGSCC_OPM-SAME: (%struct.X* noalias nocapture nofree noundef nonnull writeonly byval align 8 dereferenceable(8) [[A:%.*]]) [[ATTR1]] { +; IS__CGSCC_OPM-SAME: (%struct.X* noalias nocapture nofree noundef nonnull writeonly byval(%struct.X) align 8 dereferenceable(8) [[A:%.*]]) [[ATTR1]] { ; IS__CGSCC_OPM-NEXT: [[G0:%.*]] = getelementptr [[STRUCT_X:%.*]], %struct.X* [[A]], i32 0, i32 0 ; IS__CGSCC_OPM-NEXT: store i8* null, i8** [[G0]], align 8 ; IS__CGSCC_OPM-NEXT: ret void @@ -532,7 +532,7 @@ define void @complicated_args_byval() { ret void } -define internal i8*@test_byval2(%struct.X* byval %a) { +define internal i8*@test_byval2(%struct.X* byval(%struct.X) %a) { ; IS__TUNIT____: Function Attrs: nofree nosync nounwind readonly willreturn ; IS__TUNIT____-LABEL: define {{[^@]+}}@test_byval2 ; IS__TUNIT____-SAME: () [[ATTR3:#.*]] { diff --git a/test/Transforms/DeadArgElim/2007-12-20-ParamAttrs.ll b/test/Transforms/DeadArgElim/2007-12-20-ParamAttrs.ll index ab378e9df1e..b6c9241435e 100644 --- a/test/Transforms/DeadArgElim/2007-12-20-ParamAttrs.ll +++ b/test/Transforms/DeadArgElim/2007-12-20-ParamAttrs.ll @@ -13,7 +13,7 @@ define internal zeroext i8 @foo(i8* inreg %p, i8 signext %y, ... ) nounwind { define i32 @bar() { ; CHECK: call void @foo(i8 signext 1) [[NUW]] - %A = call zeroext i8(i8*, i8, ...) @foo(i8* inreg null, i8 signext 1, %struct* byval null ) nounwind + %A = call zeroext i8(i8*, i8, ...) @foo(i8* inreg null, i8 signext 1, %struct* byval(%struct) null ) nounwind ret i32 0 } diff --git a/test/Transforms/DeadArgElim/2008-01-16-VarargsParamAttrs.ll b/test/Transforms/DeadArgElim/2008-01-16-VarargsParamAttrs.ll index 48e43961e7a..4032e9d3e3b 100644 --- a/test/Transforms/DeadArgElim/2008-01-16-VarargsParamAttrs.ll +++ b/test/Transforms/DeadArgElim/2008-01-16-VarargsParamAttrs.ll @@ -15,17 +15,17 @@ entry: ret i32 undef } -declare void @llvm.va_start(i8*) nounwind +declare void @llvm.va_start(i8*) nounwind -declare void @llvm.va_end(i8*) nounwind +declare void @llvm.va_end(i8*) nounwind define i32 @main() { entry: %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] %tmp = getelementptr [4 x %struct.point], [4 x %struct.point]* @pts, i32 0, i32 0 ; <%struct.point*> [#uses=1] - %tmp1 = call i32 (i32, ...) @va1( i32 1, %struct.point* byval %tmp ) nounwind ; [#uses=0] - call void @exit( i32 0 ) noreturn nounwind + %tmp1 = call i32 (i32, ...) @va1(i32 1, %struct.point* byval(%struct.point) %tmp) nounwind ; [#uses=0] + call void @exit( i32 0 ) noreturn nounwind unreachable } -declare void @exit(i32) noreturn nounwind +declare void @exit(i32) noreturn nounwind diff --git a/test/Transforms/DeadArgElim/variadic_safety.ll b/test/Transforms/DeadArgElim/variadic_safety.ll index 2dac2f9180e..0e10dce3fbc 100644 --- a/test/Transforms/DeadArgElim/variadic_safety.ll +++ b/test/Transforms/DeadArgElim/variadic_safety.ll @@ -17,9 +17,9 @@ define internal i32 @va_func(i32 %a, i32 %b, ...) { define i32 @call_va(i32 %in) { %stacked = alloca i32 store i32 42, i32* %stacked - %res = call i32(i32, i32, ...) @va_func(i32 %in, i32 %in, [6 x i32] undef, i32* byval %stacked) + %res = call i32(i32, i32, ...) @va_func(i32 %in, i32 %in, [6 x i32] undef, i32* byval(i32) %stacked) ret i32 %res -; CHECK: call i32 (i32, i32, ...) @va_func(i32 undef, i32 %in, [6 x i32] undef, i32* byval %stacked) +; CHECK: call i32 (i32, i32, ...) @va_func(i32 undef, i32 %in, [6 x i32] undef, i32* byval(i32) %stacked) } define internal i32 @va_deadret_func(i32 %a, i32 %b, ...) { @@ -32,7 +32,7 @@ define internal i32 @va_deadret_func(i32 %a, i32 %b, ...) { define void @call_deadret(i32 %in) { %stacked = alloca i32 store i32 42, i32* %stacked - call i32 (i32, i32, ...) @va_deadret_func(i32 undef, i32 %in, [6 x i32] undef, i32* byval %stacked) + call i32 (i32, i32, ...) @va_deadret_func(i32 undef, i32 %in, [6 x i32] undef, i32* byval(i32) %stacked) ret void -; CHECK: call void (i32, i32, ...) @va_deadret_func(i32 undef, i32 undef, [6 x i32] undef, i32* byval %stacked) +; CHECK: call void (i32, i32, ...) @va_deadret_func(i32 undef, i32 undef, [6 x i32] undef, i32* byval(i32) %stacked) } diff --git a/test/Transforms/DeadStoreElimination/MSSA/fence-todo.ll b/test/Transforms/DeadStoreElimination/MSSA/fence-todo.ll index ab4e65edaab..a00ef9cbf24 100644 --- a/test/Transforms/DeadStoreElimination/MSSA/fence-todo.ll +++ b/test/Transforms/DeadStoreElimination/MSSA/fence-todo.ll @@ -7,7 +7,7 @@ ; Right now the DSE in presence of fence is only done in end blocks (with no successors), ; but the same logic applies to other basic blocks as well. ; The store to %addr.i can be removed since it is a byval attribute -define void @test3(i32* byval %addr.i) { +define void @test3(i32* byval(i32) %addr.i) { ; CHECK-LABEL: @test3 ; CHECK-NOT: store ; CHECK: fence diff --git a/test/Transforms/DeadStoreElimination/MSSA/simple.ll b/test/Transforms/DeadStoreElimination/MSSA/simple.ll index 5ee1a55a736..8fe4155d487 100644 --- a/test/Transforms/DeadStoreElimination/MSSA/simple.ll +++ b/test/Transforms/DeadStoreElimination/MSSA/simple.ll @@ -138,7 +138,7 @@ define i32 @test8() { ; Test for byval handling. %struct.x = type { i32, i32, i32, i32 } -define void @test9(%struct.x* byval %a) nounwind { +define void @test9(%struct.x* byval(%struct.x) %a) nounwind { ; CHECK-LABEL: @test9( ; CHECK-NEXT: ret void ; @@ -249,20 +249,20 @@ define void @test14(i32* %Q) { } ; The store here is not dead because the byval call reads it. -declare void @test19f({i32}* byval align 4 %P) +declare void @test19f({i32}* byval({i32}) align 4 %P) -define void @test19({i32} * nocapture byval align 4 %arg5) nounwind ssp { +define void @test19({i32}* nocapture byval({i32}) align 4 %arg5) nounwind ssp { ; CHECK-LABEL: @test19( ; CHECK-NEXT: bb: ; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds { i32 }, { i32 }* [[ARG5:%.*]], i32 0, i32 0 ; CHECK-NEXT: store i32 912, i32* [[TMP7]], align 4 -; CHECK-NEXT: call void @test19f({ i32 }* byval align 4 [[ARG5]]) +; CHECK-NEXT: call void @test19f({ i32 }* byval({ i32 }) align 4 [[ARG5]]) ; CHECK-NEXT: ret void ; bb: %tmp7 = getelementptr inbounds {i32}, {i32}* %arg5, i32 0, i32 0 store i32 912, i32* %tmp7 - call void @test19f({i32}* byval align 4 %arg5) + call void @test19f({i32}* byval({i32}) align 4 %arg5) ret void } diff --git a/test/Transforms/DeadStoreElimination/MSSA/tail-byval.ll b/test/Transforms/DeadStoreElimination/MSSA/tail-byval.ll index ed2fbd434a7..c11315a188b 100644 --- a/test/Transforms/DeadStoreElimination/MSSA/tail-byval.ll +++ b/test/Transforms/DeadStoreElimination/MSSA/tail-byval.ll @@ -8,16 +8,16 @@ target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128" target triple = "i386-unknown-linux-gnu" -declare void @g(i32* byval %p) +declare void @g(i32* byval(i32) %p) -define void @f(i32* byval %x) { +define void @f(i32* byval(i32) %x) { entry: %p = alloca i32 %v = load i32, i32* %x store i32 %v, i32* %p - tail call void @g(i32* byval %p) + tail call void @g(i32* byval(i32) %p) ret void } -; CHECK-LABEL: define void @f(i32* byval %x) +; CHECK-LABEL: define void @f(i32* byval(i32) %x) ; CHECK: store i32 %v, i32* %p -; CHECK: tail call void @g(i32* byval %p) +; CHECK: tail call void @g(i32* byval(i32) %p) diff --git a/test/Transforms/DeadStoreElimination/MemDepAnalysis/fence.ll b/test/Transforms/DeadStoreElimination/MemDepAnalysis/fence.ll index ce2dcd3236b..55b6b8a6d5a 100644 --- a/test/Transforms/DeadStoreElimination/MemDepAnalysis/fence.ll +++ b/test/Transforms/DeadStoreElimination/MemDepAnalysis/fence.ll @@ -52,7 +52,7 @@ define void @test2(i32* %addr.i) { ; Right now the DSE in presence of fence is only done in end blocks (with no successors), ; but the same logic applies to other basic blocks as well. ; The store to %addr.i can be removed since it is a byval attribute -define void @test3(i32* byval %addr.i) { +define void @test3(i32* byval(i32) %addr.i) { ; CHECK-LABEL: @test3 ; CHECK-NOT: store ; CHECK: fence diff --git a/test/Transforms/DeadStoreElimination/MemDepAnalysis/simple.ll b/test/Transforms/DeadStoreElimination/MemDepAnalysis/simple.ll index 26674ec382b..15caa6c898d 100644 --- a/test/Transforms/DeadStoreElimination/MemDepAnalysis/simple.ll +++ b/test/Transforms/DeadStoreElimination/MemDepAnalysis/simple.ll @@ -150,7 +150,7 @@ define i32 @test8() { ; Test for byval handling. %struct.x = type { i32, i32, i32, i32 } -define void @test9(%struct.x* byval %a) nounwind { +define void @test9(%struct.x* byval(%struct.x) %a) nounwind { ; CHECK-LABEL: @test9( ; CHECK-NEXT: ret void ; @@ -476,20 +476,20 @@ define void @test18_atomic(i8* %P, i8* %Q, i8* %R) nounwind ssp { ; The store here is not dead because the byval call reads it. -declare void @test19f({i32}* byval align 4 %P) +declare void @test19f({i32}* byval({i32}) align 4 %P) -define void @test19({i32} * nocapture byval align 4 %arg5) nounwind ssp { +define void @test19({i32} * nocapture byval({i32}) align 4 %arg5) nounwind ssp { ; CHECK-LABEL: @test19( ; CHECK-NEXT: bb: ; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds { i32 }, { i32 }* [[ARG5:%.*]], i32 0, i32 0 ; CHECK-NEXT: store i32 912, i32* [[TMP7]], align 4 -; CHECK-NEXT: call void @test19f({ i32 }* byval align 4 [[ARG5]]) +; CHECK-NEXT: call void @test19f({ i32 }* byval({ i32 }) align 4 [[ARG5]]) ; CHECK-NEXT: ret void ; bb: %tmp7 = getelementptr inbounds {i32}, {i32}* %arg5, i32 0, i32 0 store i32 912, i32* %tmp7 - call void @test19f({i32}* byval align 4 %arg5) + call void @test19f({i32}* byval({i32}) align 4 %arg5) ret void } diff --git a/test/Transforms/DeadStoreElimination/MemDepAnalysis/tail-byval.ll b/test/Transforms/DeadStoreElimination/MemDepAnalysis/tail-byval.ll index 0b4a76fee55..698f49a49b4 100644 --- a/test/Transforms/DeadStoreElimination/MemDepAnalysis/tail-byval.ll +++ b/test/Transforms/DeadStoreElimination/MemDepAnalysis/tail-byval.ll @@ -8,16 +8,16 @@ target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128" target triple = "i386-unknown-linux-gnu" -declare void @g(i32* byval %p) +declare void @g(i32* byval(i32) %p) -define void @f(i32* byval %x) { +define void @f(i32* byval(i32) %x) { entry: %p = alloca i32 %v = load i32, i32* %x store i32 %v, i32* %p - tail call void @g(i32* byval %p) + tail call void @g(i32* byval(i32) %p) ret void } -; CHECK-LABEL: define void @f(i32* byval %x) +; CHECK-LABEL: define void @f(i32* byval(i32) %x) ; CHECK: store i32 %v, i32* %p -; CHECK: tail call void @g(i32* byval %p) +; CHECK: tail call void @g(i32* byval(i32) %p) diff --git a/test/Transforms/GVN/pr17852.ll b/test/Transforms/GVN/pr17852.ll index 3d41a357f00..25caab9ab07 100644 --- a/test/Transforms/GVN/pr17852.ll +++ b/test/Transforms/GVN/pr17852.ll @@ -1,7 +1,7 @@ ; RUN: opt < %s -basic-aa -gvn target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" %struct.S0 = type { [2 x i8], [2 x i8], [4 x i8], [2 x i8], i32, i32, i32, i32 } -define void @fn1(%struct.S0* byval align 8 %p1) { +define void @fn1(%struct.S0* byval(%struct.S0) align 8 %p1) { br label %for.cond for.cond: ; preds = %1, %0 br label %for.end diff --git a/test/Transforms/IndVarSimplify/loop_evaluate9.ll b/test/Transforms/IndVarSimplify/loop_evaluate9.ll index 96f2f30bd3b..824268b2787 100644 --- a/test/Transforms/IndVarSimplify/loop_evaluate9.ll +++ b/test/Transforms/IndVarSimplify/loop_evaluate9.ll @@ -72,13 +72,13 @@ return: ; preds = %cc70a02__complex_multiplication.170.exit ret void } -declare fastcc void @cc70a02__complex_integers__complex.164(%struct.cc70a02__complex_integers__complex_type* noalias nocapture sret, i8 signext, i8 signext) nounwind +declare fastcc void @cc70a02__complex_integers__complex.164(%struct.cc70a02__complex_integers__complex_type* noalias nocapture sret(%struct.cc70a02__complex_integers__complex_type), i8 signext, i8 signext) nounwind -declare fastcc void @cc70a02__complex_integers__Osubtract.149(%struct.cc70a02__complex_integers__complex_type* noalias sret, %struct.cc70a02__complex_integers__complex_type* byval align 4) +declare fastcc void @cc70a02__complex_integers__Osubtract.149(%struct.cc70a02__complex_integers__complex_type* noalias sret(%struct.cc70a02__complex_integers__complex_type), %struct.cc70a02__complex_integers__complex_type* byval(%struct.cc70a02__complex_integers__complex_type) align 4) -declare fastcc void @cc70a02__complex_integers__Oadd.153(%struct.cc70a02__complex_integers__complex_type* noalias sret, %struct.cc70a02__complex_integers__complex_type* byval align 4, %struct.cc70a02__complex_integers__complex_type* byval align 4) +declare fastcc void @cc70a02__complex_integers__Oadd.153(%struct.cc70a02__complex_integers__complex_type* noalias sret(%struct.cc70a02__complex_integers__complex_type), %struct.cc70a02__complex_integers__complex_type* byval(%struct.cc70a02__complex_integers__complex_type) align 4, %struct.cc70a02__complex_integers__complex_type* byval(%struct.cc70a02__complex_integers__complex_type) align 4) -declare fastcc void @cc70a02__complex_multiplication.170(%struct.cc70a02__complex_integers__complex_type* noalias sret, %struct.cc70a02__complex_integers__complex_type* byval align 4) +declare fastcc void @cc70a02__complex_multiplication.170(%struct.cc70a02__complex_integers__complex_type* noalias sret(%struct.cc70a02__complex_integers__complex_type), %struct.cc70a02__complex_integers__complex_type* byval(%struct.cc70a02__complex_integers__complex_type) align 4) declare void @__gnat_rcheck_12(i8*, i32) noreturn diff --git a/test/Transforms/Inline/alloca-merge-align.ll b/test/Transforms/Inline/alloca-merge-align.ll index e3b819d561f..9ff1280062b 100644 --- a/test/Transforms/Inline/alloca-merge-align.ll +++ b/test/Transforms/Inline/alloca-merge-align.ll @@ -5,7 +5,7 @@ target triple = "powerpc64-unknown-linux-gnu" %struct.s = type { i32, i32 } -define void @foo(%struct.s* byval nocapture readonly %a) { +define void @foo(%struct.s* byval(%struct.s) nocapture readonly %a) { entry: %x = alloca [2 x i32], align 4 %a1 = getelementptr inbounds %struct.s, %struct.s* %a, i64 0, i32 0 @@ -20,7 +20,7 @@ entry: ret void } -define void @foo0(%struct.s* byval nocapture readonly %a) { +define void @foo0(%struct.s* byval(%struct.s) nocapture readonly %a) { entry: %x = alloca [2 x i32] %a1 = getelementptr inbounds %struct.s, %struct.s* %a, i64 0, i32 0 @@ -35,7 +35,7 @@ entry: ret void } -define void @foo1(%struct.s* byval nocapture readonly %a) { +define void @foo1(%struct.s* byval(%struct.s) nocapture readonly %a) { entry: %x = alloca [2 x i32], align 1 %a1 = getelementptr inbounds %struct.s, %struct.s* %a, i64 0, i32 0 @@ -52,7 +52,7 @@ entry: declare void @bar(i32*) #1 -define void @goo(%struct.s* byval nocapture readonly %a) { +define void @goo(%struct.s* byval(%struct.s) nocapture readonly %a) { entry: %x = alloca [2 x i32], align 32 %a1 = getelementptr inbounds %struct.s, %struct.s* %a, i64 0, i32 0 @@ -79,9 +79,9 @@ entry: store i64 0, i64* %a, align 8 %a1 = bitcast i64* %a to i32* store i32 1, i32* %a1, align 8 - call void @foo(%struct.s* byval %tmpcast) + call void @foo(%struct.s* byval(%struct.s) %tmpcast) store i32 2, i32* %a1, align 8 - call void @goo(%struct.s* byval %tmpcast) + call void @goo(%struct.s* byval(%struct.s) %tmpcast) ret i32 0 } @@ -97,8 +97,8 @@ entry: store i64 0, i64* %a, align 8 %a1 = bitcast i64* %a to i32* store i32 1, i32* %a1, align 8 - call void @foo0(%struct.s* byval %tmpcast) + call void @foo0(%struct.s* byval(%struct.s) %tmpcast) store i32 2, i32* %a1, align 8 - call void @goo(%struct.s* byval %tmpcast) + call void @goo(%struct.s* byval(%struct.s) %tmpcast) ret i32 0 } diff --git a/test/Transforms/Inline/byval-tail-call.ll b/test/Transforms/Inline/byval-tail-call.ll index 1a3cdc558e6..56a784a077c 100644 --- a/test/Transforms/Inline/byval-tail-call.ll +++ b/test/Transforms/Inline/byval-tail-call.ll @@ -10,7 +10,7 @@ target triple = "i386-pc-linux-gnu" declare void @ext(i32*) -define void @bar(i32* byval %x) { +define void @bar(i32* byval(i32) %x) { call void @ext(i32* %x) ret void } @@ -19,11 +19,11 @@ define void @foo(i32* %x) { ; CHECK-LABEL: define void @foo( ; CHECK: llvm.lifetime.start ; CHECK: store i32 %2, i32* %x - call void @bar(i32* byval %x) + call void @bar(i32* byval(i32) %x) ret void } -define internal void @qux(i32* byval %x) { +define internal void @qux(i32* byval(i32) %x) { call void @ext(i32* %x) tail call void @ext(i32* null) ret void @@ -37,17 +37,17 @@ define void @frob(i32* %x) { ; CHECK: {{^ *}}call void @ext(i32* nonnull %[[POS]] ; CHECK: tail call void @ext(i32* null) ; CHECK: ret void - tail call void @qux(i32* byval %x) + tail call void @qux(i32* byval(i32) %x) ret void } ; A byval parameter passed into a function which is passed out as byval does ; not block the call from being marked as tail. -declare void @ext2(i32* byval) +declare void @ext2(i32* byval(i32)) -define void @bar2(i32* byval %x) { - call void @ext2(i32* byval %x) +define void @bar2(i32* byval(i32) %x) { + call void @ext2(i32* byval(i32) %x) ret void } @@ -56,9 +56,9 @@ define void @foobar(i32* %x) { ; CHECK: %[[POS:.*]] = alloca i32 ; CHECK: %[[VAL:.*]] = load i32, i32* %x ; CHECK: store i32 %[[VAL]], i32* %[[POS]] -; CHECK: tail call void @ext2(i32* nonnull byval %[[POS]] +; CHECK: tail call void @ext2(i32* nonnull byval(i32) %[[POS]] ; CHECK: ret void - tail call void @bar2(i32* byval %x) + tail call void @bar2(i32* byval(i32) %x) ret void } @@ -67,9 +67,9 @@ define void @barfoo() { ; CHECK: %[[POS:.*]] = alloca i32 ; CHECK: %[[VAL:.*]] = load i32, i32* %x ; CHECK: store i32 %[[VAL]], i32* %[[POS]] -; CHECK: tail call void @ext2(i32* nonnull byval %[[POS]] +; CHECK: tail call void @ext2(i32* nonnull byval(i32) %[[POS]] ; CHECK: ret void %x = alloca i32 - tail call void @bar2(i32* byval %x) + tail call void @bar2(i32* byval(i32) %x) ret void } diff --git a/test/Transforms/Inline/byval.ll b/test/Transforms/Inline/byval.ll index ea2bec2cee3..ea8aef32331 100644 --- a/test/Transforms/Inline/byval.ll +++ b/test/Transforms/Inline/byval.ll @@ -13,7 +13,7 @@ target datalayout = "p:32:32-p1:64:64-p2:16:16-n16:32:64" %struct.ss = type { i32, i64 } @.str = internal constant [10 x i8] c"%d, %lld\0A\00" ; <[10 x i8]*> [#uses=1] -define internal void @f(%struct.ss* byval %b) nounwind { +define internal void @f(%struct.ss* byval(%struct.ss) %b) nounwind { entry: %tmp = getelementptr %struct.ss, %struct.ss* %b, i32 0, i32 0 ; [#uses=2] %tmp1 = load i32, i32* %tmp, align 4 ; [#uses=1] @@ -22,7 +22,7 @@ entry: ret void } -declare i32 @printf(i8*, ...) nounwind +declare i32 @printf(i8*, ...) nounwind define i32 @test1() nounwind { entry: @@ -31,7 +31,7 @@ entry: store i32 1, i32* %tmp1, align 8 %tmp4 = getelementptr %struct.ss, %struct.ss* %S, i32 0, i32 1 ; [#uses=1] store i64 2, i64* %tmp4, align 4 - call void @f( %struct.ss* byval %S ) nounwind + call void @f(%struct.ss* byval(%struct.ss) %S) nounwind ret i32 0 ; CHECK: @test1() ; CHECK: %S1 = alloca %struct.ss @@ -40,10 +40,10 @@ entry: ; CHECK: ret i32 0 } -; Inlining a byval struct should NOT cause an explicit copy +; Inlining a byval struct should NOT cause an explicit copy ; into an alloca if the function is readonly -define internal i32 @f2(%struct.ss* byval %b) nounwind readonly { +define internal i32 @f2(%struct.ss* byval(%struct.ss) %b) nounwind readonly { entry: %tmp = getelementptr %struct.ss, %struct.ss* %b, i32 0, i32 0 ; [#uses=2] %tmp1 = load i32, i32* %tmp, align 4 ; [#uses=1] @@ -58,7 +58,7 @@ entry: store i32 1, i32* %tmp1, align 8 %tmp4 = getelementptr %struct.ss, %struct.ss* %S, i32 0, i32 1 ; [#uses=1] store i64 2, i64* %tmp4, align 4 - %X = call i32 @f2( %struct.ss* byval %S ) nounwind + %X = call i32 @f2(%struct.ss* byval(%struct.ss) %S) nounwind ret i32 %X ; CHECK: @test2() ; CHECK: %S = alloca %struct.ss @@ -72,7 +72,7 @@ entry: ; PR8769 declare void @g3(%struct.ss* %p) -define internal void @f3(%struct.ss* byval align 64 %b) nounwind { +define internal void @f3(%struct.ss* byval(%struct.ss) align 64 %b) nounwind { call void @g3(%struct.ss* %b) ;; Could make alignment assumptions! ret void } @@ -80,7 +80,7 @@ define internal void @f3(%struct.ss* byval align 64 %b) nounwind { define void @test3() nounwind { entry: %S = alloca %struct.ss, align 1 ;; May not be aligned. - call void @f3( %struct.ss* byval align 64 %S) nounwind + call void @f3(%struct.ss* byval(%struct.ss) align 64 %S) nounwind ret void ; CHECK: @test3() ; CHECK: %S1 = alloca %struct.ss, align 64 @@ -91,11 +91,11 @@ entry: } -; Inlining a byval struct should NOT cause an explicit copy +; Inlining a byval struct should NOT cause an explicit copy ; into an alloca if the function is readonly, but should increase an alloca's ; alignment to satisfy an explicit alignment request. -define internal i32 @f4(%struct.ss* byval align 64 %b) nounwind readonly { +define internal i32 @f4(%struct.ss* byval(%struct.ss) align 64 %b) nounwind readonly { call void @g3(%struct.ss* %b) ret i32 4 } @@ -103,7 +103,7 @@ define internal i32 @f4(%struct.ss* byval align 64 %b) nounwind readonly { define i32 @test4() nounwind { entry: %S = alloca %struct.ss, align 2 ; <%struct.ss*> [#uses=4] - %X = call i32 @f4( %struct.ss* byval align 64 %S ) nounwind + %X = call i32 @f4(%struct.ss* byval(%struct.ss) align 64 %S) nounwind ret i32 %X ; CHECK: @test4() ; CHECK: %S = alloca %struct.ss, align 64 @@ -117,7 +117,7 @@ entry: @b = global %struct.S0 { i32 1 }, align 4 @a = common global i32 0, align 4 -define internal void @f5(%struct.S0* byval nocapture readonly align 4 %p) { +define internal void @f5(%struct.S0* byval(%struct.S0) nocapture readonly align 4 %p) { entry: store i32 0, i32* getelementptr inbounds (%struct.S0, %struct.S0* @b, i64 0, i32 0), align 4 %f2 = getelementptr inbounds %struct.S0, %struct.S0* %p, i64 0, i32 0 @@ -128,7 +128,7 @@ entry: define i32 @test5() { entry: - tail call void @f5(%struct.S0* byval align 4 @b) + tail call void @f5(%struct.S0* byval(%struct.S0) align 4 @b) %0 = load i32, i32* @a, align 4 ret i32 %0 ; CHECK: @test5() @@ -146,7 +146,7 @@ entry: @d = addrspace(1) global %struct.S1 { i32 1 }, align 4 @c = common addrspace(1) global i32 0, align 4 -define internal void @f5_as1(%struct.S1 addrspace(1)* byval nocapture readonly align 4 %p) { +define internal void @f5_as1(%struct.S1 addrspace(1)* byval(%struct.S1) nocapture readonly align 4 %p) { entry: store i32 0, i32 addrspace(1)* getelementptr inbounds (%struct.S1, %struct.S1 addrspace(1)* @d, i64 0, i32 0), align 4 %f2 = getelementptr inbounds %struct.S1, %struct.S1 addrspace(1)* %p, i64 0, i32 0 @@ -157,7 +157,7 @@ entry: define i32 @test5_as1() { entry: - tail call void @f5_as1(%struct.S1 addrspace(1)* byval align 4 @d) + tail call void @f5_as1(%struct.S1 addrspace(1)* byval(%struct.S1) align 4 @d) %0 = load i32, i32 addrspace(1)* @c, align 4 ret i32 %0 ; CHECK: @test5_as1() diff --git a/test/Transforms/Inline/byval_lifetime.ll b/test/Transforms/Inline/byval_lifetime.ll index 4517e448018..3d9b2c27660 100644 --- a/test/Transforms/Inline/byval_lifetime.ll +++ b/test/Transforms/Inline/byval_lifetime.ll @@ -8,7 +8,7 @@ @gFoo = global %struct.foo zeroinitializer, align 8 -define i32 @foo(%struct.foo* byval align 8 %f, i32 %a) { +define i32 @foo(%struct.foo* byval(%struct.foo) align 8 %f, i32 %a) { entry: %a1 = getelementptr inbounds %struct.foo, %struct.foo* %f, i32 0, i32 1 %arrayidx = getelementptr inbounds [16 x i32], [16 x i32]* %a1, i32 0, i32 %a @@ -21,6 +21,6 @@ define i32 @main(i32 %argc, i8** %argv) { ; CHECK: llvm.lifetime.start ; CHECK: memcpy entry: - %call = call i32 @foo(%struct.foo* byval align 8 @gFoo, i32 %argc) + %call = call i32 @foo(%struct.foo* byval(%struct.foo) align 8 @gFoo, i32 %argc) ret i32 %call } diff --git a/test/Transforms/Inline/inline-byval-bonus.ll b/test/Transforms/Inline/inline-byval-bonus.ll index 785de04c3f1..ec4610ed9a7 100644 --- a/test/Transforms/Inline/inline-byval-bonus.ll +++ b/test/Transforms/Inline/inline-byval-bonus.ll @@ -19,7 +19,7 @@ define i32 @caller(%struct.sphere* %i) { %shadow_ray = alloca %struct.ray, align 8 call void @fix(%struct.ray* %shadow_ray) - %call = call i32 @ray_sphere(%struct.sphere* %i, %struct.ray* byval align 8 %shadow_ray, %struct.spoint* null) + %call = call i32 @ray_sphere(%struct.sphere* %i, %struct.ray* byval(%struct.ray) align 8 %shadow_ray, %struct.spoint* null) ret i32 %call ; CHECK-LABEL: @caller( @@ -29,7 +29,7 @@ define i32 @caller(%struct.sphere* %i) { declare void @fix(%struct.ray*) -define i32 @ray_sphere(%struct.sphere* nocapture %sph, %struct.ray* nocapture byval align 8 %ray, %struct.spoint* %sp) nounwind uwtable ssp { +define i32 @ray_sphere(%struct.sphere* nocapture %sph, %struct.ray* nocapture byval(%struct.ray) align 8 %ray, %struct.spoint* %sp) nounwind uwtable ssp { %1 = getelementptr inbounds %struct.ray, %struct.ray* %ray, i64 0, i32 1, i32 0 %2 = load double, double* %1, align 8 %3 = fmul double %2, %2 diff --git a/test/Transforms/Inline/inline-tail.ll b/test/Transforms/Inline/inline-tail.ll index 10b486c5154..dbb2ae6058e 100644 --- a/test/Transforms/Inline/inline-tail.ll +++ b/test/Transforms/Inline/inline-tail.ll @@ -56,13 +56,13 @@ define void @test_musttail_basic_a(i32* %p) { ; CHECK: musttail call void @test_byval_c( ; CHECK-NEXT: ret void -declare void @test_byval_c(i32* byval %p) -define internal void @test_byval_b(i32* byval %p) { - musttail call void @test_byval_c(i32* byval %p) +declare void @test_byval_c(i32* byval(i32) %p) +define internal void @test_byval_b(i32* byval(i32) %p) { + musttail call void @test_byval_c(i32* byval(i32) %p) ret void } -define void @test_byval_a(i32* byval %p) { - musttail call void @test_byval_b(i32* byval %p) +define void @test_byval_a(i32* byval(i32) %p) { + musttail call void @test_byval_b(i32* byval(i32) %p) ret void } @@ -74,15 +74,15 @@ define void @test_byval_a(i32* byval %p) { ; CHECK-NEXT: ret void declare void @escape(i8* %buf) -declare void @test_dynalloca_c(i32* byval %p, i32 %n) -define internal void @test_dynalloca_b(i32* byval %p, i32 %n) alwaysinline { +declare void @test_dynalloca_c(i32* byval(i32) %p, i32 %n) +define internal void @test_dynalloca_b(i32* byval(i32) %p, i32 %n) alwaysinline { %buf = alloca i8, i32 %n ; dynamic alloca call void @escape(i8* %buf) ; escape it - musttail call void @test_dynalloca_c(i32* byval %p, i32 %n) + musttail call void @test_dynalloca_c(i32* byval(i32) %p, i32 %n) ret void } -define void @test_dynalloca_a(i32* byval %p, i32 %n) { - musttail call void @test_dynalloca_b(i32* byval %p, i32 %n) +define void @test_dynalloca_a(i32* byval(i32) %p, i32 %n) { + musttail call void @test_dynalloca_b(i32* byval(i32) %p, i32 %n) ret void } diff --git a/test/Transforms/Inline/inline-varargs.ll b/test/Transforms/Inline/inline-varargs.ll index d229ef39d59..6fbcd123ddf 100644 --- a/test/Transforms/Inline/inline-varargs.ll +++ b/test/Transforms/Inline/inline-varargs.ll @@ -24,11 +24,11 @@ define signext i16 @test_callee_2(...) { } define void @test_caller_2(i8* %p, i8* %q, i16 %r) { - call signext i16 (...) @test_callee_2(i8* %p, i8* byval %q, i16 signext %r) + call signext i16 (...) @test_callee_2(i8* %p, i8* byval(i8) %q, i16 signext %r) ret void } ; CHECK-LABEL: define void @test_caller_2 -; CHECK: call signext i16 (...) @vararg_fn(i8* %p, i8* byval %q, i16 signext %r) [[FN_ATTRS:#[0-9]+]] +; CHECK: call signext i16 (...) @vararg_fn(i8* %p, i8* byval(i8) %q, i16 signext %r) [[FN_ATTRS:#[0-9]+]] define void @test_callee_3(i8* %p, ...) { call signext i16 (...) @vararg_fn() diff --git a/test/Transforms/InstCombine/2008-04-22-ByValBitcast.ll b/test/Transforms/InstCombine/2008-04-22-ByValBitcast.ll index 1ea0998bf70..e4452c863aa 100644 --- a/test/Transforms/InstCombine/2008-04-22-ByValBitcast.ll +++ b/test/Transforms/InstCombine/2008-04-22-ByValBitcast.ll @@ -8,7 +8,7 @@ target triple = "i386-apple-darwin9" define void @foo(i8* %context) nounwind { entry: %tmp1 = bitcast i8* %context to %struct.NSRect* ; <%struct.NSRect*> [#uses=1] - call void (i32, ...) @bar( i32 3, %struct.NSRect* byval align 4 %tmp1 ) nounwind + call void (i32, ...) @bar( i32 3, %struct.NSRect* byval(%struct.NSRect) align 4 %tmp1 ) nounwind ret void } diff --git a/test/Transforms/InstCombine/2009-01-08-AlignAlloca.ll b/test/Transforms/InstCombine/2009-01-08-AlignAlloca.ll index f6d0c4eb95c..3c1c04a3f8f 100644 --- a/test/Transforms/InstCombine/2009-01-08-AlignAlloca.ll +++ b/test/Transforms/InstCombine/2009-01-08-AlignAlloca.ll @@ -18,7 +18,7 @@ define i32 @bar(i64 %key_token2) nounwind { ; CHECK-NEXT: store i32 0, i32* [[TMP1]], align 4 ; CHECK-NEXT: [[TMP2:%.*]] = bitcast %struct.Key* [[IOSPEC]] to i64* ; CHECK-NEXT: store i64 [[KEY_TOKEN2:%.*]], i64* [[TMP2]], align 8 -; CHECK-NEXT: [[TMP3:%.*]] = call i32 (...) @foo(%struct.Key* nonnull byval align 4 [[IOSPEC]], i32* nonnull [[RET]]) [[ATTR0:#.*]] +; CHECK-NEXT: [[TMP3:%.*]] = call i32 (...) @foo(%struct.Key* nonnull byval(%struct.Key) align 4 [[IOSPEC]], i32* nonnull [[RET]]) [[ATTR0:#.*]] ; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[RET]], align 4 ; CHECK-NEXT: ret i32 [[TMP4]] ; @@ -34,7 +34,7 @@ entry: %3 = getelementptr %struct.Key, %struct.Key* %iospec, i32 0, i32 0 ; <{ i32, i32 }*> [#uses=1] %4 = bitcast { i32, i32 }* %3 to i64* ; [#uses=1] store i64 %key_token2, i64* %4, align 4 - %5 = call i32 (...) @foo(%struct.Key* byval align 4 %iospec, i32* %ret) nounwind ; [#uses=0] + %5 = call i32 (...) @foo(%struct.Key* byval(%struct.Key) align 4 %iospec, i32* %ret) nounwind ; [#uses=0] %6 = load i32, i32* %ret, align 4 ; [#uses=1] ret i32 %6 } diff --git a/test/Transforms/InstCombine/call-cast-target.ll b/test/Transforms/InstCombine/call-cast-target.ll index 881e80762ea..309cac32414 100644 --- a/test/Transforms/InstCombine/call-cast-target.ll +++ b/test/Transforms/InstCombine/call-cast-target.ll @@ -73,7 +73,7 @@ entry: ret i32 %call } -declare i1 @fn5({ i32, i32 }* byval align 4 %r) +declare i1 @fn5({ i32, i32 }* byval({ i32, i32 }) align 4 %r) define i1 @test5() { ; CHECK-LABEL: @test5 diff --git a/test/Transforms/InstCombine/crash.ll b/test/Transforms/InstCombine/crash.ll index fbb9675c0f1..ab6ca267143 100644 --- a/test/Transforms/InstCombine/crash.ll +++ b/test/Transforms/InstCombine/crash.ll @@ -294,7 +294,7 @@ declare i32 @test14f(i8* (i8*)*) nounwind define void @test14() nounwind readnone { entry: %tmp = bitcast i32 (i8* (i8*)*)* @test14f to i32 (i32*)* - %call10 = call i32 %tmp(i32* byval undef) + %call10 = call i32 %tmp(i32* byval(i32) undef) ret void } diff --git a/test/Transforms/InstCombine/memcpy-from-global.ll b/test/Transforms/InstCombine/memcpy-from-global.ll index 738cb9ba5a3..7757f002713 100644 --- a/test/Transforms/InstCombine/memcpy-from-global.ll +++ b/test/Transforms/InstCombine/memcpy-from-global.ll @@ -178,32 +178,32 @@ define void @test3_addrspacecast() { define void @test4() { ; CHECK-LABEL: @test4( -; CHECK-NEXT: call void @baz(i8* byval getelementptr inbounds (%T, %T* @G, i64 0, i32 0)) +; CHECK-NEXT: call void @baz(i8* byval(i8) getelementptr inbounds (%T, %T* @G, i64 0, i32 0)) ; CHECK-NEXT: ret void ; %A = alloca %T %a = bitcast %T* %A to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %a, i8* align 4 bitcast (%T* @G to i8*), i64 124, i1 false) - call void @baz(i8* byval %a) + call void @baz(i8* byval(i8) %a) ret void } declare void @llvm.lifetime.start.p0i8(i64, i8*) define void @test5() { ; CHECK-LABEL: @test5( -; CHECK-NEXT: call void @baz(i8* byval getelementptr inbounds (%T, %T* @G, i64 0, i32 0)) +; CHECK-NEXT: call void @baz(i8* byval(i8) getelementptr inbounds (%T, %T* @G, i64 0, i32 0)) ; CHECK-NEXT: ret void ; %A = alloca %T %a = bitcast %T* %A to i8* call void @llvm.lifetime.start.p0i8(i64 -1, i8* %a) call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %a, i8* align 4 bitcast (%T* @G to i8*), i64 124, i1 false) - call void @baz(i8* byval %a) + call void @baz(i8* byval(i8) %a) ret void } -declare void @baz(i8* byval) +declare void @baz(i8* byval(i8)) define void @test6() { diff --git a/test/Transforms/MemCpyOpt/memcpy.ll b/test/Transforms/MemCpyOpt/memcpy.ll index a2dd706d323..0c1b283a862 100644 --- a/test/Transforms/MemCpyOpt/memcpy.ll +++ b/test/Transforms/MemCpyOpt/memcpy.ll @@ -97,13 +97,13 @@ define void @test3(%0* noalias sret %agg.result) nounwind { ; PR8644 define void @test4(i8 *%P) { ; CHECK-LABEL: @test4( -; CHECK-NEXT: call void @test4a(i8* byval align 1 [[P:%.*]]) +; CHECK-NEXT: call void @test4a(i8* byval(i8) align 1 [[P:%.*]]) ; CHECK-NEXT: ret void ; %A = alloca %1 %a = bitcast %1* %A to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %a, i8* align 4 %P, i64 8, i1 false) - call void @test4a(i8* align 1 byval %a) + call void @test4a(i8* align 1 byval(i8) %a) ret void } @@ -113,13 +113,13 @@ define void @test4_addrspace(i8 addrspace(1)* %P) { ; CHECK-NEXT: [[A1:%.*]] = alloca [[TMP1:%.*]], align 8 ; CHECK-NEXT: [[A2:%.*]] = bitcast %1* [[A1]] to i8* ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p1i8.i64(i8* align 4 [[A2]], i8 addrspace(1)* align 4 [[P:%.*]], i64 8, i1 false) -; CHECK-NEXT: call void @test4a(i8* byval align 1 [[A2]]) +; CHECK-NEXT: call void @test4a(i8* byval(i8) align 1 [[A2]]) ; CHECK-NEXT: ret void ; %a1 = alloca %1 %a2 = bitcast %1* %a1 to i8* call void @llvm.memcpy.p0i8.p1i8.i64(i8* align 4 %a2, i8 addrspace(1)* align 4 %P, i64 8, i1 false) - call void @test4a(i8* align 1 byval %a2) + call void @test4a(i8* align 1 byval(i8) %a2) ret void } @@ -129,14 +129,14 @@ define void @test4_write_between(i8 *%P) { ; CHECK-NEXT: [[A2:%.*]] = bitcast %1* [[A1]] to i8* ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[A2]], i8* align 4 [[P:%.*]], i64 8, i1 false) ; CHECK-NEXT: store i8 0, i8* [[A2]], align 1 -; CHECK-NEXT: call void @test4a(i8* byval align 1 [[A2]]) +; CHECK-NEXT: call void @test4a(i8* byval(i8) align 1 [[A2]]) ; CHECK-NEXT: ret void ; %a1 = alloca %1 %a2 = bitcast %1* %a1 to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %a2, i8* align 4 %P, i64 8, i1 false) store i8 0, i8* %a2 - call void @test4a(i8* align 1 byval %a2) + call void @test4a(i8* align 1 byval(i8) %a2) ret void } @@ -146,14 +146,14 @@ define i8 @test4_read_between(i8 *%P) { ; CHECK-NEXT: [[A2:%.*]] = bitcast %1* [[A1]] to i8* ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[A2]], i8* align 4 [[P:%.*]], i64 8, i1 false) ; CHECK-NEXT: [[X:%.*]] = load i8, i8* [[A2]], align 1 -; CHECK-NEXT: call void @test4a(i8* byval align 1 [[A2]]) +; CHECK-NEXT: call void @test4a(i8* byval(i8) align 1 [[A2]]) ; CHECK-NEXT: ret i8 [[X]] ; %a1 = alloca %1 %a2 = bitcast %1* %a1 to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %a2, i8* align 4 %P, i64 8, i1 false) %x = load i8, i8* %a2 - call void @test4a(i8* align 1 byval %a2) + call void @test4a(i8* align 1 byval(i8) %a2) ret i8 %x } @@ -164,7 +164,7 @@ define void @test4_non_local(i8 *%P, i1 %c) { ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[A2]], i8* align 4 [[P:%.*]], i64 8, i1 false) ; CHECK-NEXT: br i1 [[C:%.*]], label [[CALL:%.*]], label [[EXIT:%.*]] ; CHECK: call: -; CHECK-NEXT: call void @test4a(i8* byval align 1 [[A2]]) +; CHECK-NEXT: call void @test4a(i8* byval(i8) align 1 [[A2]]) ; CHECK-NEXT: br label [[EXIT]] ; CHECK: exit: ; CHECK-NEXT: ret void @@ -175,14 +175,14 @@ define void @test4_non_local(i8 *%P, i1 %c) { br i1 %c, label %call, label %exit call: - call void @test4a(i8* align 1 byval %a2) + call void @test4a(i8* align 1 byval(i8) %a2) br label %exit exit: ret void } -declare void @test4a(i8* align 1 byval) +declare void @test4a(i8* align 1 byval(i8)) declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1) nounwind declare void @llvm.memcpy.p0i8.p1i8.i64(i8* nocapture, i8 addrspace(1)* nocapture, i64, i1) nounwind declare void @llvm.memcpy.p1i8.p1i8.i64(i8 addrspace(1)* nocapture, i8 addrspace(1)* nocapture, i64, i1) nounwind @@ -191,7 +191,7 @@ declare void @llvm.memcpy.p1i8.p1i8.i64(i8 addrspace(1)* nocapture, i8 addrspace @sS = external global %struct.S, align 16 -declare void @test5a(%struct.S* align 16 byval) nounwind ssp +declare void @test5a(%struct.S* align 16 byval(%struct.S)) nounwind ssp ; rdar://8713376 - This memcpy can't be eliminated. @@ -203,7 +203,7 @@ define i32 @test5(i32 %x) nounwind ssp { ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP]], i8* align 16 bitcast (%struct.S* @sS to i8*), i64 32, i1 false) ; CHECK-NEXT: [[A:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[Y]], i64 0, i32 1, i64 0 ; CHECK-NEXT: store i8 4, i8* [[A]], align 1 -; CHECK-NEXT: call void @test5a(%struct.S* byval align 16 [[Y]]) +; CHECK-NEXT: call void @test5a(%struct.S* byval(%struct.S) align 16 [[Y]]) ; CHECK-NEXT: ret i32 0 ; entry: @@ -212,7 +212,7 @@ entry: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %tmp, i8* align 16 bitcast (%struct.S* @sS to i8*), i64 32, i1 false) %a = getelementptr %struct.S, %struct.S* %y, i64 0, i32 1, i64 0 store i8 4, i8* %a - call void @test5a(%struct.S* align 16 byval %y) + call void @test5a(%struct.S* align 16 byval(%struct.S) %y) ret i32 0 } @@ -230,10 +230,10 @@ define void @test6(i8 *%P) { ; isn't itself 8 byte aligned. %struct.p = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } -define i32 @test7(%struct.p* nocapture align 8 byval %q) nounwind ssp { +define i32 @test7(%struct.p* nocapture align 8 byval(%struct.p) %q) nounwind ssp { ; CHECK-LABEL: @test7( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[CALL:%.*]] = call i32 @g(%struct.p* byval align 8 [[Q:%.*]]) [[ATTR0]] +; CHECK-NEXT: [[CALL:%.*]] = call i32 @g(%struct.p* byval(%struct.p) align 8 [[Q:%.*]]) [[ATTR0]] ; CHECK-NEXT: ret i32 [[CALL]] ; entry: @@ -241,11 +241,11 @@ entry: %tmp = bitcast %struct.p* %agg.tmp to i8* %tmp1 = bitcast %struct.p* %q to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %tmp, i8* align 4 %tmp1, i64 48, i1 false) - %call = call i32 @g(%struct.p* align 8 byval %agg.tmp) nounwind + %call = call i32 @g(%struct.p* align 8 byval(%struct.p) %agg.tmp) nounwind ret i32 %call } -declare i32 @g(%struct.p* align 8 byval) +declare i32 @g(%struct.p* align 8 byval(%struct.p)) declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i1) nounwind diff --git a/test/Transforms/MemCpyOpt/smaller.ll b/test/Transforms/MemCpyOpt/smaller.ll index cd5fa957d8b..19ececdd815 100644 --- a/test/Transforms/MemCpyOpt/smaller.ll +++ b/test/Transforms/MemCpyOpt/smaller.ll @@ -15,7 +15,7 @@ target datalayout = "e-p:32:32:32" @.str = private constant [11 x i8] c"0123456789\00" @cell = external global %struct.s -declare void @check(%struct.s* byval %p) nounwind +declare void @check(%struct.s* byval(%struct.s) %p) nounwind declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i1) nounwind define void @foo() nounwind { @@ -26,7 +26,7 @@ define void @foo() nounwind { ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 getelementptr inbounds (%struct.s, %struct.s* @cell, i32 0, i32 0, i32 0), i8* align 1 getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0), i32 11, i1 false) ; CHECK-NEXT: [[TMP:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.s* [[AGG_TMP]], i32 0, i32 0, i32 0 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP]], i8* align 4 getelementptr inbounds (%struct.s, %struct.s* @cell, i32 0, i32 0, i32 0), i32 16, i1 false) -; CHECK-NEXT: call void @check(%struct.s* byval [[AGG_TMP]]) +; CHECK-NEXT: call void @check(%struct.s* byval(%struct.s) [[AGG_TMP]]) ; CHECK-NEXT: ret void ; entry: @@ -35,6 +35,6 @@ entry: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 getelementptr inbounds (%struct.s, %struct.s* @cell, i32 0, i32 0, i32 0), i8* align 1 getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0), i32 11, i1 false) %tmp = getelementptr inbounds %struct.s, %struct.s* %agg.tmp, i32 0, i32 0, i32 0 call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %tmp, i8* align 4 getelementptr inbounds (%struct.s, %struct.s* @cell, i32 0, i32 0, i32 0), i32 16, i1 false) - call void @check(%struct.s* byval %agg.tmp) + call void @check(%struct.s* byval(%struct.s) %agg.tmp) ret void } diff --git a/test/Transforms/MemCpyOpt/sret.ll b/test/Transforms/MemCpyOpt/sret.ll index c509364d048..2d48855fb0a 100644 --- a/test/Transforms/MemCpyOpt/sret.ll +++ b/test/Transforms/MemCpyOpt/sret.ll @@ -7,7 +7,7 @@ target triple = "i686-apple-darwin9" %0 = type { x86_fp80, x86_fp80 } -define void @ccosl(%0* noalias sret %agg.result, %0* byval align 8 %z) nounwind { +define void @ccosl(%0* noalias sret %agg.result, %0* byval(%0) align 8 %z) nounwind { ; CHECK-LABEL: @ccosl( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[IZ:%.*]] = alloca [[TMP0:%.*]], align 16 @@ -21,7 +21,7 @@ define void @ccosl(%0* noalias sret %agg.result, %0* byval align 8 %z) nounwind ; CHECK-NEXT: [[TMP8:%.*]] = load x86_fp80, x86_fp80* [[TMP7]], align 16 ; CHECK-NEXT: store x86_fp80 [[TMP3]], x86_fp80* [[REAL]], align 16 ; CHECK-NEXT: store x86_fp80 [[TMP8]], x86_fp80* [[TMP4]], align 16 -; CHECK-NEXT: call void @ccoshl(%0* noalias sret [[AGG_RESULT:%.*]], %0* byval align 8 [[IZ]]) [[ATTR0:#.*]] +; CHECK-NEXT: call void @ccoshl(%0* noalias sret [[AGG_RESULT:%.*]], %0* byval(%0) align 8 [[IZ]]) [[ATTR0:#.*]] ; CHECK-NEXT: [[MEMTMP14:%.*]] = bitcast %0* [[MEMTMP]] to i8* ; CHECK-NEXT: [[AGG_RESULT15:%.*]] = bitcast %0* [[AGG_RESULT]] to i8* ; CHECK-NEXT: ret void @@ -38,13 +38,13 @@ entry: %tmp8 = load x86_fp80, x86_fp80* %tmp7, align 16 store x86_fp80 %tmp3, x86_fp80* %real, align 16 store x86_fp80 %tmp8, x86_fp80* %tmp4, align 16 - call void @ccoshl(%0* noalias sret %memtmp, %0* byval align 8 %iz) nounwind + call void @ccoshl(%0* noalias sret %memtmp, %0* byval(%0) align 8 %iz) nounwind %memtmp14 = bitcast %0* %memtmp to i8* %agg.result15 = bitcast %0* %agg.result to i8* call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 16 %agg.result15, i8* align 16 %memtmp14, i32 32, i1 false) ret void } -declare void @ccoshl(%0* noalias nocapture sret, %0* byval) nounwind +declare void @ccoshl(%0* noalias nocapture sret, %0* byval(%0)) nounwind declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i1) nounwind diff --git a/test/Transforms/MergeFunc/mismatching-attr-crash.ll b/test/Transforms/MergeFunc/mismatching-attr-crash.ll index e3f81c5776f..65d71d110fe 100644 --- a/test/Transforms/MergeFunc/mismatching-attr-crash.ll +++ b/test/Transforms/MergeFunc/mismatching-attr-crash.ll @@ -2,10 +2,10 @@ ; CHECK-LABEL: define void @foo ; CHECK: call void %bc -define void @foo(i8* byval %a0, i8* swiftself %a4) { +define void @foo(i8* byval(i8) %a0, i8* swiftself %a4) { entry: %bc = bitcast i8* %a0 to void (i8*, i8*)* - call void %bc(i8* byval %a0, i8* swiftself %a4) + call void %bc(i8* byval(i8) %a0, i8* swiftself %a4) ret void } diff --git a/test/Transforms/MergeICmps/X86/pr41917.ll b/test/Transforms/MergeICmps/X86/pr41917.ll index a697b462259..22cba94c582 100644 --- a/test/Transforms/MergeICmps/X86/pr41917.ll +++ b/test/Transforms/MergeICmps/X86/pr41917.ll @@ -7,7 +7,7 @@ target triple = "i386-pc-windows-msvc19.11.0" %class.a = type { i32, i32, i32, i32, i32 } ; Function Attrs: nounwind optsize -define dso_local zeroext i1 @pr41917(%class.a* byval nocapture readonly align 4 %g, %class.a* byval nocapture readonly align 4 %p2) local_unnamed_addr #0 { +define dso_local zeroext i1 @pr41917(%class.a* byval(%class.a) nocapture readonly align 4 %g, %class.a* byval(%class.a) nocapture readonly align 4 %p2) local_unnamed_addr #0 { ; CHECK-LABEL: @pr41917( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[CALL:%.*]] = tail call zeroext i1 @f2() #3 diff --git a/test/Transforms/NewGVN/pr17852.ll b/test/Transforms/NewGVN/pr17852.ll index a7907bd2f6d..7d888e95a0d 100644 --- a/test/Transforms/NewGVN/pr17852.ll +++ b/test/Transforms/NewGVN/pr17852.ll @@ -1,7 +1,7 @@ ; RUN: opt < %s -basic-aa -newgvn target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" %struct.S0 = type { [2 x i8], [2 x i8], [4 x i8], [2 x i8], i32, i32, i32, i32 } -define void @fn1(%struct.S0* byval align 8 %p1) { +define void @fn1(%struct.S0* byval(%struct.S0) align 8 %p1) { br label %for.cond for.cond: ; preds = %1, %0 br label %for.end diff --git a/test/Transforms/PGOProfile/indirect_call_promotion_byval.ll b/test/Transforms/PGOProfile/indirect_call_promotion_byval.ll index 9664d203a92..844b03c6459 100644 --- a/test/Transforms/PGOProfile/indirect_call_promotion_byval.ll +++ b/test/Transforms/PGOProfile/indirect_call_promotion_byval.ll @@ -19,7 +19,7 @@ entry: ret i32 %v } -define i32 @func5(%struct.Foo.1* byval %p) { +define i32 @func5(%struct.Foo.1* byval(%struct.Foo.1) %p) { entry: %gep = getelementptr inbounds %struct.Foo.1, %struct.Foo.1* %p, i32 0, i32 0 %v = load i32, i32* %gep diff --git a/test/Transforms/SCCP/2009-09-24-byval-ptr.ll b/test/Transforms/SCCP/2009-09-24-byval-ptr.ll index 9a027668036..e491e041228 100644 --- a/test/Transforms/SCCP/2009-09-24-byval-ptr.ll +++ b/test/Transforms/SCCP/2009-09-24-byval-ptr.ll @@ -3,7 +3,7 @@ ; PR5038 %struct.MYstr = type { i8, i32 } @mystr = internal global %struct.MYstr zeroinitializer ; <%struct.MYstr*> [#uses=3] -define internal void @vfu1(%struct.MYstr* byval align 4 %u) nounwind { +define internal void @vfu1(%struct.MYstr* byval(%struct.MYstr) align 4 %u) nounwind { entry: %0 = getelementptr %struct.MYstr, %struct.MYstr* %u, i32 0, i32 1 ; [#uses=1] store i32 99, i32* %0, align 4 @@ -17,7 +17,7 @@ return: ; preds = %entry ret void } -define internal i32 @vfu2(%struct.MYstr* byval align 4 %u) nounwind readonly { +define internal i32 @vfu2(%struct.MYstr* byval(%struct.MYstr) align 4 %u) nounwind readonly { entry: %0 = getelementptr %struct.MYstr, %struct.MYstr* %u, i32 0, i32 1 ; [#uses=1] %1 = load i32, i32* %0 @@ -32,8 +32,8 @@ entry: define i32 @unions() nounwind { entry: - call void @vfu1(%struct.MYstr* byval align 4 @mystr) nounwind - %result = call i32 @vfu2(%struct.MYstr* byval align 4 @mystr) nounwind + call void @vfu1(%struct.MYstr* byval(%struct.MYstr) align 4 @mystr) nounwind + %result = call i32 @vfu2(%struct.MYstr* byval(%struct.MYstr) align 4 @mystr) nounwind ; CHECK: ret i32 %result ret i32 %result } diff --git a/test/Transforms/SLPVectorizer/X86/reverse_extract_elements.ll b/test/Transforms/SLPVectorizer/X86/reverse_extract_elements.ll index 6843e852416..928457ea430 100644 --- a/test/Transforms/SLPVectorizer/X86/reverse_extract_elements.ll +++ b/test/Transforms/SLPVectorizer/X86/reverse_extract_elements.ll @@ -27,7 +27,7 @@ entry: ret float %add.3 } -define double @dotd(<4 x double>* byval nocapture readonly align 32, <4 x double>* byval nocapture readonly align 32) { +define double @dotd(<4 x double>* byval(<4 x double>) nocapture readonly align 32, <4 x double>* byval(<4 x double>) nocapture readonly align 32) { ; CHECK-LABEL: @dotd( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[X:%.*]] = load <4 x double>, <4 x double>* [[TMP0:%.*]], align 32 diff --git a/test/Transforms/SafeStack/X86/byval.ll b/test/Transforms/SafeStack/X86/byval.ll index 1b131aadef0..e4172137c43 100644 --- a/test/Transforms/SafeStack/X86/byval.ll +++ b/test/Transforms/SafeStack/X86/byval.ll @@ -7,7 +7,7 @@ target triple = "x86_64-unknown-linux-gnu" %struct.S = type { [100 x i32] } ; Safe access to a byval argument. -define i32 @ByValSafe(%struct.S* byval nocapture readonly align 8 %zzz) norecurse nounwind readonly safestack uwtable { +define i32 @ByValSafe(%struct.S* byval(%struct.S) nocapture readonly align 8 %zzz) norecurse nounwind readonly safestack uwtable { entry: ; CHECK-LABEL: @ByValSafe ; CHECK-NOT: __safestack_unsafe_stack_ptr @@ -19,7 +19,7 @@ entry: ; Unsafe access to a byval argument. ; Argument is copied to the unsafe stack. -define i32 @ByValUnsafe(%struct.S* byval nocapture readonly align 8 %zzz, i64 %idx) norecurse nounwind readonly safestack uwtable { +define i32 @ByValUnsafe(%struct.S* byval(%struct.S) nocapture readonly align 8 %zzz, i64 %idx) norecurse nounwind readonly safestack uwtable { entry: ; CHECK-LABEL: @ByValUnsafe ; CHECK: %[[A:.*]] = load {{.*}} @__safestack_unsafe_stack_ptr @@ -36,7 +36,7 @@ entry: ; Unsafe access to a byval argument. ; Argument is copied to the unsafe stack. ; Check that dest align of memcpy is set according to datalayout prefered alignment -define i32 @ByValUnsafe2(%struct.S* byval nocapture readonly %zzz, i64 %idx) norecurse nounwind readonly safestack uwtable { +define i32 @ByValUnsafe2(%struct.S* byval(%struct.S) nocapture readonly %zzz, i64 %idx) norecurse nounwind readonly safestack uwtable { entry: ; CHECK-LABEL: @ByValUnsafe ; CHECK: %[[A:.*]] = load {{.*}} @__safestack_unsafe_stack_ptr @@ -51,7 +51,7 @@ entry: } ; Highly aligned byval argument. -define i32 @ByValUnsafeAligned(%struct.S* byval nocapture readonly align 64 %zzz, i64 %idx) norecurse nounwind readonly safestack uwtable { +define i32 @ByValUnsafeAligned(%struct.S* byval(%struct.S) nocapture readonly align 64 %zzz, i64 %idx) norecurse nounwind readonly safestack uwtable { entry: ; CHECK-LABEL: @ByValUnsafeAligned ; CHECK: %[[A:.*]] = load {{.*}} @__safestack_unsafe_stack_ptr diff --git a/test/Transforms/SafeStack/X86/debug-loc.ll b/test/Transforms/SafeStack/X86/debug-loc.ll index ffd76d4929f..2b0018a7153 100644 --- a/test/Transforms/SafeStack/X86/debug-loc.ll +++ b/test/Transforms/SafeStack/X86/debug-loc.ll @@ -8,7 +8,7 @@ target triple = "x86_64-unknown-linux-gnu" %struct.S = type { [100 x i8] } ; Function Attrs: safestack uwtable -define void @f(%struct.S* byval align 8 %zzz) #0 !dbg !12 { +define void @f(%struct.S* byval(%struct.S) align 8 %zzz) #0 !dbg !12 { ; CHECK: define void @f entry: diff --git a/test/Transforms/TailCallElim/basic.ll b/test/Transforms/TailCallElim/basic.ll index 6116014a024..98274c83bea 100644 --- a/test/Transforms/TailCallElim/basic.ll +++ b/test/Transforms/TailCallElim/basic.ll @@ -153,7 +153,7 @@ cond_false: } ; Don't tail call if a byval arg is captured. -define void @test9(i32* byval %a) { +define void @test9(i32* byval(i32) %a) { ; CHECK-LABEL: define void @test9( ; CHECK: {{^ *}}call void @use( call void @use(i32* %a) @@ -213,27 +213,27 @@ entry: ; point, and both calls below can be marked tail. define void @test13() { ; CHECK-LABEL: @test13 -; CHECK: tail call void @bar(%struct.foo* byval %f) +; CHECK: tail call void @bar(%struct.foo* byval(%struct.foo) %f) ; CHECK: tail call void @bar(%struct.foo* null) entry: %f = alloca %struct.foo - call void @bar(%struct.foo* byval %f) + call void @bar(%struct.foo* byval(%struct.foo) %f) call void @bar(%struct.foo* null) ret void } ; A call which passes a byval parameter using byval can be marked tail. -define void @test14(%struct.foo* byval %f) { +define void @test14(%struct.foo* byval(%struct.foo) %f) { ; CHECK-LABEL: @test14 ; CHECK: tail call void @bar entry: - call void @bar(%struct.foo* byval %f) + call void @bar(%struct.foo* byval(%struct.foo) %f) ret void } ; If a byval parameter is copied into an alloca and passed byval the call can ; be marked tail. -define void @test15(%struct.foo* byval %f) { +define void @test15(%struct.foo* byval(%struct.foo) %f) { ; CHECK-LABEL: @test15 ; CHECK: tail call void @bar entry: @@ -241,9 +241,9 @@ entry: %0 = bitcast %struct.foo* %agg.tmp to i8* %1 = bitcast %struct.foo* %f to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* %1, i64 40, i1 false) - call void @bar(%struct.foo* byval %agg.tmp) + call void @bar(%struct.foo* byval(%struct.foo) %agg.tmp) ret void } -declare void @bar(%struct.foo* byval) +declare void @bar(%struct.foo* byval(%struct.foo)) declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i1) diff --git a/test/Verifier/amdgpu-cc.ll b/test/Verifier/amdgpu-cc.ll index 1cd1b346741..df2a8199e0b 100644 --- a/test/Verifier/amdgpu-cc.ll +++ b/test/Verifier/amdgpu-cc.ll @@ -64,49 +64,49 @@ define spir_kernel void @varargs_spir_kernel(...) { ; CHECK: Calling convention disallows byval ; CHECK-NEXT: void (i32 addrspace(5)*)* @byval_cc_amdgpu_kernel -define amdgpu_kernel void @byval_cc_amdgpu_kernel(i32 addrspace(5)* byval %ptr) { +define amdgpu_kernel void @byval_cc_amdgpu_kernel(i32 addrspace(5)* byval(i32) %ptr) { ret void } ; CHECK: Calling convention disallows byval ; CHECK-NEXT: void (i32 addrspace(1)*)* @byval_as1_cc_amdgpu_kernel -define amdgpu_kernel void @byval_as1_cc_amdgpu_kernel(i32 addrspace(1)* byval %ptr) { +define amdgpu_kernel void @byval_as1_cc_amdgpu_kernel(i32 addrspace(1)* byval(i32) %ptr) { ret void } ; CHECK: Calling convention disallows byval ; CHECK-NEXT: void (i32*)* @byval_as0_cc_amdgpu_kernel -define amdgpu_kernel void @byval_as0_cc_amdgpu_kernel(i32* byval %ptr) { +define amdgpu_kernel void @byval_as0_cc_amdgpu_kernel(i32* byval(i32) %ptr) { ret void } ; CHECK: Calling convention disallows byval ; CHECK-NEXT: void (i32 addrspace(5)*)* @byval_cc_amdgpu_vs -define amdgpu_vs void @byval_cc_amdgpu_vs(i32 addrspace(5)* byval %ptr) { +define amdgpu_vs void @byval_cc_amdgpu_vs(i32 addrspace(5)* byval(i32) %ptr) { ret void } ; CHECK: Calling convention disallows byval ; CHECK-NEXT: void (i32 addrspace(5)*)* @byval_cc_amdgpu_hs -define amdgpu_hs void @byval_cc_amdgpu_hs(i32 addrspace(5)* byval %ptr) { +define amdgpu_hs void @byval_cc_amdgpu_hs(i32 addrspace(5)* byval(i32) %ptr) { ret void } ; CHECK: Calling convention disallows byval ; CHECK-NEXT: void (i32 addrspace(5)*)* @byval_cc_amdgpu_gs -define amdgpu_gs void @byval_cc_amdgpu_gs(i32 addrspace(5)* byval %ptr) { +define amdgpu_gs void @byval_cc_amdgpu_gs(i32 addrspace(5)* byval(i32) %ptr) { ret void } ; CHECK: Calling convention disallows byval ; CHECK-NEXT: void (i32 addrspace(5)*)* @byval_cc_amdgpu_ps -define amdgpu_ps void @byval_cc_amdgpu_ps(i32 addrspace(5)* byval %ptr) { +define amdgpu_ps void @byval_cc_amdgpu_ps(i32 addrspace(5)* byval(i32) %ptr) { ret void } ; CHECK: Calling convention disallows byval ; CHECK-NEXT: void (i32 addrspace(5)*)* @byval_cc_amdgpu_cs -define amdgpu_cs void @byval_cc_amdgpu_cs(i32 addrspace(5)* byval %ptr) { +define amdgpu_cs void @byval_cc_amdgpu_cs(i32 addrspace(5)* byval(i32) %ptr) { ret void } diff --git a/test/Verifier/byval-4.ll b/test/Verifier/byval-4.ll index b6f9c67962c..21d196a0ce3 100644 --- a/test/Verifier/byval-4.ll +++ b/test/Verifier/byval-4.ll @@ -1,4 +1,4 @@ ; RUN: llvm-as %s -o /dev/null %struct.foo = type { i64 } -declare void @h(%struct.foo* byval %num) +declare void @h(%struct.foo* byval(%struct.foo) %num) diff --git a/test/Verifier/inalloca1.ll b/test/Verifier/inalloca1.ll index 38b5507abba..350c182d8c2 100644 --- a/test/Verifier/inalloca1.ll +++ b/test/Verifier/inalloca1.ll @@ -1,6 +1,6 @@ ; RUN: not llvm-as %s -o /dev/null 2>&1 | FileCheck %s -declare void @a(i64* byval inalloca %p) +declare void @a(i64* byval(i64) inalloca %p) ; CHECK: Attributes {{.*}} are incompatible declare void @b(i64* inreg inalloca %p) diff --git a/test/Verifier/musttail-invalid.ll b/test/Verifier/musttail-invalid.ll index 041d3a481cf..5ec4ce5ecd2 100644 --- a/test/Verifier/musttail-invalid.ll +++ b/test/Verifier/musttail-invalid.ll @@ -40,7 +40,7 @@ define void @mismatched_retty(i32) { } declare void @mismatched_byval_callee({ i32 }*) -define void @mismatched_byval({ i32 }* byval %a) { +define void @mismatched_byval({ i32 }* byval({ i32 }) %a) { ; CHECK: mismatched ABI impacting function attributes musttail call void @mismatched_byval_callee({ i32 }* %a) ret void @@ -60,10 +60,10 @@ define void @mismatched_sret(i32* %a) { ret void } -declare void @mismatched_alignment_callee(i32* byval align 8) -define void @mismatched_alignment(i32* byval align 4 %a) { +declare void @mismatched_alignment_callee(i32* byval(i32) align 8) +define void @mismatched_alignment(i32* byval(i32) align 4 %a) { ; CHECK: mismatched ABI impacting function attributes - musttail call void @mismatched_alignment_callee(i32* byval align 8 %a) + musttail call void @mismatched_alignment_callee(i32* byval(i32) align 8 %a) ret void }