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[Hexagon] Adding doubleword multiplies with and without accumulation.
llvm-svn: 224293
This commit is contained in:
Colin LeMahieu
parent
d27db299e8
commit
4c0e2a35a6
@ -25,6 +25,11 @@ def I64 : PatLeaf<(i64 DoubleRegs:$R)>;
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def F32 : PatLeaf<(f32 IntRegs:$R)>;
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def F64 : PatLeaf<(f64 DoubleRegs:$R)>;
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// Pattern fragments to extract the low and high subregisters from a
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// 64-bit value.
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def LoReg: OutPatFrag<(ops node:$Rs),
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(EXTRACT_SUBREG (i64 $Rs), subreg_loreg)>;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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@ -1744,6 +1749,13 @@ let Defs = [R29, R30, R31], Uses = [R29], hasSideEffects = 0 in {
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//===----------------------------------------------------------------------===//
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// MTYPE/MPYH +
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Template Class
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// MPYS / Multipy signed/unsigned halfwords
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//Rd=mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat]
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//===----------------------------------------------------------------------===//
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let hasNewValue = 1, opNewValue = 0 in
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class T_M2_mpy < bits<2> LHbits, bit isSat, bit isRnd,
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bit hasShift, bit isUnsigned>
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@ -2279,6 +2291,121 @@ def M2_mpyud_hl_s1: T_M2_mpyd<0b10, 0, 1, 1>;
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def M2_mpyud_lh_s1: T_M2_mpyd<0b01, 0, 1, 1>;
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def M2_mpyud_ll_s1: T_M2_mpyd<0b00, 0, 1, 1>;
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}
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//===----------------------------------------------------------------------===//
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// Template Class for xtype mpy:
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// Vector multiply
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// Complex multiply
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// multiply 32X32 and use full result
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//===----------------------------------------------------------------------===//
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let hasSideEffects = 0 in
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class T_XTYPE_mpy64 <string mnemonic, bits<3> MajOp, bits<3> MinOp,
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bit isSat, bit hasShift, bit isConj>
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: MInst <(outs DoubleRegs:$Rdd),
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(ins IntRegs:$Rs, IntRegs:$Rt),
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"$Rdd = "#mnemonic#"($Rs, $Rt"#!if(isConj,"*)",")")
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#!if(hasShift,":<<1","")
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#!if(isSat,":sat",""),
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[] > {
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bits<5> Rdd;
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bits<5> Rs;
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bits<5> Rt;
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let IClass = 0b1110;
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let Inst{27-24} = 0b0101;
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let Inst{23-21} = MajOp;
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let Inst{20-16} = Rs;
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let Inst{12-8} = Rt;
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let Inst{7-5} = MinOp;
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let Inst{4-0} = Rdd;
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}
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//===----------------------------------------------------------------------===//
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// Template Class for xtype mpy with accumulation into 64-bit:
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// Vector multiply
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// Complex multiply
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// multiply 32X32 and use full result
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//===----------------------------------------------------------------------===//
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class T_XTYPE_mpy64_acc <string op1, string op2, bits<3> MajOp, bits<3> MinOp,
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bit isSat, bit hasShift, bit isConj>
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: MInst <(outs DoubleRegs:$Rxx),
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(ins DoubleRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
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"$Rxx "#op2#"= "#op1#"($Rs, $Rt"#!if(isConj,"*)",")")
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#!if(hasShift,":<<1","")
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#!if(isSat,":sat",""),
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[] , "$dst2 = $Rxx" > {
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bits<5> Rxx;
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bits<5> Rs;
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bits<5> Rt;
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let IClass = 0b1110;
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let Inst{27-24} = 0b0111;
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let Inst{23-21} = MajOp;
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let Inst{20-16} = Rs;
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let Inst{12-8} = Rt;
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let Inst{7-5} = MinOp;
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let Inst{4-0} = Rxx;
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}
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// MPY - Multiply and use full result
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// Rdd = mpy[u](Rs,Rt)
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let isCodeGenOnly = 0 in {
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def M2_dpmpyss_s0 : T_XTYPE_mpy64 < "mpy", 0b000, 0b000, 0, 0, 0>;
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def M2_dpmpyuu_s0 : T_XTYPE_mpy64 < "mpyu", 0b010, 0b000, 0, 0, 0>;
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// Rxx[+-]= mpy[u](Rs,Rt)
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def M2_dpmpyss_acc_s0 : T_XTYPE_mpy64_acc < "mpy", "+", 0b000, 0b000, 0, 0, 0>;
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def M2_dpmpyss_nac_s0 : T_XTYPE_mpy64_acc < "mpy", "-", 0b001, 0b000, 0, 0, 0>;
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def M2_dpmpyuu_acc_s0 : T_XTYPE_mpy64_acc < "mpyu", "+", 0b010, 0b000, 0, 0, 0>;
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def M2_dpmpyuu_nac_s0 : T_XTYPE_mpy64_acc < "mpyu", "-", 0b011, 0b000, 0, 0, 0>;
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}
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def: Pat<(i64 (mul (i64 (anyext (i32 IntRegs:$src1))),
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(i64 (anyext (i32 IntRegs:$src2))))),
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(M2_dpmpyuu_s0 IntRegs:$src1, IntRegs:$src2)>;
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def: Pat<(i64 (mul (i64 (sext (i32 IntRegs:$src1))),
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(i64 (sext (i32 IntRegs:$src2))))),
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(M2_dpmpyss_s0 IntRegs:$src1, IntRegs:$src2)>;
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def: Pat<(i64 (mul (is_sext_i32:$src1),
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(is_sext_i32:$src2))),
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(M2_dpmpyss_s0 (LoReg DoubleRegs:$src1), (LoReg DoubleRegs:$src2))>;
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// Multiply and accumulate, use full result.
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// Rxx[+-]=mpy(Rs,Rt)
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def: Pat<(i64 (add (i64 DoubleRegs:$src1),
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(mul (i64 (sext (i32 IntRegs:$src2))),
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(i64 (sext (i32 IntRegs:$src3)))))),
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(M2_dpmpyss_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
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def: Pat<(i64 (sub (i64 DoubleRegs:$src1),
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(mul (i64 (sext (i32 IntRegs:$src2))),
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(i64 (sext (i32 IntRegs:$src3)))))),
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(M2_dpmpyss_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
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def: Pat<(i64 (add (i64 DoubleRegs:$src1),
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(mul (i64 (anyext (i32 IntRegs:$src2))),
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(i64 (anyext (i32 IntRegs:$src3)))))),
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(M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
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def: Pat<(i64 (add (i64 DoubleRegs:$src1),
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(mul (i64 (zext (i32 IntRegs:$src2))),
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(i64 (zext (i32 IntRegs:$src3)))))),
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(M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
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def: Pat<(i64 (sub (i64 DoubleRegs:$src1),
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(mul (i64 (anyext (i32 IntRegs:$src2))),
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(i64 (anyext (i32 IntRegs:$src3)))))),
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(M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
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def: Pat<(i64 (sub (i64 DoubleRegs:$src1),
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(mul (i64 (zext (i32 IntRegs:$src2))),
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(i64 (zext (i32 IntRegs:$src3)))))),
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(M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
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// Multiply and use lower result.
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// Rd=+mpyi(Rs,#u8)
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@ -856,3 +856,12 @@ def symbolHi32 : Operand<i32> {
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def symbolLo32 : Operand<i32> {
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let PrintMethod = "printSymbolLo";
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}
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// Return true if for a 32 to 64-bit sign-extended load.
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def is_sext_i32 : PatLeaf<(i64 DoubleRegs:$src1), [{
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LoadSDNode *LD = dyn_cast<LoadSDNode>(N);
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if (!LD)
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return false;
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return LD->getExtensionType() == ISD::SEXTLOAD &&
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LD->getMemoryVT().getScalarType() == MVT::i32;
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}]>;
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@ -174,3 +174,15 @@
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# CHECK: r17 = mpy(r21, r31.h):<<1:rnd:sat
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0x91 0xdf 0xf5 0xed
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# CHECK: r17 = mpy(r21, r31.l):<<1:rnd:sat
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0x10 0xdf 0x15 0xe5
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# CHECK: r17:16 = mpy(r21, r31)
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0x10 0xdf 0x55 0xe5
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# CHECK: r17:16 = mpyu(r21, r31)
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0x10 0xdf 0x15 0xe7
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# CHECK: r17:16 += mpy(r21, r31)
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0x10 0xdf 0x35 0xe7
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# CHECK: r17:16 -= mpy(r21, r31)
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0x10 0xdf 0x55 0xe7
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# CHECK: r17:16 += mpyu(r21, r31)
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0x10 0xdf 0x75 0xe7
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# CHECK: r17:16 -= mpyu(r21, r31)
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