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[ARM] Accept a subset of Thumb GPR register class when emitting an SP-relative
load instruction The function `Thumb1InstrInfo::loadRegFromStackSlot` accepts only the `tGPR` register class. The function serves to emit a `tLDRspi` instruction and certainly any subset of the `tGPR` register class is a valid destination of the load. Differential revision: https://reviews.llvm.org/D42535 llvm-svn: 323514
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@ -109,11 +109,11 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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assert((RC == &ARM::tGPRRegClass ||
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assert((RC->hasSuperClassEq(&ARM::tGPRRegClass) ||
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(TargetRegisterInfo::isPhysicalRegister(DestReg) &&
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isARMLowRegister(DestReg))) && "Unknown regclass!");
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if (RC == &ARM::tGPRRegClass ||
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if (RC->hasSuperClassEq(&ARM::tGPRRegClass) ||
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(TargetRegisterInfo::isPhysicalRegister(DestReg) &&
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isARMLowRegister(DestReg))) {
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DebugLoc DL;
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@ -103,3 +103,28 @@ define i32 @test7() {
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}
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declare i32 @bar(i32, i32, i32, i32)
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; Regression test for failure to load indirect branch target (class tcGPR) from
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; a stack slot.
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%struct.S = type { i32 }
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define void @test8(i32 (i32, i32, i32)* nocapture %fn, i32 %x) local_unnamed_addr {
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entry:
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%call = tail call %struct.S* bitcast (%struct.S* (...)* @test8_u to %struct.S* ()*)()
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%a = getelementptr inbounds %struct.S, %struct.S* %call, i32 0, i32 0
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%0 = load i32, i32* %a, align 4
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%call1 = tail call i32 @test8_h(i32 0)
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%call2 = tail call i32 @test8_g(i32 %0, i32 %call1, i32 0)
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store i32 %x, i32* %a, align 4
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%call4 = tail call i32 %fn(i32 1, i32 2, i32 3)
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ret void
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}
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declare %struct.S* @test8_u(...)
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declare i32 @test8_g(i32, i32, i32)
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declare i32 @test8_h(i32)
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; CHECK: str r0, [sp] @ 4-byte Spill
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; CHECK: ldr r3, [sp] @ 4-byte Reload
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; CHECK: bx r3
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