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[aarch64] add def-pats for dot product
This patch adds the patterns to select the dot product instructions. Tested on aarch64-linux with make check-all. Differential Revision: https://reviews.llvm.org/D67645 llvm-svn: 372408
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Sebastian Pop
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@ -7000,5 +7000,114 @@ let AddedComplexity = 10 in {
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def : Pat<(i32 (extractelt (v2i32 V64:$V), (i64 0))), (EXTRACT_SUBREG V64:$V, ssub)>;
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}
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// dot_v4i8
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class mul_v4i8<SDPatternOperator ldop> :
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PatFrag<(ops node:$Rn, node:$Rm, node:$offset),
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(mul (ldop (add node:$Rn, node:$offset)),
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(ldop (add node:$Rm, node:$offset)))>;
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class mulz_v4i8<SDPatternOperator ldop> :
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PatFrag<(ops node:$Rn, node:$Rm),
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(mul (ldop node:$Rn), (ldop node:$Rm))>;
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def load_v4i8 :
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OutPatFrag<(ops node:$R),
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(INSERT_SUBREG
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(v2i32 (IMPLICIT_DEF)),
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(i32 (COPY_TO_REGCLASS (LDRWui node:$R, (i64 0)), FPR32)),
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ssub)>;
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class dot_v4i8<Instruction DOT, SDPatternOperator ldop> :
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Pat<(i32 (add (mul_v4i8<ldop> GPR64sp:$Rn, GPR64sp:$Rm, (i64 3)),
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(add (mul_v4i8<ldop> GPR64sp:$Rn, GPR64sp:$Rm, (i64 2)),
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(add (mul_v4i8<ldop> GPR64sp:$Rn, GPR64sp:$Rm, (i64 1)),
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(mulz_v4i8<ldop> GPR64sp:$Rn, GPR64sp:$Rm))))),
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(EXTRACT_SUBREG (i64 (DOT (DUPv2i32gpr WZR),
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(load_v4i8 GPR64sp:$Rn),
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(load_v4i8 GPR64sp:$Rm))),
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sub_32)>, Requires<[HasDotProd]>;
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// dot_v8i8
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class ee_v8i8<SDPatternOperator extend> :
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PatFrag<(ops node:$V, node:$K),
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(v4i16 (extract_subvector (v8i16 (extend node:$V)), node:$K))>;
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class mul_v8i8<SDPatternOperator mulop, SDPatternOperator extend> :
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PatFrag<(ops node:$M, node:$N, node:$K),
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(mulop (v4i16 (ee_v8i8<extend> node:$M, node:$K)),
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(v4i16 (ee_v8i8<extend> node:$N, node:$K)))>;
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class idot_v8i8<SDPatternOperator mulop, SDPatternOperator extend> :
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PatFrag<(ops node:$M, node:$N),
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(i32 (extractelt
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(v4i32 (AArch64uaddv
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(add (mul_v8i8<mulop, extend> node:$M, node:$N, (i64 0)),
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(mul_v8i8<mulop, extend> node:$M, node:$N, (i64 4))))),
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(i64 0)))>;
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// vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
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def VADDV_32 : OutPatFrag<(ops node:$R), (ADDPv2i32 node:$R, node:$R)>;
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class odot_v8i8<Instruction DOT> :
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OutPatFrag<(ops node:$Vm, node:$Vn),
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(EXTRACT_SUBREG
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(VADDV_32
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(i64 (DOT (DUPv2i32gpr WZR),
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(v8i8 node:$Vm),
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(v8i8 node:$Vn)))),
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sub_32)>;
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class dot_v8i8<Instruction DOT, SDPatternOperator mulop,
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SDPatternOperator extend> :
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Pat<(idot_v8i8<mulop, extend> V64:$Vm, V64:$Vn),
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(odot_v8i8<DOT> V64:$Vm, V64:$Vn)>,
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Requires<[HasDotProd]>;
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// dot_v16i8
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class ee_v16i8<SDPatternOperator extend> :
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PatFrag<(ops node:$V, node:$K1, node:$K2),
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(v4i16 (extract_subvector
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(v8i16 (extend
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(v8i8 (extract_subvector node:$V, node:$K1)))), node:$K2))>;
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class mul_v16i8<SDPatternOperator mulop, SDPatternOperator extend> :
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PatFrag<(ops node:$M, node:$N, node:$K1, node:$K2),
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(v4i32
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(mulop (v4i16 (ee_v16i8<extend> node:$M, node:$K1, node:$K2)),
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(v4i16 (ee_v16i8<extend> node:$N, node:$K1, node:$K2))))>;
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class idot_v16i8<SDPatternOperator m, SDPatternOperator x> :
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PatFrag<(ops node:$M, node:$N),
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(i32 (extractelt
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(v4i32 (AArch64uaddv
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(add
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(add (mul_v16i8<m, x> node:$M, node:$N, (i64 0), (i64 0)),
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(mul_v16i8<m, x> node:$M, node:$N, (i64 8), (i64 0))),
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(add (mul_v16i8<m, x> node:$M, node:$N, (i64 0), (i64 4)),
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(mul_v16i8<m, x> node:$M, node:$N, (i64 8), (i64 4)))))),
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(i64 0)))>;
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class odot_v16i8<Instruction DOT> :
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OutPatFrag<(ops node:$Vm, node:$Vn),
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(i32 (ADDVv4i32v
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(DOT (DUPv4i32gpr WZR), node:$Vm, node:$Vn)))>;
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class dot_v16i8<Instruction DOT, SDPatternOperator mulop,
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SDPatternOperator extend> :
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Pat<(idot_v16i8<mulop, extend> V128:$Vm, V128:$Vn),
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(odot_v16i8<DOT> V128:$Vm, V128:$Vn)>,
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Requires<[HasDotProd]>;
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let AddedComplexity = 10 in {
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def : dot_v4i8<SDOTv8i8, sextloadi8>;
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def : dot_v4i8<UDOTv8i8, zextloadi8>;
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def : dot_v8i8<SDOTv8i8, AArch64smull, sext>;
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def : dot_v8i8<UDOTv8i8, AArch64umull, zext>;
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def : dot_v16i8<SDOTv16i8, AArch64smull, sext>;
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def : dot_v16i8<UDOTv16i8, AArch64umull, zext>;
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// FIXME: add patterns to generate vector by element dot product.
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// FIXME: add SVE dot-product patterns.
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}
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include "AArch64InstrAtomics.td"
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include "AArch64SVEInstrInfo.td"
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@ -128,3 +128,145 @@ entry:
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%vdot1.i = call <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %.cast3) #2
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ret <4 x i32> %vdot1.i
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}
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define fastcc void @test_sdot_v4i8(i8* noalias nocapture %0, i8* noalias nocapture readonly %1, i8* noalias nocapture readonly %2) {
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entry:
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; CHECK-LABEL: test_sdot_v4i8:
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; CHECK: sdot {{v[0-9]+}}.2s, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
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%3 = bitcast i8* %0 to i32*
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%4 = load i8, i8* %1, align 1
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%5 = sext i8 %4 to i32
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%6 = load i8, i8* %2, align 1
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%7 = sext i8 %6 to i32
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%8 = mul nsw i32 %7, %5
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%9 = getelementptr inbounds i8, i8* %1, i64 1
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%10 = load i8, i8* %9, align 1
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%11 = sext i8 %10 to i32
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%12 = getelementptr inbounds i8, i8* %2, i64 1
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%13 = load i8, i8* %12, align 1
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%14 = sext i8 %13 to i32
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%15 = mul nsw i32 %14, %11
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%16 = add nsw i32 %15, %8
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%17 = getelementptr inbounds i8, i8* %1, i64 2
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%18 = load i8, i8* %17, align 1
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%19 = sext i8 %18 to i32
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%20 = getelementptr inbounds i8, i8* %2, i64 2
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%21 = load i8, i8* %20, align 1
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%22 = sext i8 %21 to i32
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%23 = mul nsw i32 %22, %19
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%24 = add nsw i32 %23, %16
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%25 = getelementptr inbounds i8, i8* %1, i64 3
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%26 = load i8, i8* %25, align 1
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%27 = sext i8 %26 to i32
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%28 = getelementptr inbounds i8, i8* %2, i64 3
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%29 = load i8, i8* %28, align 1
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%30 = sext i8 %29 to i32
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%31 = mul nsw i32 %30, %27
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%32 = add nsw i32 %31, %24
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store i32 %32, i32* %3, align 64
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ret void
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}
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define fastcc void @test_udot_v4i8(i8* noalias nocapture %0, i8* noalias nocapture readonly %1, i8* noalias nocapture readonly %2) {
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entry:
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; CHECK-LABEL: test_udot_v4i8:
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; CHECK: udot {{v[0-9]+}}.2s, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
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%3 = bitcast i8* %0 to i32*
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%4 = load i8, i8* %1, align 1
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%5 = zext i8 %4 to i32
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%6 = load i8, i8* %2, align 1
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%7 = zext i8 %6 to i32
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%8 = mul nsw i32 %7, %5
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%9 = getelementptr inbounds i8, i8* %1, i64 1
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%10 = load i8, i8* %9, align 1
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%11 = zext i8 %10 to i32
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%12 = getelementptr inbounds i8, i8* %2, i64 1
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%13 = load i8, i8* %12, align 1
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%14 = zext i8 %13 to i32
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%15 = mul nsw i32 %14, %11
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%16 = add nsw i32 %15, %8
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%17 = getelementptr inbounds i8, i8* %1, i64 2
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%18 = load i8, i8* %17, align 1
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%19 = zext i8 %18 to i32
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%20 = getelementptr inbounds i8, i8* %2, i64 2
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%21 = load i8, i8* %20, align 1
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%22 = zext i8 %21 to i32
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%23 = mul nsw i32 %22, %19
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%24 = add nsw i32 %23, %16
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%25 = getelementptr inbounds i8, i8* %1, i64 3
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%26 = load i8, i8* %25, align 1
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%27 = zext i8 %26 to i32
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%28 = getelementptr inbounds i8, i8* %2, i64 3
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%29 = load i8, i8* %28, align 1
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%30 = zext i8 %29 to i32
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%31 = mul nsw i32 %30, %27
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%32 = add nsw i32 %31, %24
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store i32 %32, i32* %3, align 64
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ret void
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}
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declare i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32>)
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define i32 @test_udot_v8i8(i8* nocapture readonly %a, i8* nocapture readonly %b) {
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entry:
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; CHECK-LABEL: test_udot_v8i8:
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; CHECK: udot {{v[0-9]+}}.2s, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
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%0 = bitcast i8* %a to <8 x i8>*
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%1 = load <8 x i8>, <8 x i8>* %0
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%2 = zext <8 x i8> %1 to <8 x i32>
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%3 = bitcast i8* %b to <8 x i8>*
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%4 = load <8 x i8>, <8 x i8>* %3
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%5 = zext <8 x i8> %4 to <8 x i32>
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%6 = mul nuw nsw <8 x i32> %5, %2
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%7 = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> %6)
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ret i32 %7
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}
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define i32 @test_sdot_v8i8(i8* nocapture readonly %a, i8* nocapture readonly %b) {
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entry:
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; CHECK-LABEL: test_sdot_v8i8:
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; CHECK: sdot {{v[0-9]+}}.2s, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
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%0 = bitcast i8* %a to <8 x i8>*
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%1 = load <8 x i8>, <8 x i8>* %0
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%2 = sext <8 x i8> %1 to <8 x i32>
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%3 = bitcast i8* %b to <8 x i8>*
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%4 = load <8 x i8>, <8 x i8>* %3
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%5 = sext <8 x i8> %4 to <8 x i32>
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%6 = mul nsw <8 x i32> %5, %2
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%7 = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> %6)
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ret i32 %7
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}
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declare i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32>)
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define i32 @test_udot_v16i8(i8* nocapture readonly %a, i8* nocapture readonly %b, i32 %sum) {
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entry:
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; CHECK-LABEL: test_udot_v16i8:
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; CHECK: udot {{v[0-9]+}}.4s, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
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%0 = bitcast i8* %a to <16 x i8>*
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%1 = load <16 x i8>, <16 x i8>* %0
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%2 = zext <16 x i8> %1 to <16 x i32>
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%3 = bitcast i8* %b to <16 x i8>*
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%4 = load <16 x i8>, <16 x i8>* %3
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%5 = zext <16 x i8> %4 to <16 x i32>
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%6 = mul nuw nsw <16 x i32> %5, %2
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%7 = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %6)
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%op.extra = add i32 %7, %sum
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ret i32 %op.extra
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}
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define i32 @test_sdot_v16i8(i8* nocapture readonly %a, i8* nocapture readonly %b, i32 %sum) {
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entry:
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; CHECK-LABEL: test_sdot_v16i8:
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; CHECK: sdot {{v[0-9]+}}.4s, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
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%0 = bitcast i8* %a to <16 x i8>*
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%1 = load <16 x i8>, <16 x i8>* %0
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%2 = sext <16 x i8> %1 to <16 x i32>
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%3 = bitcast i8* %b to <16 x i8>*
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%4 = load <16 x i8>, <16 x i8>* %3
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%5 = sext <16 x i8> %4 to <16 x i32>
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%6 = mul nsw <16 x i32> %5, %2
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%7 = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %6)
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%op.extra = add nsw i32 %7, %sum
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ret i32 %op.extra
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}
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