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[WebAssembly] Initial SIMD128 support.
Kicks off the implementation of wasm SIMD128 support (spec: https://github.com/stoklund/portable-simd/blob/master/portable-simd.md), adding support for add, sub, mul for i8x16, i16x8, i32x4, and f32x4. The spec is WIP, and might change in the near future. Patch by João Porto Differential Revision: https://reviews.llvm.org/D22686 llvm-svn: 277543
This commit is contained in:
Derek Schuff
parent
f502af3ddc
commit
4c52f7daa5
@ -210,6 +210,11 @@ const char *llvm::WebAssembly::TypeToString(MVT Ty) {
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return "f32";
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case MVT::f64:
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return "f64";
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case MVT::v16i8:
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case MVT::v8i16:
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case MVT::v4i32:
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case MVT::v4f32:
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return "v128";
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default:
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llvm_unreachable("unsupported type");
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}
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@ -23,7 +23,7 @@ include "llvm/Target/Target.td"
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// WebAssembly Subtarget features.
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//===----------------------------------------------------------------------===//
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def FeatureSIMD128 : SubtargetFeature<"simd128", "HasSIMD128", "false",
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def FeatureSIMD128 : SubtargetFeature<"simd128", "HasSIMD128", "true",
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"Enable 128-bit SIMD">;
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//===----------------------------------------------------------------------===//
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@ -26,9 +26,10 @@
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///
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//===----------------------------------------------------------------------===//
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#include "WebAssembly.h"
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#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
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#include "WebAssembly.h"
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#include "WebAssemblyMachineFunctionInfo.h"
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#include "WebAssemblySubtarget.h"
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#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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@ -71,6 +72,10 @@ static bool IsArgument(const MachineInstr &MI) {
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case WebAssembly::ARGUMENT_I64:
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case WebAssembly::ARGUMENT_F32:
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case WebAssembly::ARGUMENT_F64:
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case WebAssembly::ARGUMENT_v16i8:
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case WebAssembly::ARGUMENT_v8i16:
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case WebAssembly::ARGUMENT_v4i32:
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case WebAssembly::ARGUMENT_v4f32:
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return true;
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default:
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return false;
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@ -95,7 +95,8 @@ private:
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MVT WebAssemblyAsmPrinter::getRegType(unsigned RegNo) const {
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const TargetRegisterClass *TRC = MRI->getRegClass(RegNo);
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for (MVT T : {MVT::i32, MVT::i64, MVT::f32, MVT::f64})
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for (MVT T : {MVT::i32, MVT::i64, MVT::f32, MVT::f64, MVT::v16i8, MVT::v8i16,
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MVT::v4i32, MVT::v4f32})
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if (TRC->hasType(T))
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return T;
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DEBUG(errs() << "Unknown type for register number: " << RegNo);
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@ -234,13 +235,21 @@ void WebAssemblyAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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case WebAssembly::ARGUMENT_I64:
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case WebAssembly::ARGUMENT_F32:
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case WebAssembly::ARGUMENT_F64:
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case WebAssembly::ARGUMENT_v16i8:
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case WebAssembly::ARGUMENT_v8i16:
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case WebAssembly::ARGUMENT_v4i32:
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case WebAssembly::ARGUMENT_v4f32:
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// These represent values which are live into the function entry, so there's
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// no instruction to emit.
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break;
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case WebAssembly::FALLTHROUGH_RETURN_I32:
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case WebAssembly::FALLTHROUGH_RETURN_I64:
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case WebAssembly::FALLTHROUGH_RETURN_F32:
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case WebAssembly::FALLTHROUGH_RETURN_F64: {
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case WebAssembly::FALLTHROUGH_RETURN_F64:
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case WebAssembly::FALLTHROUGH_RETURN_v16i8:
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case WebAssembly::FALLTHROUGH_RETURN_v8i16:
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case WebAssembly::FALLTHROUGH_RETURN_v4i32:
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case WebAssembly::FALLTHROUGH_RETURN_v4f32: {
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// These instructions represent the implicit return at the end of a
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// function body. The operand is always a pop.
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assert(MFI->isVRegStackified(MI->getOperand(0).getReg()));
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@ -113,6 +113,13 @@ private:
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case MVT::f32:
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case MVT::f64:
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return VT;
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case MVT::v16i8:
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case MVT::v8i16:
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case MVT::v4i32:
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case MVT::v4f32:
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if (Subtarget->hasSIMD128())
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return VT;
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break;
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default:
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break;
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}
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@ -575,7 +582,9 @@ bool WebAssemblyFastISel::fastLowerArguments() {
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return false;
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Type *ArgTy = Arg.getType();
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if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy())
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if (ArgTy->isStructTy() || ArgTy->isArrayTy())
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return false;
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if (!Subtarget->hasSIMD128() && ArgTy->isVectorTy())
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return false;
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unsigned Opc;
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@ -600,6 +609,22 @@ bool WebAssemblyFastISel::fastLowerArguments() {
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Opc = WebAssembly::ARGUMENT_F64;
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RC = &WebAssembly::F64RegClass;
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break;
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case MVT::v16i8:
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Opc = WebAssembly::ARGUMENT_v16i8;
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RC = &WebAssembly::V128RegClass;
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break;
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case MVT::v8i16:
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Opc = WebAssembly::ARGUMENT_v8i16;
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RC = &WebAssembly::V128RegClass;
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break;
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case MVT::v4i32:
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Opc = WebAssembly::ARGUMENT_v4i32;
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RC = &WebAssembly::V128RegClass;
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break;
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case MVT::v4f32:
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Opc = WebAssembly::ARGUMENT_v4f32;
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RC = &WebAssembly::V128RegClass;
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break;
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default:
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return false;
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}
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@ -639,6 +664,9 @@ bool WebAssemblyFastISel::selectCall(const Instruction *I) {
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if (IsVoid) {
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Opc = IsDirect ? WebAssembly::CALL_VOID : WebAssembly::CALL_INDIRECT_VOID;
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} else {
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if (!Subtarget->hasSIMD128() && Call->getType()->isVectorTy())
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return false;
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MVT::SimpleValueType RetTy = getSimpleType(Call->getType());
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switch (RetTy) {
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case MVT::i1:
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@ -660,6 +688,26 @@ bool WebAssemblyFastISel::selectCall(const Instruction *I) {
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Opc = IsDirect ? WebAssembly::CALL_F64 : WebAssembly::CALL_INDIRECT_F64;
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ResultReg = createResultReg(&WebAssembly::F64RegClass);
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break;
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case MVT::v16i8:
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Opc =
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IsDirect ? WebAssembly::CALL_v16i8 : WebAssembly::CALL_INDIRECT_v16i8;
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ResultReg = createResultReg(&WebAssembly::V128RegClass);
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break;
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case MVT::v8i16:
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Opc =
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IsDirect ? WebAssembly::CALL_v8i16 : WebAssembly::CALL_INDIRECT_v8i16;
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ResultReg = createResultReg(&WebAssembly::V128RegClass);
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break;
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case MVT::v4i32:
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Opc =
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IsDirect ? WebAssembly::CALL_v4i32 : WebAssembly::CALL_INDIRECT_v4i32;
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ResultReg = createResultReg(&WebAssembly::V128RegClass);
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break;
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case MVT::v4f32:
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Opc =
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IsDirect ? WebAssembly::CALL_v4f32 : WebAssembly::CALL_INDIRECT_v4f32;
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ResultReg = createResultReg(&WebAssembly::V128RegClass);
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break;
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default:
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return false;
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}
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@ -972,6 +1020,8 @@ bool WebAssemblyFastISel::selectLoad(const Instruction *I) {
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const LoadInst *Load = cast<LoadInst>(I);
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if (Load->isAtomic())
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return false;
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if (!Subtarget->hasSIMD128() && Load->getType()->isVectorTy())
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return false;
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Address Addr;
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if (!computeAddress(Load->getPointerOperand(), Addr))
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@ -1027,6 +1077,9 @@ bool WebAssemblyFastISel::selectStore(const Instruction *I) {
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const StoreInst *Store = cast<StoreInst>(I);
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if (Store->isAtomic())
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return false;
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if (!Subtarget->hasSIMD128() &&
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Store->getValueOperand()->getType()->isVectorTy())
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return false;
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Address Addr;
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if (!computeAddress(Store->getPointerOperand(), Addr))
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@ -1102,7 +1155,7 @@ bool WebAssemblyFastISel::selectBr(const Instruction *I) {
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
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.addMBB(TBB)
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.addReg(CondReg);
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finishCondBranch(Br->getParent(), TBB, FBB);
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return true;
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}
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@ -1120,6 +1173,9 @@ bool WebAssemblyFastISel::selectRet(const Instruction *I) {
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}
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Value *RV = Ret->getOperand(0);
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if (!Subtarget->hasSIMD128() && RV->getType()->isVectorTy())
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return false;
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unsigned Opc;
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switch (getSimpleType(RV->getType())) {
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case MVT::i1: case MVT::i8:
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@ -1129,8 +1185,24 @@ bool WebAssemblyFastISel::selectRet(const Instruction *I) {
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case MVT::i64:
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Opc = WebAssembly::RETURN_I64;
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break;
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case MVT::f32: Opc = WebAssembly::RETURN_F32; break;
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case MVT::f64: Opc = WebAssembly::RETURN_F64; break;
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case MVT::f32:
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Opc = WebAssembly::RETURN_F32;
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break;
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case MVT::f64:
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Opc = WebAssembly::RETURN_F64;
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break;
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case MVT::v16i8:
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Opc = WebAssembly::RETURN_v16i8;
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break;
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case MVT::v8i16:
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Opc = WebAssembly::RETURN_v8i16;
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break;
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case MVT::v4i32:
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Opc = WebAssembly::RETURN_v4i32;
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break;
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case MVT::v4f32:
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Opc = WebAssembly::RETURN_v4f32;
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break;
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default: return false;
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}
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@ -54,6 +54,12 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering(
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addRegisterClass(MVT::i64, &WebAssembly::I64RegClass);
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addRegisterClass(MVT::f32, &WebAssembly::F32RegClass);
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addRegisterClass(MVT::f64, &WebAssembly::F64RegClass);
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if (Subtarget->hasSIMD128()) {
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addRegisterClass(MVT::v16i8, &WebAssembly::V128RegClass);
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addRegisterClass(MVT::v8i16, &WebAssembly::V128RegClass);
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addRegisterClass(MVT::v4i32, &WebAssembly::V128RegClass);
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addRegisterClass(MVT::v4f32, &WebAssembly::V128RegClass);
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}
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// Compute derived properties from the register classes.
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computeRegisterProperties(Subtarget->getRegisterInfo());
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@ -190,6 +196,10 @@ WebAssemblyTargetLowering::getRegForInlineAsmConstraint(
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switch (Constraint[0]) {
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case 'r':
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assert(VT != MVT::iPTR && "Pointer MVT not expected here");
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if (Subtarget->hasSIMD128() && VT.isVector()) {
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if (VT.getSizeInBits() == 128)
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return std::make_pair(0U, &WebAssembly::V128RegClass);
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}
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if (VT.isInteger() && !VT.isVector()) {
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if (VT.getSizeInBits() <= 32)
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return std::make_pair(0U, &WebAssembly::I32RegClass);
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@ -33,11 +33,29 @@ multiclass CALL<WebAssemblyRegClass vt, string prefix> {
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[(set vt:$dst, (WebAssemblycall1 I32:$callee))],
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!strconcat(prefix, "call_indirect\t$dst, $callee")>;
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}
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multiclass SIMD_CALL<ValueType vt, string prefix> {
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def CALL_#vt : SIMD_I<(outs V128:$dst), (ins i32imm:$callee, variable_ops),
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[(set (vt V128:$dst),
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(WebAssemblycall1 (i32 imm:$callee)))],
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!strconcat(prefix, "call\t$dst, $callee")>;
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def CALL_INDIRECT_#vt : SIMD_I<(outs V128:$dst),
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(ins I32:$callee, variable_ops),
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[(set (vt V128:$dst),
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(WebAssemblycall1 I32:$callee))],
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!strconcat(prefix,
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"call_indirect\t$dst, $callee")>;
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}
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let Uses = [SP32, SP64], isCall = 1 in {
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defm : CALL<I32, "i32.">;
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defm : CALL<I64, "i64.">;
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defm : CALL<F32, "f32.">;
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defm : CALL<F64, "f64.">;
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defm : SIMD_CALL<v16i8, "i8x16.">;
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defm : SIMD_CALL<v8i16, "i16x8.">;
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defm : SIMD_CALL<v4i32, "i32x4.">;
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defm : SIMD_CALL<v4f32, "f32x4.">;
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def CALL_VOID : I<(outs), (ins i32imm:$callee, variable_ops),
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[(WebAssemblycall0 (i32 imm:$callee))],
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@ -58,6 +76,14 @@ def : Pat<(f32 (WebAssemblycall1 (WebAssemblywrapper tglobaladdr:$callee))),
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(CALL_F32 tglobaladdr:$callee)>;
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def : Pat<(f64 (WebAssemblycall1 (WebAssemblywrapper tglobaladdr:$callee))),
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(CALL_F64 tglobaladdr:$callee)>;
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def : Pat<(v16i8 (WebAssemblycall1 (WebAssemblywrapper tglobaladdr:$callee))),
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(CALL_v16i8 tglobaladdr:$callee)>, Requires<[HasSIMD128]>;
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def : Pat<(v8i16 (WebAssemblycall1 (WebAssemblywrapper tglobaladdr:$callee))),
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(CALL_v8i16 tglobaladdr:$callee)>, Requires<[HasSIMD128]>;
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def : Pat<(v4i32 (WebAssemblycall1 (WebAssemblywrapper tglobaladdr:$callee))),
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(CALL_v4i32 tglobaladdr:$callee)>, Requires<[HasSIMD128]>;
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def : Pat<(v4f32 (WebAssemblycall1 (WebAssemblywrapper tglobaladdr:$callee))),
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(CALL_v4f32 tglobaladdr:$callee)>, Requires<[HasSIMD128]>;
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def : Pat<(WebAssemblycall0 (WebAssemblywrapper tglobaladdr:$callee)),
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(CALL_VOID tglobaladdr:$callee)>;
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@ -70,5 +96,13 @@ def : Pat<(f32 (WebAssemblycall1 (WebAssemblywrapper texternalsym:$callee))),
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(CALL_F32 texternalsym:$callee)>;
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def : Pat<(f64 (WebAssemblycall1 (WebAssemblywrapper texternalsym:$callee))),
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(CALL_F64 texternalsym:$callee)>;
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def : Pat<(v16i8 (WebAssemblycall1 (WebAssemblywrapper texternalsym:$callee))),
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(CALL_v16i8 texternalsym:$callee)>, Requires<[HasSIMD128]>;
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def : Pat<(v8i16 (WebAssemblycall1 (WebAssemblywrapper texternalsym:$callee))),
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(CALL_v8i16 texternalsym:$callee)>, Requires<[HasSIMD128]>;
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def : Pat<(v4i32 (WebAssemblycall1 (WebAssemblywrapper texternalsym:$callee))),
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(CALL_v4i32 texternalsym:$callee)>, Requires<[HasSIMD128]>;
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def : Pat<(v4f32 (WebAssemblycall1 (WebAssemblywrapper texternalsym:$callee))),
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(CALL_v4f32 texternalsym:$callee)>, Requires<[HasSIMD128]>;
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def : Pat<(WebAssemblycall0 (WebAssemblywrapper texternalsym:$callee)),
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(CALL_VOID texternalsym:$callee)>;
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@ -77,12 +77,27 @@ multiclass RETURN<WebAssemblyRegClass vt> {
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def FALLTHROUGH_RETURN_#vt : I<(outs), (ins vt:$val), []>;
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}
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multiclass SIMD_RETURN<ValueType vt> {
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def RETURN_#vt : SIMD_I<(outs), (ins V128:$val),
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[(WebAssemblyreturn (vt V128:$val))],
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"return \t$val">;
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// Equivalent to RETURN_#vt, for use at the end of a function when wasm
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// semantics return by falling off the end of the block.
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let isCodeGenOnly = 1 in
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def FALLTHROUGH_RETURN_#vt : SIMD_I<(outs), (ins V128:$val), []>;
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}
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let isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 in {
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let isReturn = 1 in {
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defm : RETURN<I32>;
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defm : RETURN<I64>;
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defm : RETURN<F32>;
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defm : RETURN<F64>;
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defm : SIMD_RETURN<v16i8>;
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defm : SIMD_RETURN<v8i16>;
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defm : SIMD_RETURN<v4i32>;
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defm : SIMD_RETURN<v4f32>;
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def RETURN_VOID : I<(outs), (ins), [(WebAssemblyreturn)], "return">;
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// This is to RETURN_VOID what FALLTHROUGH_RETURN_#vt is to RETURN_#vt.
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@ -28,6 +28,9 @@ class I<dag oops, dag iops, list<dag> pattern, string asmstr = "">
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let Pattern = pattern;
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}
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class SIMD_I<dag oops, dag iops, list<dag> pattern, string asmstr = "">
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: I<oops, iops, pattern, asmstr>, Requires<[HasSIMD128]>;
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// Unary and binary instructions, for the local types that WebAssembly supports.
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multiclass UnaryInt<SDNode node, string name> {
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def _I32 : I<(outs I32:$dst), (ins I32:$src),
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@ -61,6 +64,21 @@ multiclass BinaryFP<SDNode node, string name> {
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[(set F64:$dst, (node F64:$lhs, F64:$rhs))],
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!strconcat("f64.", !strconcat(name, "\t$dst, $lhs, $rhs"))>;
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}
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multiclass SIMDBinary<SDNode node, SDNode fnode, string name> {
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def _I8x16 : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
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[(set (v16i8 V128:$dst), (node V128:$lhs, V128:$rhs))],
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!strconcat("i8x16.", !strconcat(name, "\t$dst, $lhs, $rhs"))>;
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def _I16x8 : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
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[(set (v8i16 V128:$dst), (node V128:$lhs, V128:$rhs))],
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!strconcat("i16x8.", !strconcat(name, "\t$dst, $lhs, $rhs"))>;
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def _I32x4 : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
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[(set (v4i32 V128:$dst), (node V128:$lhs, V128:$rhs))],
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!strconcat("i32x4.", !strconcat(name, "\t$dst, $lhs, $rhs"))>;
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def _F32x4 : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
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[(set (v4f32 V128:$dst), (fnode V128:$lhs, V128:$rhs))],
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!strconcat("f32x4.", !strconcat(name, "\t$dst, $lhs, $rhs"))>;
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}
|
||||
multiclass ComparisonInt<CondCode cond, string name> {
|
||||
def _I32 : I<(outs I32:$dst), (ins I32:$lhs, I32:$rhs),
|
||||
[(set I32:$dst, (setcc I32:$lhs, I32:$rhs, cond))],
|
||||
|
||||
@ -100,10 +100,20 @@ multiclass ARGUMENT<WebAssemblyRegClass vt> {
|
||||
def ARGUMENT_#vt : I<(outs vt:$res), (ins i32imm:$argno),
|
||||
[(set vt:$res, (WebAssemblyargument timm:$argno))]>;
|
||||
}
|
||||
multiclass SIMD_ARGUMENT<ValueType vt> {
|
||||
let hasSideEffects = 1, Uses = [ARGUMENTS], isCodeGenOnly = 1 in
|
||||
def ARGUMENT_#vt : SIMD_I<(outs V128:$res), (ins i32imm:$argno),
|
||||
[(set (vt V128:$res),
|
||||
(WebAssemblyargument timm:$argno))]>;
|
||||
}
|
||||
defm : ARGUMENT<I32>;
|
||||
defm : ARGUMENT<I64>;
|
||||
defm : ARGUMENT<F32>;
|
||||
defm : ARGUMENT<F64>;
|
||||
defm : SIMD_ARGUMENT<v16i8>;
|
||||
defm : SIMD_ARGUMENT<v8i16>;
|
||||
defm : SIMD_ARGUMENT<v4i32>;
|
||||
defm : SIMD_ARGUMENT<v4f32>;
|
||||
|
||||
let Defs = [ARGUMENTS] in {
|
||||
|
||||
@ -131,6 +141,7 @@ defm : LOCAL<I32>;
|
||||
defm : LOCAL<I64>;
|
||||
defm : LOCAL<F32>;
|
||||
defm : LOCAL<F64>;
|
||||
defm : LOCAL<V128>, Requires<[HasSIMD128]>;
|
||||
|
||||
let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1 in {
|
||||
def CONST_I32 : I<(outs I32:$res), (ins i32imm:$imm),
|
||||
|
||||
@ -12,5 +12,8 @@
|
||||
///
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// TODO: Implement SIMD instructions.
|
||||
// Note: use Requires<[HasSIMD128]>.
|
||||
let isCommutable = 1 in {
|
||||
defm ADD : SIMDBinary<add, fadd, "add ">;
|
||||
defm MUL: SIMDBinary<mul, fmul, "mul ">;
|
||||
} // isCommutable = 1
|
||||
defm SUB: SIMDBinary<sub, fsub, "sub ">;
|
||||
|
||||
@ -108,7 +108,8 @@ bool WebAssemblyPeephole::runOnMachineFunction(MachineFunction &MF) {
|
||||
|
||||
MachineRegisterInfo &MRI = MF.getRegInfo();
|
||||
WebAssemblyFunctionInfo &MFI = *MF.getInfo<WebAssemblyFunctionInfo>();
|
||||
const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
|
||||
const auto &Subtarget = MF.getSubtarget<WebAssemblySubtarget>();
|
||||
const auto &TII = *Subtarget.getInstrInfo();
|
||||
const WebAssemblyTargetLowering &TLI =
|
||||
*MF.getSubtarget<WebAssemblySubtarget>().getTargetLowering();
|
||||
auto &LibInfo = getAnalysis<TargetLibraryInfoWrapperPass>().getTLI();
|
||||
@ -186,6 +187,34 @@ bool WebAssemblyPeephole::runOnMachineFunction(MachineFunction &MF) {
|
||||
MI, MBB, MF, MFI, MRI, TII, WebAssembly::FALLTHROUGH_RETURN_F64,
|
||||
WebAssembly::COPY_LOCAL_F64);
|
||||
break;
|
||||
case WebAssembly::RETURN_v16i8:
|
||||
Changed |=
|
||||
Subtarget.hasSIMD128() &&
|
||||
MaybeRewriteToFallthrough(MI, MBB, MF, MFI, MRI, TII,
|
||||
WebAssembly::FALLTHROUGH_RETURN_v16i8,
|
||||
WebAssembly::COPY_LOCAL_V128);
|
||||
break;
|
||||
case WebAssembly::RETURN_v8i16:
|
||||
Changed |=
|
||||
Subtarget.hasSIMD128() &&
|
||||
MaybeRewriteToFallthrough(MI, MBB, MF, MFI, MRI, TII,
|
||||
WebAssembly::FALLTHROUGH_RETURN_v8i16,
|
||||
WebAssembly::COPY_LOCAL_V128);
|
||||
break;
|
||||
case WebAssembly::RETURN_v4i32:
|
||||
Changed |=
|
||||
Subtarget.hasSIMD128() &&
|
||||
MaybeRewriteToFallthrough(MI, MBB, MF, MFI, MRI, TII,
|
||||
WebAssembly::FALLTHROUGH_RETURN_v4i32,
|
||||
WebAssembly::COPY_LOCAL_V128);
|
||||
break;
|
||||
case WebAssembly::RETURN_v4f32:
|
||||
Changed |=
|
||||
Subtarget.hasSIMD128() &&
|
||||
MaybeRewriteToFallthrough(MI, MBB, MF, MFI, MRI, TII,
|
||||
WebAssembly::FALLTHROUGH_RETURN_v4f32,
|
||||
WebAssembly::COPY_LOCAL_V128);
|
||||
break;
|
||||
case WebAssembly::RETURN_VOID:
|
||||
if (!DisableWebAssemblyFallthroughReturnOpt &&
|
||||
&MBB == &MF.back() && &MI == &MBB.back())
|
||||
|
||||
@ -65,6 +65,10 @@ static bool IsArgument(const MachineInstr *MI) {
|
||||
case WebAssembly::ARGUMENT_I64:
|
||||
case WebAssembly::ARGUMENT_F32:
|
||||
case WebAssembly::ARGUMENT_F64:
|
||||
case WebAssembly::ARGUMENT_v16i8:
|
||||
case WebAssembly::ARGUMENT_v8i16:
|
||||
case WebAssembly::ARGUMENT_v4i32:
|
||||
case WebAssembly::ARGUMENT_v4f32:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
@ -73,7 +77,7 @@ static bool IsArgument(const MachineInstr *MI) {
|
||||
|
||||
// Test whether the given register has an ARGUMENT def.
|
||||
static bool HasArgumentDef(unsigned Reg, const MachineRegisterInfo &MRI) {
|
||||
for (auto &Def : MRI.def_instructions(Reg))
|
||||
for (const auto &Def : MRI.def_instructions(Reg))
|
||||
if (IsArgument(&Def))
|
||||
return true;
|
||||
return false;
|
||||
|
||||
@ -72,7 +72,11 @@ bool WebAssemblyRegNumbering::runOnMachineFunction(MachineFunction &MF) {
|
||||
case WebAssembly::ARGUMENT_I32:
|
||||
case WebAssembly::ARGUMENT_I64:
|
||||
case WebAssembly::ARGUMENT_F32:
|
||||
case WebAssembly::ARGUMENT_F64: {
|
||||
case WebAssembly::ARGUMENT_F64:
|
||||
case WebAssembly::ARGUMENT_v16i8:
|
||||
case WebAssembly::ARGUMENT_v8i16:
|
||||
case WebAssembly::ARGUMENT_v4i32:
|
||||
case WebAssembly::ARGUMENT_v4f32: {
|
||||
int64_t Imm = MI.getOperand(1).getImm();
|
||||
DEBUG(dbgs() << "Arg VReg " << MI.getOperand(0).getReg() << " -> WAReg "
|
||||
<< Imm << "\n");
|
||||
|
||||
@ -418,6 +418,8 @@ static unsigned GetTeeLocalOpcode(const TargetRegisterClass *RC) {
|
||||
return WebAssembly::TEE_LOCAL_F32;
|
||||
if (RC == &WebAssembly::F64RegClass)
|
||||
return WebAssembly::TEE_LOCAL_F64;
|
||||
if (RC == &WebAssembly::V128RegClass)
|
||||
return WebAssembly::TEE_LOCAL_V128;
|
||||
llvm_unreachable("Unexpected register class");
|
||||
}
|
||||
|
||||
@ -765,7 +767,11 @@ bool WebAssemblyRegStackify::runOnMachineFunction(MachineFunction &MF) {
|
||||
if (Def->getOpcode() == WebAssembly::ARGUMENT_I32 ||
|
||||
Def->getOpcode() == WebAssembly::ARGUMENT_I64 ||
|
||||
Def->getOpcode() == WebAssembly::ARGUMENT_F32 ||
|
||||
Def->getOpcode() == WebAssembly::ARGUMENT_F64)
|
||||
Def->getOpcode() == WebAssembly::ARGUMENT_F64 ||
|
||||
Def->getOpcode() == WebAssembly::ARGUMENT_v16i8 ||
|
||||
Def->getOpcode() == WebAssembly::ARGUMENT_v8i16 ||
|
||||
Def->getOpcode() == WebAssembly::ARGUMENT_v4i32 ||
|
||||
Def->getOpcode() == WebAssembly::ARGUMENT_v4f32)
|
||||
continue;
|
||||
|
||||
// Decide which strategy to take. Prefer to move a single-use value
|
||||
|
||||
@ -39,6 +39,8 @@ def SP64 : WebAssemblyReg<"%SP64">;
|
||||
def F32_0 : WebAssemblyReg<"%f32.0">;
|
||||
def F64_0 : WebAssemblyReg<"%f64.0">;
|
||||
|
||||
def V128_0: WebAssemblyReg<"%v128">;
|
||||
|
||||
// The expression stack "register". This is an opaque entity which serves to
|
||||
// order uses and defs that must remain in LIFO order.
|
||||
def EXPR_STACK : WebAssemblyReg<"STACK">;
|
||||
@ -56,3 +58,5 @@ def I32 : WebAssemblyRegClass<[i32], 32, (add FP32, SP32)>;
|
||||
def I64 : WebAssemblyRegClass<[i64], 64, (add FP64, SP64)>;
|
||||
def F32 : WebAssemblyRegClass<[f32], 32, (add F32_0)>;
|
||||
def F64 : WebAssemblyRegClass<[f64], 64, (add F64_0)>;
|
||||
def V128 : WebAssemblyRegClass<[v4f32, v4i32, v16i8, v8i16], 128, (add V128_0)>;
|
||||
|
||||
|
||||
158
test/CodeGen/WebAssembly/simd-arith.ll
Normal file
158
test/CodeGen/WebAssembly/simd-arith.ll
Normal file
@ -0,0 +1,158 @@
|
||||
; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
|
||||
; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128
|
||||
; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -mattr=-simd128 | FileCheck %s --check-prefixes CHECK,NO-SIMD128
|
||||
; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -mattr=-simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,NO-SIMD128
|
||||
|
||||
; Test that basic SIMD128 arithmetic operations assemble as expected.
|
||||
|
||||
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
|
||||
target triple = "wasm32-unknown-unknown"
|
||||
|
||||
declare i32 @llvm.ctlz.i32(i32, i1)
|
||||
declare i32 @llvm.cttz.i32(i32, i1)
|
||||
declare i32 @llvm.ctpop.i32(i32)
|
||||
|
||||
; ==============================================================================
|
||||
; 16 x i8
|
||||
; ==============================================================================
|
||||
; CHECK-LABEL: add_v16i8
|
||||
; NO-SIMD128-NOT: i8x16
|
||||
; SIMD128: .param v128, v128{{$}}
|
||||
; SIMD128: .result v128{{$}}
|
||||
; SIMD128: i8x16.add $push0=, $0, $1{{$}}
|
||||
; SIMD128: return $pop0{{$}}
|
||||
define <16 x i8> @add_v16i8(<16 x i8> %x, <16 x i8> %y) {
|
||||
%a = add <16 x i8> %x, %y
|
||||
ret <16 x i8> %a
|
||||
}
|
||||
|
||||
; CHECK-LABEL: sub_v16i8
|
||||
; NO-SIMD128-NOT: i8x16
|
||||
; SIMD128: .param v128, v128{{$}}
|
||||
; SIMD128: .result v128{{$}}
|
||||
; SIMD128: i8x16.sub $push0=, $0, $1{{$}}
|
||||
; SIMD128: return $pop0{{$}}
|
||||
define <16 x i8> @sub_v16i8(<16 x i8> %x, <16 x i8> %y) {
|
||||
%a = sub <16 x i8> %x, %y
|
||||
ret <16 x i8> %a
|
||||
}
|
||||
|
||||
; CHECK-LABEL: mul_v16i8
|
||||
; NO-SIMD128-NOT: i8x16
|
||||
; SIMD128: .param v128, v128{{$}}
|
||||
; SIMD128: .result v128{{$}}
|
||||
; SIMD128: i8x16.mul $push0=, $0, $1{{$}}
|
||||
; SIMD128: return $pop0{{$}}
|
||||
define <16 x i8> @mul_v16i8(<16 x i8> %x, <16 x i8> %y) {
|
||||
%a = mul <16 x i8> %x, %y
|
||||
ret <16 x i8> %a
|
||||
}
|
||||
|
||||
; ==============================================================================
|
||||
; 8 x i16
|
||||
; ==============================================================================
|
||||
; CHECK-LABEL: add_v8i16
|
||||
; NO-SIMD128-NOT: i16x8
|
||||
; SIMD128: .param v128, v128{{$}}
|
||||
; SIMD128: .result v128{{$}}
|
||||
; SIMD128: i16x8.add $push0=, $0, $1{{$}}
|
||||
; SIMD128: return $pop0{{$}}
|
||||
define <8 x i16> @add_v8i16(<8 x i16> %x, <8 x i16> %y) {
|
||||
%a = add <8 x i16> %x, %y
|
||||
ret <8 x i16> %a
|
||||
}
|
||||
|
||||
; CHECK-LABEL: sub_v8i16
|
||||
; NO-SIMD128-NOT: i16x8
|
||||
; SIMD128: .param v128, v128{{$}}
|
||||
; SIMD128: .result v128{{$}}
|
||||
; SIMD128: i16x8.sub $push0=, $0, $1{{$}}
|
||||
; SIMD128: return $pop0{{$}}
|
||||
define <8 x i16> @sub_v8i16(<8 x i16> %x, <8 x i16> %y) {
|
||||
%a = sub <8 x i16> %x, %y
|
||||
ret <8 x i16> %a
|
||||
}
|
||||
|
||||
; CHECK-LABEL: mul_v8i16
|
||||
; NO-SIMD128-NOT: i16x8
|
||||
; SIMD128: .param v128, v128{{$}}
|
||||
; SIMD128: .result v128{{$}}
|
||||
; SIMD128: i16x8.mul $push0=, $0, $1{{$}}
|
||||
; SIMD128: return $pop0{{$}}
|
||||
define <8 x i16> @mul_v8i16(<8 x i16> %x, <8 x i16> %y) {
|
||||
%a = mul <8 x i16> %x, %y
|
||||
ret <8 x i16> %a
|
||||
}
|
||||
|
||||
; ==============================================================================
|
||||
; 4 x i32
|
||||
; ==============================================================================
|
||||
; CHECK-LABEL: add_v4i32
|
||||
; NO-SIMD128-NOT: i32x4
|
||||
; SIMD128: .param v128, v128{{$}}
|
||||
; SIMD128: .result v128{{$}}
|
||||
; SIMD128: i32x4.add $push0=, $0, $1{{$}}
|
||||
; SIMD128: return $pop0{{$}}
|
||||
define <4 x i32> @add_v4i32(<4 x i32> %x, <4 x i32> %y) {
|
||||
%a = add <4 x i32> %x, %y
|
||||
ret <4 x i32> %a
|
||||
}
|
||||
|
||||
; CHECK-LABEL: sub_v4i32
|
||||
; NO-SIMD128-NOT: i32x4
|
||||
; SIMD128: .param v128, v128{{$}}
|
||||
; SIMD128: .result v128{{$}}
|
||||
; SIMD128: i32x4.sub $push0=, $0, $1{{$}}
|
||||
; SIMD128: return $pop0{{$}}
|
||||
define <4 x i32> @sub_v4i32(<4 x i32> %x, <4 x i32> %y) {
|
||||
%a = sub <4 x i32> %x, %y
|
||||
ret <4 x i32> %a
|
||||
}
|
||||
|
||||
; CHECK-LABEL: mul_v4i32
|
||||
; NO-SIMD128-NOT: i32x4
|
||||
; SIMD128: .param v128, v128{{$}}
|
||||
; SIMD128: .result v128{{$}}
|
||||
; SIMD128: i32x4.mul $push0=, $0, $1{{$}}
|
||||
; SIMD128: return $pop0{{$}}
|
||||
define <4 x i32> @mul_v4i32(<4 x i32> %x, <4 x i32> %y) {
|
||||
%a = mul <4 x i32> %x, %y
|
||||
ret <4 x i32> %a
|
||||
}
|
||||
|
||||
; ==============================================================================
|
||||
; 4 x float
|
||||
; ==============================================================================
|
||||
; CHECK-LABEL: add_v4f32
|
||||
; NO-SIMD128-NOT: f32x4
|
||||
; SIMD128: .param v128, v128{{$}}
|
||||
; SIMD128: .result v128{{$}}
|
||||
; SIMD128: f32x4.add $push0=, $0, $1{{$}}
|
||||
; SIMD128: return $pop0{{$}}
|
||||
define <4 x float> @add_v4f32(<4 x float> %x, <4 x float> %y) {
|
||||
%a = fadd <4 x float> %x, %y
|
||||
ret <4 x float> %a
|
||||
}
|
||||
|
||||
; CHECK-LABEL: sub_v4f32
|
||||
; NO-SIMD128-NOT: f32x4
|
||||
; SIMD128: .param v128, v128{{$}}
|
||||
; SIMD128: .result v128{{$}}
|
||||
; SIMD128: f32x4.sub $push0=, $0, $1{{$}}
|
||||
; SIMD128: return $pop0{{$}}
|
||||
define <4 x float> @sub_v4f32(<4 x float> %x, <4 x float> %y) {
|
||||
%a = fsub <4 x float> %x, %y
|
||||
ret <4 x float> %a
|
||||
}
|
||||
|
||||
; CHECK-LABEL: mul_v4f32
|
||||
; NO-SIMD128-NOT: f32x4
|
||||
; SIMD128: .param v128, v128{{$}}
|
||||
; SIMD128: .result v128{{$}}
|
||||
; SIMD128: f32x4.mul $push0=, $0, $1{{$}}
|
||||
; SIMD128: return $pop0{{$}}
|
||||
define <4 x float> @mul_v4f32(<4 x float> %x, <4 x float> %y) {
|
||||
%a = fmul <4 x float> %x, %y
|
||||
ret <4 x float> %a
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user