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Rename MachineInstrInfo::getDescriptor to MachineInstrInfo::get
llvm-svn: 4387
This commit is contained in:
Chris Lattner
parent
c3e30fed7b
commit
4cb6ebc9a1
@ -81,7 +81,6 @@ struct MachineInstrDescriptor {
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class MachineInstrInfo {
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private:
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const MachineInstrDescriptor* desc; // raw array to allow static init'n
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unsigned descSize; // number of entries in the desc array
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unsigned numRealOpCodes; // number of non-dummy op codes
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@ -96,25 +95,28 @@ public:
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unsigned getNumRealOpCodes() const { return numRealOpCodes; }
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unsigned getNumTotalOpCodes() const { return descSize; }
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const MachineInstrDescriptor& getDescriptor(MachineOpCode opCode) const {
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/// get - Return the machine instruction descriptor that corresponds to the
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/// specified instruction opcode.
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///
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const MachineInstrDescriptor& get(MachineOpCode opCode) const {
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assert(opCode >= 0 && opCode < (int)descSize);
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return desc[opCode];
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}
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int getNumOperands(MachineOpCode opCode) const {
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return getDescriptor(opCode).numOperands;
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return get(opCode).numOperands;
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}
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int getResultPos(MachineOpCode opCode) const {
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return getDescriptor(opCode).resultPos;
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return get(opCode).resultPos;
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}
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unsigned getNumDelaySlots(MachineOpCode opCode) const {
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return getDescriptor(opCode).numDelaySlots;
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return get(opCode).numDelaySlots;
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}
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InstrSchedClass getSchedClass(MachineOpCode opCode) const {
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return getDescriptor(opCode).schedClass;
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return get(opCode).schedClass;
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}
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//
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@ -122,66 +124,66 @@ public:
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// flags listed above.
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//
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unsigned getIClass(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass;
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return get(opCode).iclass;
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}
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bool isNop(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_NOP_FLAG;
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return get(opCode).iclass & M_NOP_FLAG;
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}
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bool isBranch(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_BRANCH_FLAG;
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return get(opCode).iclass & M_BRANCH_FLAG;
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}
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bool isCall(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_CALL_FLAG;
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return get(opCode).iclass & M_CALL_FLAG;
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}
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bool isReturn(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_RET_FLAG;
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return get(opCode).iclass & M_RET_FLAG;
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}
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bool isControlFlow(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_BRANCH_FLAG
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|| getDescriptor(opCode).iclass & M_CALL_FLAG
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|| getDescriptor(opCode).iclass & M_RET_FLAG;
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return get(opCode).iclass & M_BRANCH_FLAG
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|| get(opCode).iclass & M_CALL_FLAG
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|| get(opCode).iclass & M_RET_FLAG;
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}
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bool isArith(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_ARITH_FLAG;
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return get(opCode).iclass & M_ARITH_FLAG;
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}
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bool isCCInstr(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_CC_FLAG;
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return get(opCode).iclass & M_CC_FLAG;
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}
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bool isLogical(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_LOGICAL_FLAG;
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return get(opCode).iclass & M_LOGICAL_FLAG;
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}
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bool isIntInstr(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_INT_FLAG;
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return get(opCode).iclass & M_INT_FLAG;
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}
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bool isFloatInstr(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_FLOAT_FLAG;
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return get(opCode).iclass & M_FLOAT_FLAG;
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}
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bool isConditional(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_CONDL_FLAG;
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return get(opCode).iclass & M_CONDL_FLAG;
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}
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bool isLoad(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_LOAD_FLAG;
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return get(opCode).iclass & M_LOAD_FLAG;
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}
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bool isPrefetch(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_PREFETCH_FLAG;
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return get(opCode).iclass & M_PREFETCH_FLAG;
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}
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bool isLoadOrPrefetch(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_LOAD_FLAG
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|| getDescriptor(opCode).iclass & M_PREFETCH_FLAG;
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return get(opCode).iclass & M_LOAD_FLAG
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|| get(opCode).iclass & M_PREFETCH_FLAG;
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}
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bool isStore(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_STORE_FLAG;
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return get(opCode).iclass & M_STORE_FLAG;
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}
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bool isMemoryAccess(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_LOAD_FLAG
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|| getDescriptor(opCode).iclass & M_PREFETCH_FLAG
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|| getDescriptor(opCode).iclass & M_STORE_FLAG;
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return get(opCode).iclass & M_LOAD_FLAG
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|| get(opCode).iclass & M_PREFETCH_FLAG
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|| get(opCode).iclass & M_STORE_FLAG;
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}
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bool isDummyPhiInstr(const MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_DUMMY_PHI_FLAG;
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return get(opCode).iclass & M_DUMMY_PHI_FLAG;
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}
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bool isPseudoInstr(const MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_PSEUDO_FLAG;
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return get(opCode).iclass & M_PSEUDO_FLAG;
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}
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// Check if an instruction can be issued before its operands are ready,
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@ -201,11 +203,11 @@ public:
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// Latencies for individual instructions and instruction pairs
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//
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virtual int minLatency(MachineOpCode opCode) const {
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return getDescriptor(opCode).latency;
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return get(opCode).latency;
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}
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virtual int maxLatency(MachineOpCode opCode) const {
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return getDescriptor(opCode).latency;
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return get(opCode).latency;
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}
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//
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@ -229,8 +231,8 @@ public:
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//
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virtual uint64_t maxImmedConstant(MachineOpCode opCode,
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bool &isSignExtended) const {
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isSignExtended = getDescriptor(opCode).immedIsSignExtended;
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return getDescriptor(opCode).maxImmedConst;
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isSignExtended = get(opCode).immedIsSignExtended;
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return get(opCode).maxImmedConst;
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}
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//-------------------------------------------------------------------------
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@ -81,7 +81,6 @@ struct MachineInstrDescriptor {
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class MachineInstrInfo {
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private:
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const MachineInstrDescriptor* desc; // raw array to allow static init'n
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unsigned descSize; // number of entries in the desc array
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unsigned numRealOpCodes; // number of non-dummy op codes
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@ -96,25 +95,28 @@ public:
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unsigned getNumRealOpCodes() const { return numRealOpCodes; }
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unsigned getNumTotalOpCodes() const { return descSize; }
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const MachineInstrDescriptor& getDescriptor(MachineOpCode opCode) const {
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/// get - Return the machine instruction descriptor that corresponds to the
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/// specified instruction opcode.
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///
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const MachineInstrDescriptor& get(MachineOpCode opCode) const {
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assert(opCode >= 0 && opCode < (int)descSize);
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return desc[opCode];
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}
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int getNumOperands(MachineOpCode opCode) const {
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return getDescriptor(opCode).numOperands;
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return get(opCode).numOperands;
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}
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int getResultPos(MachineOpCode opCode) const {
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return getDescriptor(opCode).resultPos;
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return get(opCode).resultPos;
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}
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unsigned getNumDelaySlots(MachineOpCode opCode) const {
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return getDescriptor(opCode).numDelaySlots;
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return get(opCode).numDelaySlots;
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}
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InstrSchedClass getSchedClass(MachineOpCode opCode) const {
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return getDescriptor(opCode).schedClass;
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return get(opCode).schedClass;
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}
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//
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@ -122,66 +124,66 @@ public:
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// flags listed above.
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//
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unsigned getIClass(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass;
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return get(opCode).iclass;
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}
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bool isNop(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_NOP_FLAG;
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return get(opCode).iclass & M_NOP_FLAG;
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}
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bool isBranch(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_BRANCH_FLAG;
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return get(opCode).iclass & M_BRANCH_FLAG;
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}
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bool isCall(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_CALL_FLAG;
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return get(opCode).iclass & M_CALL_FLAG;
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}
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bool isReturn(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_RET_FLAG;
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return get(opCode).iclass & M_RET_FLAG;
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}
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bool isControlFlow(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_BRANCH_FLAG
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|| getDescriptor(opCode).iclass & M_CALL_FLAG
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|| getDescriptor(opCode).iclass & M_RET_FLAG;
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return get(opCode).iclass & M_BRANCH_FLAG
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|| get(opCode).iclass & M_CALL_FLAG
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|| get(opCode).iclass & M_RET_FLAG;
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}
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bool isArith(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_ARITH_FLAG;
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return get(opCode).iclass & M_ARITH_FLAG;
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}
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bool isCCInstr(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_CC_FLAG;
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return get(opCode).iclass & M_CC_FLAG;
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}
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bool isLogical(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_LOGICAL_FLAG;
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return get(opCode).iclass & M_LOGICAL_FLAG;
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}
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bool isIntInstr(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_INT_FLAG;
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return get(opCode).iclass & M_INT_FLAG;
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}
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bool isFloatInstr(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_FLOAT_FLAG;
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return get(opCode).iclass & M_FLOAT_FLAG;
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}
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bool isConditional(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_CONDL_FLAG;
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return get(opCode).iclass & M_CONDL_FLAG;
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}
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bool isLoad(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_LOAD_FLAG;
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return get(opCode).iclass & M_LOAD_FLAG;
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}
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bool isPrefetch(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_PREFETCH_FLAG;
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return get(opCode).iclass & M_PREFETCH_FLAG;
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}
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bool isLoadOrPrefetch(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_LOAD_FLAG
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|| getDescriptor(opCode).iclass & M_PREFETCH_FLAG;
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return get(opCode).iclass & M_LOAD_FLAG
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|| get(opCode).iclass & M_PREFETCH_FLAG;
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}
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bool isStore(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_STORE_FLAG;
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return get(opCode).iclass & M_STORE_FLAG;
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}
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bool isMemoryAccess(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_LOAD_FLAG
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|| getDescriptor(opCode).iclass & M_PREFETCH_FLAG
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|| getDescriptor(opCode).iclass & M_STORE_FLAG;
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return get(opCode).iclass & M_LOAD_FLAG
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|| get(opCode).iclass & M_PREFETCH_FLAG
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|| get(opCode).iclass & M_STORE_FLAG;
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}
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bool isDummyPhiInstr(const MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_DUMMY_PHI_FLAG;
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return get(opCode).iclass & M_DUMMY_PHI_FLAG;
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}
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bool isPseudoInstr(const MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_PSEUDO_FLAG;
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return get(opCode).iclass & M_PSEUDO_FLAG;
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}
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// Check if an instruction can be issued before its operands are ready,
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@ -201,11 +203,11 @@ public:
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// Latencies for individual instructions and instruction pairs
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//
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virtual int minLatency(MachineOpCode opCode) const {
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return getDescriptor(opCode).latency;
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return get(opCode).latency;
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}
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virtual int maxLatency(MachineOpCode opCode) const {
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return getDescriptor(opCode).latency;
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return get(opCode).latency;
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}
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//
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@ -229,8 +231,8 @@ public:
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//
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virtual uint64_t maxImmedConstant(MachineOpCode opCode,
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bool &isSignExtended) const {
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isSignExtended = getDescriptor(opCode).immedIsSignExtended;
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return getDescriptor(opCode).maxImmedConst;
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isSignExtended = get(opCode).immedIsSignExtended;
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return get(opCode).maxImmedConst;
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}
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//-------------------------------------------------------------------------
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