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[PowerPC] fold addi's imm operand to its imm form consumer's displacement
This patch adds a function to do following transformation: %0:g8rc_and_g8rc_nox0 = ADDI8 %5:g8rc_and_g8rc_nox0, 144 STD killed %7:g8rc, 16, %0:g8rc_and_g8rc_nox0 :: (store 8 into %ir.8) ------> STD killed %7:g8rc, 160, %5:g8rc_and_g8rc_nox0 :: (store 8 into %ir.8) Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D81723
This commit is contained in:
Chen Zheng
parent
be0a92b108
commit
4cc65c325c
@ -2563,7 +2563,8 @@ MachineInstr *PPCInstrInfo::getForwardingDefMI(
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MachineRegisterInfo *MRI = &MI.getParent()->getParent()->getRegInfo();
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const TargetRegisterInfo *TRI = &getRegisterInfo();
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// If we're in SSA, get the defs through the MRI. Otherwise, only look
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// within the basic block to see if the register is defined using an LI/LI8.
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// within the basic block to see if the register is defined using an
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// LI/LI8/ADDI/ADDI8.
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if (MRI->isSSA()) {
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for (int i = 1, e = MI.getNumOperands(); i < e; i++) {
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if (!MI.getOperand(i).isReg())
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@ -2574,9 +2575,16 @@ MachineInstr *PPCInstrInfo::getForwardingDefMI(
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unsigned TrueReg = TRI->lookThruCopyLike(Reg, MRI);
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if (Register::isVirtualRegister(TrueReg)) {
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DefMI = MRI->getVRegDef(TrueReg);
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if (DefMI->getOpcode() == PPC::LI || DefMI->getOpcode() == PPC::LI8) {
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if (DefMI->getOpcode() == PPC::LI || DefMI->getOpcode() == PPC::LI8 ||
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DefMI->getOpcode() == PPC::ADDI ||
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DefMI->getOpcode() == PPC::ADDI8) {
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OpNoForForwarding = i;
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break;
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// The ADDI and LI operand maybe exist in one instruction at same
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// time. we prefer to fold LI operand as LI only has one Imm operand
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// and is more possible to be converted. So if current DefMI is
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// ADDI/ADDI8, we continue to find possible LI/LI8.
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if (DefMI->getOpcode() == PPC::LI || DefMI->getOpcode() == PPC::LI8)
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break;
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}
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}
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}
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@ -2647,10 +2655,6 @@ const unsigned *PPCInstrInfo::getLoadOpcodesForSpillArray() const {
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void PPCInstrInfo::fixupIsDeadOrKill(MachineInstr &StartMI, MachineInstr &EndMI,
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unsigned RegNo) const {
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const MachineRegisterInfo &MRI =
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StartMI.getParent()->getParent()->getRegInfo();
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if (MRI.isSSA())
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return;
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// Instructions between [StartMI, EndMI] should be in same basic block.
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assert((StartMI.getParent() == EndMI.getParent()) &&
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@ -2973,6 +2977,13 @@ bool PPCInstrInfo::convertToImmediateForm(MachineInstr &MI,
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if (KilledDef && KillFwdDefMI)
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*KilledDef = DefMI;
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// If this is a imm instruction and its register operands is produced by ADDI,
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// put the imm into imm inst directly.
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if (RI.getMappedIdxOpcForImmOpc(MI.getOpcode()) !=
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PPC::INSTRUCTION_LIST_END &&
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transformToNewImmFormFedByAdd(MI, *DefMI, ForwardingOperand))
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return true;
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ImmInstrInfo III;
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bool IsVFReg = MI.getOperand(0).isReg()
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? isVFRegister(MI.getOperand(0).getReg())
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@ -3513,6 +3524,10 @@ bool PPCInstrInfo::isDefMIElgibleForForwarding(MachineInstr &DefMI,
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RegMO = &DefMI.getOperand(1);
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ImmMO = &DefMI.getOperand(2);
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// Before RA, ADDI first operand could be a frame index.
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if (!RegMO->isReg())
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return false;
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// This DefMI is elgible for forwarding if it is:
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// 1. add inst
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// 2. one of the operands is Imm/CPI/Global.
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@ -3561,7 +3576,8 @@ bool PPCInstrInfo::isRegElgibleForForwarding(
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bool PPCInstrInfo::isImmElgibleForForwarding(const MachineOperand &ImmMO,
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const MachineInstr &DefMI,
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const ImmInstrInfo &III,
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int64_t &Imm) const {
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int64_t &Imm,
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int64_t BaseImm) const {
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assert(isAnImmediateOperand(ImmMO) && "ImmMO is NOT an immediate");
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if (DefMI.getOpcode() == PPC::ADDItocL) {
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// The operand for ADDItocL is CPI, which isn't imm at compiling time,
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@ -3584,10 +3600,10 @@ bool PPCInstrInfo::isImmElgibleForForwarding(const MachineOperand &ImmMO,
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if (ImmMO.isImm()) {
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// It is Imm, we need to check if the Imm fit the range.
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int64_t Immediate = ImmMO.getImm();
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// Sign-extend to 64-bits.
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Imm = ((uint64_t)Immediate & ~0x7FFFuLL) != 0 ?
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(Immediate | 0xFFFFFFFFFFFF0000) : Immediate;
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// DefMI may be folded with another imm form instruction, the result Imm is
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// the sum of Imm of DefMI and BaseImm which is from imm form instruction.
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Imm = SignExtend64<16>(ImmMO.getImm() + BaseImm);
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if (Imm % III.ImmMustBeMultipleOf)
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return false;
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@ -3840,6 +3856,99 @@ bool PPCInstrInfo::simplifyToLI(MachineInstr &MI, MachineInstr &DefMI,
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return false;
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}
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bool PPCInstrInfo::transformToNewImmFormFedByAdd(
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MachineInstr &MI, MachineInstr &DefMI, unsigned OpNoForForwarding) const {
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MachineRegisterInfo *MRI = &MI.getParent()->getParent()->getRegInfo();
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bool PostRA = !MRI->isSSA();
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// FIXME: extend this to post-ra. Need to do some change in getForwardingDefMI
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// for post-ra.
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if (PostRA)
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return false;
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// Only handle load/store.
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if (!MI.mayLoadOrStore())
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return false;
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unsigned XFormOpcode = RI.getMappedIdxOpcForImmOpc(MI.getOpcode());
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assert((XFormOpcode != PPC::INSTRUCTION_LIST_END) &&
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"MI must have x-form opcode");
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// get Imm Form info.
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ImmInstrInfo III;
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bool IsVFReg = MI.getOperand(0).isReg()
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? isVFRegister(MI.getOperand(0).getReg())
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: false;
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if (!instrHasImmForm(XFormOpcode, IsVFReg, III, PostRA))
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return false;
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if (!III.IsSummingOperands)
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return false;
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if (OpNoForForwarding != III.OpNoForForwarding)
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return false;
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MachineOperand ImmOperandMI = MI.getOperand(III.ImmOpNo);
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if (!ImmOperandMI.isImm())
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return false;
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// Check DefMI.
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MachineOperand *ImmMO = nullptr;
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MachineOperand *RegMO = nullptr;
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if (!isDefMIElgibleForForwarding(DefMI, III, ImmMO, RegMO))
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return false;
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assert(ImmMO && RegMO && "Imm and Reg operand must have been set");
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// Check Imm.
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// Set ImmBase from imm instruction as base and get new Imm inside
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// isImmElgibleForForwarding.
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int64_t ImmBase = ImmOperandMI.getImm();
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int64_t Imm = 0;
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if (!isImmElgibleForForwarding(*ImmMO, DefMI, III, Imm, ImmBase))
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return false;
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// Get killed info in case fixup needed after transformation.
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unsigned ForwardKilledOperandReg = ~0U;
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if (MI.getOperand(III.OpNoForForwarding).isKill())
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ForwardKilledOperandReg = MI.getOperand(III.OpNoForForwarding).getReg();
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// Do the transform
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LLVM_DEBUG(dbgs() << "Replacing instruction:\n");
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LLVM_DEBUG(MI.dump());
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LLVM_DEBUG(dbgs() << "Fed by:\n");
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LLVM_DEBUG(DefMI.dump());
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MI.getOperand(III.OpNoForForwarding).setReg(RegMO->getReg());
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MI.getOperand(III.OpNoForForwarding).setIsKill(RegMO->isKill());
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MI.getOperand(III.ImmOpNo).setImm(Imm);
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// FIXME: fix kill/dead flag if MI and DefMI are not in same basic block.
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if (DefMI.getParent() == MI.getParent()) {
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// Check if reg is killed between MI and DefMI.
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auto IsKilledFor = [&](unsigned Reg) {
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MachineBasicBlock::const_reverse_iterator It = MI;
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MachineBasicBlock::const_reverse_iterator E = DefMI;
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It++;
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for (; It != E; ++It) {
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if (It->killsRegister(Reg))
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return true;
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}
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return false;
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};
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// Update kill flag
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if (RegMO->isKill() || IsKilledFor(RegMO->getReg()))
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fixupIsDeadOrKill(DefMI, MI, RegMO->getReg());
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if (ForwardKilledOperandReg != ~0U)
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fixupIsDeadOrKill(DefMI, MI, ForwardKilledOperandReg);
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}
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LLVM_DEBUG(dbgs() << "With:\n");
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LLVM_DEBUG(MI.dump());
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return true;
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}
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// If an X-Form instruction is fed by an add-immediate and one of its operands
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// is the literal zero, attempt to forward the source of the add-immediate to
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// the corresponding D-Form instruction with the displacement coming from
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@ -191,6 +191,10 @@ class PPCInstrInfo : public PPCGenInstrInfo {
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// LI8.
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bool simplifyToLI(MachineInstr &MI, MachineInstr &DefMI,
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unsigned OpNoForForwarding, MachineInstr **KilledDef) const;
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// If the inst is imm-form and its register operand is produced by a ADDI, put
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// the imm into the inst directly and remove the ADDI if possible.
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bool transformToNewImmFormFedByAdd(MachineInstr &MI, MachineInstr &DefMI,
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unsigned OpNoForForwarding) const;
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// If the inst is x-form and has imm-form and one of its operand is produced
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// by a LI, put the imm into the inst directly and remove the LI if possible.
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bool transformToImmFormFedByLI(MachineInstr &MI, const ImmInstrInfo &III,
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@ -221,7 +225,8 @@ class PPCInstrInfo : public PPCGenInstrInfo {
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bool isImmElgibleForForwarding(const MachineOperand &ImmMO,
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const MachineInstr &DefMI,
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const ImmInstrInfo &III,
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int64_t &Imm) const;
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int64_t &Imm,
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int64_t BaseImm = 0) const;
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bool isRegElgibleForForwarding(const MachineOperand &RegMO,
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const MachineInstr &DefMI,
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const MachineInstr &MI, bool KillDefMI,
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67
test/CodeGen/PowerPC/convert-ri-addi-to-ri.mir
Normal file
67
test/CodeGen/PowerPC/convert-ri-addi-to-ri.mir
Normal file
@ -0,0 +1,67 @@
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# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs \
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# RUN: -run-pass ppc-mi-peepholes -ppc-convert-rr-to-ri %s -o - | FileCheck %s
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---
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name: foldNewDformStore
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# CHECK: name: foldNewDformStore
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x3
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%0:g8rc_and_g8rc_nox0 = COPY $x3
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%1:g8rc_and_g8rc_nox0 = ADDI8 %0:g8rc_and_g8rc_nox0, 144
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%2:g8rc = LI8 0
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; CHECK: STD killed %2, 160, %0
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STD killed %2:g8rc, 16, %1:g8rc_and_g8rc_nox0
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BLR8 implicit $lr8, implicit $rm
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...
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---
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name: foldNewDformStoreAlignNotMatch
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# CHECK: name: foldNewDformStoreAlignNotMatch
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x3
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%0:g8rc_and_g8rc_nox0 = COPY $x3
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%1:g8rc_and_g8rc_nox0 = ADDI8 %0:g8rc_and_g8rc_nox0, 141
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%2:g8rc = LI8 0
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; CHECK: STD killed %2, 16, %1
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STD killed %2:g8rc, 16, %1:g8rc_and_g8rc_nox0
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BLR8 implicit $lr8, implicit $rm
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...
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---
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name: foldNewDformStoreKilledFlag
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# CHECK: name: foldNewDformStoreKilledFlag
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x3
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%0:g8rc_and_g8rc_nox0 = COPY $x3
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%1:g8rc_and_g8rc_nox0 = ADDI8 %0:g8rc_and_g8rc_nox0, 144
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%2:g8rc = LI8 0
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; CHECK: STD %1, 0, %0
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STD %1:g8rc_and_g8rc_nox0, 0, killed %0:g8rc_and_g8rc_nox0
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; CHECK: STD killed %2, 160, killed %0
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STD killed %2:g8rc, 16, %1:g8rc_and_g8rc_nox0
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BLR8 implicit $lr8, implicit $rm
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...
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---
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name: foldNewDformPreferLIOperand
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# CHECK: name: foldNewDformPreferLIOperand
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x3
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%0:g8rc_and_g8rc_nox0 = COPY $x3
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%1:g8rc = ADDI8 %0:g8rc_and_g8rc_nox0, 1
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%2:g8rc = LI8 1
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; CHECK: SUBFIC8 killed %1, 1, implicit-def $carry
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%3:g8rc = SUBFC8 killed %1:g8rc, %2:g8rc, implicit-def $carry
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%4:g8rc = SUBFE8 %2:g8rc, %2:g8rc, implicit-def dead $carry, implicit $carry
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%5:g8rc = NEG8 killed %4:g8rc
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$x3 = COPY %5:g8rc
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BLR8 implicit $lr8, implicit $rm, implicit $x3
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...
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