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Revert r358800. Breaks Obsequi from the test suite.
The last attempt fixed gcc and consumer-typeset, but Obsequi seems to fail with a different issue. llvm-svn: 358829
This commit is contained in:
Amara Emerson
parent
1ab2f5937d
commit
4cebcd0399
@ -639,10 +639,6 @@ public:
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return actionIf(LegalizeAction::Unsupported,
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LegalityPredicates::memSizeInBytesNotPow2(0));
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}
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LegalizeRuleSet &lowerIfMemSizeNotPow2() {
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return actionIf(LegalizeAction::Lower,
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LegalityPredicates::memSizeInBytesNotPow2(0));
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}
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LegalizeRuleSet &customIf(LegalityPredicate Predicate) {
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// We have no choice but conservatively assume that a custom action with a
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@ -1483,57 +1483,11 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
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LLT DstTy = MRI.getType(DstReg);
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auto &MMO = **MI.memoperands_begin();
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if (DstTy.getSizeInBits() == MMO.getSizeInBits()) {
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if (MI.getOpcode() == TargetOpcode::G_LOAD) {
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// This load needs splitting into power of 2 sized loads.
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if (DstTy.isVector())
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if (DstTy.getSizeInBits() == MMO.getSize() /* in bytes */ * 8) {
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// In the case of G_LOAD, this was a non-extending load already and we're
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// about to lower to the same instruction.
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if (MI.getOpcode() == TargetOpcode::G_LOAD)
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return UnableToLegalize;
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if (isPowerOf2_32(DstTy.getSizeInBits()))
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return UnableToLegalize; // Don't know what we're being asked to do.
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// Our strategy here is to generate anyextending loads for the smaller
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// types up to next power-2 result type, and then combine the two larger
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// result values together, before truncating back down to the non-pow-2
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// type.
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// E.g. v1 = i24 load =>
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// v2 = i32 load (2 byte)
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// v3 = i32 load (1 byte)
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// v4 = i32 shl v3, 16
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// v5 = i32 or v4, v2
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// v1 = i24 trunc v5
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// By doing this we generate the correct truncate which should get
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// combined away as an artifact with a matching extend.
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uint64_t LargeSplitSize = PowerOf2Floor(DstTy.getSizeInBits());
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uint64_t SmallSplitSize = DstTy.getSizeInBits() - LargeSplitSize;
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MachineFunction &MF = MIRBuilder.getMF();
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MachineMemOperand *LargeMMO =
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MF.getMachineMemOperand(&MMO, 0, LargeSplitSize / 8);
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MachineMemOperand *SmallMMO = MF.getMachineMemOperand(
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&MMO, LargeSplitSize / 8, SmallSplitSize / 8);
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LLT PtrTy = MRI.getType(PtrReg);
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unsigned AnyExtSize = NextPowerOf2(DstTy.getSizeInBits());
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LLT AnyExtTy = LLT::scalar(AnyExtSize);
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unsigned LargeLdReg = MRI.createGenericVirtualRegister(AnyExtTy);
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unsigned SmallLdReg = MRI.createGenericVirtualRegister(AnyExtTy);
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auto LargeLoad =
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MIRBuilder.buildLoad(LargeLdReg, PtrReg, *LargeMMO);
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auto OffsetCst =
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MIRBuilder.buildConstant(LLT::scalar(64), LargeSplitSize / 8);
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unsigned GEPReg = MRI.createGenericVirtualRegister(PtrTy);
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auto SmallPtr = MIRBuilder.buildGEP(GEPReg, PtrReg, OffsetCst.getReg(0));
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auto SmallLoad = MIRBuilder.buildLoad(SmallLdReg, SmallPtr.getReg(0),
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*SmallMMO);
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auto ShiftAmt = MIRBuilder.buildConstant(AnyExtTy, LargeSplitSize);
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auto Shift = MIRBuilder.buildShl(AnyExtTy, SmallLoad, ShiftAmt);
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auto Or = MIRBuilder.buildOr(AnyExtTy, Shift, LargeLoad);
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MIRBuilder.buildTrunc(DstReg, {Or.getReg(0)});
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MI.eraseFromParent();
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return Legalized;
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}
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MIRBuilder.buildLoad(DstReg, PtrReg, MMO);
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MI.eraseFromParent();
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return Legalized;
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@ -1562,51 +1516,6 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
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return UnableToLegalize;
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}
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case TargetOpcode::G_STORE: {
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// Lower a non-power of 2 store into multiple pow-2 stores.
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// E.g. split an i24 store into an i16 store + i8 store.
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// We do this by first extending the stored value to the next largest power
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// of 2 type, and then using truncating stores to store the components.
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// By doing this, likewise with G_LOAD, generate an extend that can be
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// artifact-combined away instead of leaving behind extracts.
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unsigned SrcReg = MI.getOperand(0).getReg();
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unsigned PtrReg = MI.getOperand(1).getReg();
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LLT SrcTy = MRI.getType(SrcReg);
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MachineMemOperand &MMO = **MI.memoperands_begin();
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if (SrcTy.getSizeInBits() != MMO.getSizeInBits())
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return UnableToLegalize;
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if (SrcTy.isVector())
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return UnableToLegalize;
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if (isPowerOf2_32(SrcTy.getSizeInBits()))
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return UnableToLegalize; // Don't know what we're being asked to do.
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// Extend to the next pow-2.
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const LLT ExtendTy = LLT::scalar(NextPowerOf2(SrcTy.getSizeInBits()));
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auto ExtVal = MIRBuilder.buildAnyExt(ExtendTy, SrcReg);
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// Obtain the smaller value by shifting away the larger value.
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uint64_t LargeSplitSize = PowerOf2Floor(SrcTy.getSizeInBits());
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uint64_t SmallSplitSize = SrcTy.getSizeInBits() - LargeSplitSize;
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auto ShiftAmt = MIRBuilder.buildConstant(ExtendTy, LargeSplitSize);
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auto SmallVal = MIRBuilder.buildLShr(ExtendTy, ExtVal, ShiftAmt);
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// Generate the GEP and truncating stores.
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LLT PtrTy = MRI.getType(PtrReg);
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auto OffsetCst =
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MIRBuilder.buildConstant(LLT::scalar(64), LargeSplitSize / 8);
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unsigned GEPReg = MRI.createGenericVirtualRegister(PtrTy);
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auto SmallPtr = MIRBuilder.buildGEP(GEPReg, PtrReg, OffsetCst.getReg(0));
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MachineFunction &MF = MIRBuilder.getMF();
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MachineMemOperand *LargeMMO =
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MF.getMachineMemOperand(&MMO, 0, LargeSplitSize / 8);
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MachineMemOperand *SmallMMO =
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MF.getMachineMemOperand(&MMO, LargeSplitSize / 8, SmallSplitSize / 8);
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MIRBuilder.buildStore(ExtVal.getReg(0), PtrReg, *LargeMMO);
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MIRBuilder.buildStore(SmallVal.getReg(0), SmallPtr.getReg(0), *SmallMMO);
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_CTLZ_ZERO_UNDEF:
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case TargetOpcode::G_CTTZ_ZERO_UNDEF:
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case TargetOpcode::G_CTLZ:
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@ -235,12 +235,14 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {
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.legalForTypesWithMemDesc({{s32, p0, 8, 8},
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{s32, p0, 16, 8}})
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.clampScalar(0, s8, s64)
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.lowerIfMemSizeNotPow2()
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.widenScalarToNextPow2(0)
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// TODO: We could support sum-of-pow2's but the lowering code doesn't know
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// how to do that yet.
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.unsupportedIfMemSizeNotPow2()
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// Lower any any-extending loads left into G_ANYEXT and G_LOAD
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.lowerIf([=](const LegalityQuery &Query) {
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return Query.Types[0].getSizeInBits() != Query.MMODescrs[0].SizeInBits;
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})
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.widenScalarToNextPow2(0)
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.clampMaxNumElements(0, s32, 2)
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.clampMaxNumElements(0, s64, 1)
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.customIf(IsPtrVecPred);
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@ -248,8 +250,6 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {
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getActionDefinitionsBuilder(G_STORE)
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.legalForTypesWithMemDesc({{s8, p0, 8, 8},
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{s16, p0, 16, 8},
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{s32, p0, 8, 8},
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{s32, p0, 16, 8},
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{s32, p0, 32, 8},
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{s64, p0, 64, 8},
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{p0, p0, 64, 8},
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@ -260,7 +260,10 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {
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{v4s32, p0, 128, 8},
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{v2s64, p0, 128, 8}})
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.clampScalar(0, s8, s64)
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.lowerIfMemSizeNotPow2()
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.widenScalarToNextPow2(0)
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// TODO: We could support sum-of-pow2's but the lowering code doesn't know
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// how to do that yet.
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.unsupportedIfMemSizeNotPow2()
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.lowerIf([=](const LegalityQuery &Query) {
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return Query.Types[0].isScalar() &&
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Query.Types[0].getSizeInBits() != Query.MMODescrs[0].SizeInBits;
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@ -54,6 +54,26 @@ false:
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}
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; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %3:_(s32) = G_LOAD %1:_(p0) :: (load 3 from `i24* undef`, align 1) (in function: odd_type_load)
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; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for odd_type_load
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; FALLBACK-WITH-REPORT-OUT-LABEL: odd_type_load
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define i32 @odd_type_load() {
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entry:
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%ld = load i24, i24* undef, align 1
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%cst = zext i24 %ld to i32
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ret i32 %cst
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}
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; General legalizer inability to handle types whose size wasn't a power of 2.
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; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_STORE %1:_(s42), %0:_(p0) :: (store 6 into %ir.addr, align 8) (in function: odd_type)
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; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for odd_type
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; FALLBACK-WITH-REPORT-OUT-LABEL: odd_type:
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define void @odd_type(i42* %addr) {
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%val42 = load i42, i42* %addr
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store i42 %val42, i42* %addr
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ret void
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}
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; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_STORE %1:_(<7 x s32>), %0:_(p0) :: (store 28 into %ir.addr, align 32) (in function: odd_vector)
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; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for odd_vector
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; FALLBACK-WITH-REPORT-OUT-LABEL: odd_vector:
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@ -1,49 +0,0 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - -verify-machineinstrs | FileCheck %s
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--- |
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64"
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define i32 @load_store_test(i24* %ptr, i24* %ptr2) {
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%val = load i24, i24* %ptr
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store i24 %val, i24* %ptr2
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ret i32 0
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}
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...
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---
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name: load_store_test
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1 (%ir-block.0):
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liveins: $x0, $x1
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; CHECK-LABEL: name: load_store_test
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; CHECK: liveins: $x0, $x1
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; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 2 from %ir.ptr, align 4)
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; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
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; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C1]](s64)
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; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[GEP]](p0) :: (load 1 from %ir.ptr + 2, align 4)
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; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD1]], [[C2]](s32)
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; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LOAD]]
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
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; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY2]], [[C2]](s32)
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; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[COPY1]], [[C1]](s64)
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; CHECK: G_STORE [[COPY2]](s32), [[COPY1]](p0) :: (store 2 into %ir.ptr2, align 4)
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; CHECK: G_STORE [[LSHR]](s32), [[GEP1]](p0) :: (store 1 into %ir.ptr2 + 2, align 4)
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; CHECK: $w0 = COPY [[C]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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%0:_(p0) = COPY $x0
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%1:_(p0) = COPY $x1
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%3:_(s32) = G_CONSTANT i32 0
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%2:_(s24) = G_LOAD %0(p0) :: (load 3 from %ir.ptr, align 4)
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G_STORE %2(s24), %1(p0) :: (store 3 into %ir.ptr2, align 4)
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$w0 = COPY %3(s32)
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RET_ReallyLR implicit $w0
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...
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