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ARM alternate size suffices for VTRN instructions.

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rdar://10435076

llvm-svn: 144694
This commit is contained in:
Jim Grosbach 2011-11-15 20:49:46 +00:00
parent f71db061ba
commit 4d0ad5a4e0
2 changed files with 76 additions and 0 deletions
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16
lib/Target/ARM/ARMInstrNEON.td
View File

@ -5442,3 +5442,19 @@ defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm",
// (VST1d32Q addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>; // (VST1d32Q addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>;
//defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn", //defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn",
// (VST1d64Q addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>; // (VST1d64Q addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>;
// VTRN instructions data type suffix aliases for more-specific types.
defm : VFPDT8ReqInstAlias <"vtrn${p}", "$Dd, $Dm",
(VTRNd8 DPR:$Dd, DPR:$Dm, pred:$p)>;
defm : VFPDT16ReqInstAlias<"vtrn${p}", "$Dd, $Dm",
(VTRNd16 DPR:$Dd, DPR:$Dm, pred:$p)>;
defm : VFPDT32ReqInstAlias<"vtrn${p}", "$Dd, $Dm",
(VTRNd32 DPR:$Dd, DPR:$Dm, pred:$p)>;
defm : VFPDT8ReqInstAlias <"vtrn${p}", "$Qd, $Qm",
(VTRNq8 QPR:$Qd, QPR:$Qm, pred:$p)>;
defm : VFPDT16ReqInstAlias<"vtrn${p}", "$Qd, $Qm",
(VTRNq16 QPR:$Qd, QPR:$Qm, pred:$p)>;
defm : VFPDT32ReqInstAlias<"vtrn${p}", "$Qd, $Qm",
(VTRNq32 QPR:$Qd, QPR:$Qm, pred:$p)>;

60
test/MC/ARM/neon-shuffle-encoding.s
View File

@ -44,3 +44,63 @@
vzip.16 q9, q8 vzip.16 q9, q8
@ CHECK: vzip.32 q9, q8 @ encoding: [0xe0,0x21,0xfa,0xf3] @ CHECK: vzip.32 q9, q8 @ encoding: [0xe0,0x21,0xfa,0xf3]
vzip.32 q9, q8 vzip.32 q9, q8
@ VTRN alternate size suffices
vtrn.8 d3, d9
vtrn.i8 d3, d9
vtrn.u8 d3, d9
vtrn.p8 d3, d9
vtrn.16 d3, d9
vtrn.i16 d3, d9
vtrn.u16 d3, d9
vtrn.p16 d3, d9
vtrn.32 d3, d9
vtrn.i32 d3, d9
vtrn.u32 d3, d9
vtrn.f32 d3, d9
vtrn.f d3, d9
vtrn.8 q14, q6
vtrn.i8 q14, q6
vtrn.u8 q14, q6
vtrn.p8 q14, q6
vtrn.16 q14, q6
vtrn.i16 q14, q6
vtrn.u16 q14, q6
vtrn.p16 q14, q6
vtrn.32 q14, q6
vtrn.i32 q14, q6
vtrn.u32 q14, q6
vtrn.f32 q14, q6
vtrn.f q14, q6
@ CHECK: vtrn.8 d3, d9 @ encoding: [0x89,0x30,0xb2,0xf3]
@ CHECK: vtrn.8 d3, d9 @ encoding: [0x89,0x30,0xb2,0xf3]
@ CHECK: vtrn.8 d3, d9 @ encoding: [0x89,0x30,0xb2,0xf3]
@ CHECK: vtrn.8 d3, d9 @ encoding: [0x89,0x30,0xb2,0xf3]
@ CHECK: vtrn.16 d3, d9 @ encoding: [0x89,0x30,0xb6,0xf3]
@ CHECK: vtrn.16 d3, d9 @ encoding: [0x89,0x30,0xb6,0xf3]
@ CHECK: vtrn.16 d3, d9 @ encoding: [0x89,0x30,0xb6,0xf3]
@ CHECK: vtrn.16 d3, d9 @ encoding: [0x89,0x30,0xb6,0xf3]
@ CHECK: vtrn.32 d3, d9 @ encoding: [0x89,0x30,0xba,0xf3]
@ CHECK: vtrn.32 d3, d9 @ encoding: [0x89,0x30,0xba,0xf3]
@ CHECK: vtrn.32 d3, d9 @ encoding: [0x89,0x30,0xba,0xf3]
@ CHECK: vtrn.32 d3, d9 @ encoding: [0x89,0x30,0xba,0xf3]
@ CHECK: vtrn.32 d3, d9 @ encoding: [0x89,0x30,0xba,0xf3]
@ CHECK: vtrn.8 q14, q6 @ encoding: [0xcc,0xc0,0xf2,0xf3]
@ CHECK: vtrn.8 q14, q6 @ encoding: [0xcc,0xc0,0xf2,0xf3]
@ CHECK: vtrn.8 q14, q6 @ encoding: [0xcc,0xc0,0xf2,0xf3]
@ CHECK: vtrn.8 q14, q6 @ encoding: [0xcc,0xc0,0xf2,0xf3]
@ CHECK: vtrn.16 q14, q6 @ encoding: [0xcc,0xc0,0xf6,0xf3]
@ CHECK: vtrn.16 q14, q6 @ encoding: [0xcc,0xc0,0xf6,0xf3]
@ CHECK: vtrn.16 q14, q6 @ encoding: [0xcc,0xc0,0xf6,0xf3]
@ CHECK: vtrn.16 q14, q6 @ encoding: [0xcc,0xc0,0xf6,0xf3]
@ CHECK: vtrn.32 q14, q6 @ encoding: [0xcc,0xc0,0xfa,0xf3]
@ CHECK: vtrn.32 q14, q6 @ encoding: [0xcc,0xc0,0xfa,0xf3]
@ CHECK: vtrn.32 q14, q6 @ encoding: [0xcc,0xc0,0xfa,0xf3]
@ CHECK: vtrn.32 q14, q6 @ encoding: [0xcc,0xc0,0xfa,0xf3]
@ CHECK: vtrn.32 q14, q6 @ encoding: [0xcc,0xc0,0xfa,0xf3]