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Build correct vector filled with undef nodes

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llvm-svn: 217570
This commit is contained in:
David Xu 2014-09-11 05:10:28 +00:00
parent 83a8cc35ba
commit 4d7f013423
2 changed files with 62 additions and 4 deletions
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24
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -2664,9 +2664,17 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
// fold (and x, 0) -> 0, vector edition
if (ISD::isBuildVectorAllZeros(N0.getNode()))
return N0;
// do not return N0, because undef node may exist in N0
return DAG.getConstant(
APInt::getNullValue(
N0.getValueType().getScalarType().getSizeInBits()),
N0.getValueType());
if (ISD::isBuildVectorAllZeros(N1.getNode()))
return N1;
// do not return N1, because undef node may exist in N1
return DAG.getConstant(
APInt::getNullValue(
N1.getValueType().getScalarType().getSizeInBits()),
N1.getValueType());
// fold (and x, -1) -> x, vector edition
if (ISD::isBuildVectorAllOnes(N0.getNode()))
@ -3312,9 +3320,17 @@ SDValue DAGCombiner::visitOR(SDNode *N) {
// fold (or x, -1) -> -1, vector edition
if (ISD::isBuildVectorAllOnes(N0.getNode()))
return N0;
// do not return N0, because undef node may exist in N0
return DAG.getConstant(
APInt::getAllOnesValue(
N0.getValueType().getScalarType().getSizeInBits()),
N0.getValueType());
if (ISD::isBuildVectorAllOnes(N1.getNode()))
return N1;
// do not return N1, because undef node may exist in N1
return DAG.getConstant(
APInt::getAllOnesValue(
N1.getValueType().getScalarType().getSizeInBits()),
N1.getValueType());
// fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask1)
// fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf B, A, Mask2)

42
test/CodeGen/AArch64/aarch64_tree_tests.ll Normal file
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@ -0,0 +1,42 @@
; RUN: llc < %s | FileCheck %s
; ModuleID = 'aarch64_tree_tests.bc'
target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
target triple = "arm64--linux-gnu"
; CHECK-LABLE: @aarch64_tree_tests_and
; CHECK: .hword 32768
; CHECK: .hword 32767
; CHECK: .hword 4664
; CHECK: .hword 32767
; CHECK: .hword 32768
; CHECK: .hword 32768
; CHECK: .hword 0
; CHECK: .hword 0
; Function Attrs: nounwind readnone
define <8 x i16> @aarch64_tree_tests_and(<8 x i16> %a) {
entry:
%and = and <8 x i16> <i16 0, i16 undef, i16 undef, i16 0, i16 0, i16 undef, i16 undef, i16 0>, %a
%ret = add <8 x i16> %and, <i16 -32768, i16 32767, i16 4664, i16 32767, i16 -32768, i16 -32768, i16 0, i16 0>
ret <8 x i16> %ret
}
; CHECK-LABLE: @aarch64_tree_tests_or
; CHECK: .hword 32768
; CHECK: .hword 32766
; CHECK: .hword 4664
; CHECK: .hword 32766
; CHECK: .hword 32768
; CHECK: .hword 32768
; CHECK: .hword 65535
; CHECK: .hword 65535
; Function Attrs: nounwind readnone
define <8 x i16> @aarch64_tree_tests_or(<8 x i16> %a) {
entry:
%or = or <8 x i16> <i16 -1, i16 undef, i16 undef, i16 -1, i16 -1, i16 undef, i16 undef, i16 -1>, %a
%ret = add <8 x i16> %or, <i16 -32767, i16 32767, i16 4665, i16 32767, i16 -32767, i16 -32767, i16 0, i16 0>
ret <8 x i16> %ret
}