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[AMDGPU][MC] New syntax for ds_swizzle_b32 offset
See Bug 28601: https://bugs.llvm.org//show_bug.cgi?id=28601 Reviewers: artem.tamazov, vpykhtin Differential Revision: https://reviews.llvm.org/D33542 llvm-svn: 304309
This commit is contained in:
Dmitry Preobrazhensky
parent
87c40bfe25
commit
4d8a23e13b
@ -161,7 +161,8 @@ public:
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ImmTyOpSel,
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ImmTyOpSelHi,
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ImmTyNegLo,
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ImmTyNegHi
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ImmTyNegHi,
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ImmTySwizzle
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};
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struct TokOp {
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@ -474,6 +475,7 @@ public:
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bool isSWaitCnt() const;
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bool isHwreg() const;
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bool isSendMsg() const;
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bool isSwizzle() const;
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bool isSMRDOffset8() const;
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bool isSMRDOffset20() const;
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bool isSMRDLiteralOffset() const;
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@ -659,6 +661,7 @@ public:
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case ImmTyOpSelHi: OS << "OpSelHi"; break;
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case ImmTyNegLo: OS << "NegLo"; break;
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case ImmTyNegHi: OS << "NegHi"; break;
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case ImmTySwizzle: OS << "Swizzle"; break;
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}
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}
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@ -994,6 +997,12 @@ private:
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bool isInlineConstant(const MCInst &Inst, unsigned OpIdx) const;
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unsigned findImplicitSGPRReadInVOP(const MCInst &Inst) const;
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bool trySkipId(const StringRef Id);
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bool trySkipToken(const AsmToken::TokenKind Kind);
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bool skipToken(const AsmToken::TokenKind Kind, const StringRef ErrMsg);
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bool parseString(StringRef &Val, const StringRef ErrMsg = "expected a string");
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bool parseExpr(int64_t &Imm);
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public:
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OperandMatchResultTy parseOptionalOperand(OperandVector &Operands);
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@ -1003,6 +1012,19 @@ public:
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OperandMatchResultTy parseInterpAttr(OperandVector &Operands);
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OperandMatchResultTy parseSOppBrTarget(OperandVector &Operands);
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bool parseSwizzleOperands(const unsigned OpNum, int64_t* Op,
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const unsigned MinVal,
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const unsigned MaxVal,
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const StringRef ErrMsg);
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OperandMatchResultTy parseSwizzleOp(OperandVector &Operands);
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bool parseSwizzleOffset(int64_t &Imm);
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bool parseSwizzleMacro(int64_t &Imm);
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bool parseSwizzleQuadPerm(int64_t &Imm);
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bool parseSwizzleBitmaskPerm(int64_t &Imm);
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bool parseSwizzleBroadcast(int64_t &Imm);
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bool parseSwizzleSwap(int64_t &Imm);
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bool parseSwizzleReverse(int64_t &Imm);
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void cvtMubuf(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, false, false); }
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void cvtMubufAtomic(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, true, false); }
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void cvtMubufAtomicReturn(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, true, true); }
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@ -2785,7 +2807,13 @@ void AMDGPUAsmParser::cvtDSImpl(MCInst &Inst, const OperandVector &Operands,
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OptionalIdx[Op.getImmTy()] = i;
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}
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addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOffset);
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AMDGPUOperand::ImmTy OffsetType =
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(Inst.getOpcode() == AMDGPU::DS_SWIZZLE_B32_si ||
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Inst.getOpcode() == AMDGPU::DS_SWIZZLE_B32_vi) ? AMDGPUOperand::ImmTySwizzle :
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AMDGPUOperand::ImmTyOffset;
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addOptionalImmOperand(Inst, Operands, OptionalIdx, OffsetType);
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if (!IsGdsHardcoded) {
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addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGDS);
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}
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@ -3383,6 +3411,298 @@ bool AMDGPUOperand::isSendMsg() const {
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return isImmTy(ImmTySendMsg);
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}
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//===----------------------------------------------------------------------===//
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// parser helpers
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//===----------------------------------------------------------------------===//
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bool
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AMDGPUAsmParser::trySkipId(const StringRef Id) {
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if (getLexer().getKind() == AsmToken::Identifier &&
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Parser.getTok().getString() == Id) {
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Parser.Lex();
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return true;
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}
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return false;
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}
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bool
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AMDGPUAsmParser::trySkipToken(const AsmToken::TokenKind Kind) {
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if (getLexer().getKind() == Kind) {
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Parser.Lex();
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return true;
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}
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return false;
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}
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bool
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AMDGPUAsmParser::skipToken(const AsmToken::TokenKind Kind,
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const StringRef ErrMsg) {
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if (!trySkipToken(Kind)) {
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Error(Parser.getTok().getLoc(), ErrMsg);
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return false;
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}
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return true;
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}
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bool
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AMDGPUAsmParser::parseExpr(int64_t &Imm) {
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return !getParser().parseAbsoluteExpression(Imm);
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}
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bool
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AMDGPUAsmParser::parseString(StringRef &Val, const StringRef ErrMsg) {
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SMLoc S = Parser.getTok().getLoc();
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if (getLexer().getKind() == AsmToken::String) {
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Val = Parser.getTok().getStringContents();
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Parser.Lex();
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return true;
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} else {
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Error(S, ErrMsg);
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return false;
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}
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}
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//===----------------------------------------------------------------------===//
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// swizzle
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//===----------------------------------------------------------------------===//
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LLVM_READNONE
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static unsigned
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encodeBitmaskPerm(const unsigned AndMask,
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const unsigned OrMask,
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const unsigned XorMask) {
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using namespace llvm::AMDGPU::Swizzle;
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return BITMASK_PERM_ENC |
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(AndMask << BITMASK_AND_SHIFT) |
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(OrMask << BITMASK_OR_SHIFT) |
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(XorMask << BITMASK_XOR_SHIFT);
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}
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bool
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AMDGPUAsmParser::parseSwizzleOperands(const unsigned OpNum, int64_t* Op,
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const unsigned MinVal,
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const unsigned MaxVal,
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const StringRef ErrMsg) {
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for (unsigned i = 0; i < OpNum; ++i) {
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if (!skipToken(AsmToken::Comma, "expected a comma")){
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return false;
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}
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SMLoc ExprLoc = Parser.getTok().getLoc();
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if (!parseExpr(Op[i])) {
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return false;
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}
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if (Op[i] < MinVal || Op[i] > MaxVal) {
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Error(ExprLoc, ErrMsg);
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return false;
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}
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}
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return true;
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}
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bool
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AMDGPUAsmParser::parseSwizzleQuadPerm(int64_t &Imm) {
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using namespace llvm::AMDGPU::Swizzle;
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int64_t Lane[LANE_NUM];
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if (parseSwizzleOperands(LANE_NUM, Lane, 0, LANE_MAX,
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"expected a 2-bit lane id")) {
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Imm = QUAD_PERM_ENC;
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for (auto i = 0; i < LANE_NUM; ++i) {
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Imm |= Lane[i] << (LANE_SHIFT * i);
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}
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return true;
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}
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return false;
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}
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bool
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AMDGPUAsmParser::parseSwizzleBroadcast(int64_t &Imm) {
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using namespace llvm::AMDGPU::Swizzle;
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SMLoc S = Parser.getTok().getLoc();
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int64_t GroupSize;
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int64_t LaneIdx;
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if (!parseSwizzleOperands(1, &GroupSize,
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2, 32,
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"group size must be in the interval [2,32]")) {
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return false;
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}
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if (!isPowerOf2_64(GroupSize)) {
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Error(S, "group size must be a power of two");
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return false;
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}
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if (parseSwizzleOperands(1, &LaneIdx,
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0, GroupSize - 1,
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"lane id must be in the interval [0,group size - 1]")) {
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Imm = encodeBitmaskPerm(BITMASK_MAX - GroupSize + 1, LaneIdx, 0);
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return true;
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}
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return false;
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}
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bool
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AMDGPUAsmParser::parseSwizzleReverse(int64_t &Imm) {
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using namespace llvm::AMDGPU::Swizzle;
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SMLoc S = Parser.getTok().getLoc();
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int64_t GroupSize;
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if (!parseSwizzleOperands(1, &GroupSize,
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2, 32, "group size must be in the interval [2,32]")) {
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return false;
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}
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if (!isPowerOf2_64(GroupSize)) {
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Error(S, "group size must be a power of two");
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return false;
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}
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Imm = encodeBitmaskPerm(BITMASK_MAX, 0, GroupSize - 1);
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return true;
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}
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bool
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AMDGPUAsmParser::parseSwizzleSwap(int64_t &Imm) {
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using namespace llvm::AMDGPU::Swizzle;
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SMLoc S = Parser.getTok().getLoc();
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int64_t GroupSize;
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if (!parseSwizzleOperands(1, &GroupSize,
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1, 16, "group size must be in the interval [1,16]")) {
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return false;
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}
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if (!isPowerOf2_64(GroupSize)) {
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Error(S, "group size must be a power of two");
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return false;
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}
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Imm = encodeBitmaskPerm(BITMASK_MAX, 0, GroupSize);
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return true;
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}
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bool
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AMDGPUAsmParser::parseSwizzleBitmaskPerm(int64_t &Imm) {
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using namespace llvm::AMDGPU::Swizzle;
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if (!skipToken(AsmToken::Comma, "expected a comma")) {
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return false;
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}
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StringRef Ctl;
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SMLoc StrLoc = Parser.getTok().getLoc();
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if (!parseString(Ctl)) {
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return false;
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}
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if (Ctl.size() != BITMASK_WIDTH) {
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Error(StrLoc, "expected a 5-character mask");
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return false;
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}
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unsigned AndMask = 0;
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unsigned OrMask = 0;
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unsigned XorMask = 0;
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for (size_t i = 0; i < Ctl.size(); ++i) {
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unsigned Mask = 1 << (BITMASK_WIDTH - 1 - i);
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switch(Ctl[i]) {
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default:
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Error(StrLoc, "invalid mask");
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return false;
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case '0':
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break;
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case '1':
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OrMask |= Mask;
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break;
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case 'p':
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AndMask |= Mask;
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break;
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case 'i':
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AndMask |= Mask;
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XorMask |= Mask;
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break;
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}
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}
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Imm = encodeBitmaskPerm(AndMask, OrMask, XorMask);
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return true;
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}
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bool
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AMDGPUAsmParser::parseSwizzleOffset(int64_t &Imm) {
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SMLoc OffsetLoc = Parser.getTok().getLoc();
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if (!parseExpr(Imm)) {
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return false;
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}
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if (!isUInt<16>(Imm)) {
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Error(OffsetLoc, "expected a 16-bit offset");
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return false;
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}
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return true;
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}
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bool
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AMDGPUAsmParser::parseSwizzleMacro(int64_t &Imm) {
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using namespace llvm::AMDGPU::Swizzle;
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if (skipToken(AsmToken::LParen, "expected a left parentheses")) {
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SMLoc ModeLoc = Parser.getTok().getLoc();
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bool Ok = false;
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if (trySkipId(IdSymbolic[ID_QUAD_PERM])) {
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Ok = parseSwizzleQuadPerm(Imm);
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} else if (trySkipId(IdSymbolic[ID_BITMASK_PERM])) {
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Ok = parseSwizzleBitmaskPerm(Imm);
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} else if (trySkipId(IdSymbolic[ID_BROADCAST])) {
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Ok = parseSwizzleBroadcast(Imm);
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} else if (trySkipId(IdSymbolic[ID_SWAP])) {
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Ok = parseSwizzleSwap(Imm);
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} else if (trySkipId(IdSymbolic[ID_REVERSE])) {
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Ok = parseSwizzleReverse(Imm);
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} else {
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Error(ModeLoc, "expected a swizzle mode");
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}
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return Ok && skipToken(AsmToken::RParen, "expected a closing parentheses");
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}
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return false;
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}
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OperandMatchResultTy
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AMDGPUAsmParser::parseSwizzleOp(OperandVector &Operands) {
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SMLoc S = Parser.getTok().getLoc();
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int64_t Imm = 0;
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if (trySkipId("offset")) {
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bool Ok = false;
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if (skipToken(AsmToken::Colon, "expected a colon")) {
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if (trySkipId("swizzle")) {
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Ok = parseSwizzleMacro(Imm);
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} else {
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Ok = parseSwizzleOffset(Imm);
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}
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}
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Operands.push_back(AMDGPUOperand::CreateImm(this, Imm, S, AMDGPUOperand::ImmTySwizzle));
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return Ok? MatchOperand_Success : MatchOperand_ParseFail;
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} else {
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return MatchOperand_NoMatch;
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}
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}
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bool
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AMDGPUOperand::isSwizzle() const {
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return isImmTy(ImmTySwizzle);
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}
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//===----------------------------------------------------------------------===//
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// sopp branch targets
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//===----------------------------------------------------------------------===//
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@ -145,10 +145,10 @@ class DS_1A2D_Off8_RET<string opName,
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let hasPostISelHook = 1;
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}
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class DS_1A_RET<string opName, RegisterClass rc = VGPR_32>
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class DS_1A_RET<string opName, RegisterClass rc = VGPR_32, Operand ofs = offset>
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: DS_Pseudo<opName,
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(outs rc:$vdst),
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(ins VGPR_32:$addr, offset:$offset, gds:$gds),
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(ins VGPR_32:$addr, ofs:$offset, gds:$gds),
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"$vdst, $addr$offset$gds"> {
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let has_data0 = 0;
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@ -440,7 +440,7 @@ def DS_WRITE_SRC2_B32 : DS_1A<"ds_write_src2_b32">;
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def DS_WRITE_SRC2_B64 : DS_1A<"ds_write_src2_b64">;
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let Uses = [EXEC], mayLoad = 0, mayStore = 0, isConvergent = 1 in {
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def DS_SWIZZLE_B32 : DS_1A_RET <"ds_swizzle_b32">;
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def DS_SWIZZLE_B32 : DS_1A_RET <"ds_swizzle_b32", VGPR_32, SwizzleImm>;
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}
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let mayStore = 0 in {
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@ -1160,6 +1160,112 @@ void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo,
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O << SImm16; // Unknown simm16 code.
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}
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static void printSwizzleBitmask(const uint16_t AndMask,
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const uint16_t OrMask,
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const uint16_t XorMask,
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raw_ostream &O) {
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using namespace llvm::AMDGPU::Swizzle;
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uint16_t Probe0 = ((0 & AndMask) | OrMask) ^ XorMask;
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uint16_t Probe1 = ((BITMASK_MASK & AndMask) | OrMask) ^ XorMask;
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O << "\"";
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for (unsigned Mask = 1 << (BITMASK_WIDTH - 1); Mask > 0; Mask >>= 1) {
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uint16_t p0 = Probe0 & Mask;
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uint16_t p1 = Probe1 & Mask;
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if (p0 == p1) {
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if (p0 == 0) {
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O << "0";
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} else {
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O << "1";
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}
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} else {
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if (p0 == 0) {
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O << "p";
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} else {
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O << "i";
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}
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}
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}
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O << "\"";
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}
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void AMDGPUInstPrinter::printSwizzle(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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using namespace llvm::AMDGPU::Swizzle;
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uint16_t Imm = MI->getOperand(OpNo).getImm();
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if (Imm == 0) {
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return;
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}
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O << " offset:";
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if ((Imm & QUAD_PERM_ENC_MASK) == QUAD_PERM_ENC) {
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O << "swizzle(" << IdSymbolic[ID_QUAD_PERM];
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for (auto i = 0; i < LANE_NUM; ++i) {
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O << ",";
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O << formatDec(Imm & LANE_MASK);
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Imm >>= LANE_SHIFT;
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}
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O << ")";
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} else if ((Imm & BITMASK_PERM_ENC_MASK) == BITMASK_PERM_ENC) {
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uint16_t AndMask = (Imm >> BITMASK_AND_SHIFT) & BITMASK_MASK;
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uint16_t OrMask = (Imm >> BITMASK_OR_SHIFT) & BITMASK_MASK;
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uint16_t XorMask = (Imm >> BITMASK_XOR_SHIFT) & BITMASK_MASK;
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if (AndMask == BITMASK_MAX &&
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OrMask == 0 &&
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countPopulation(XorMask) == 1) {
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O << "swizzle(" << IdSymbolic[ID_SWAP];
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O << ",";
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O << formatDec(XorMask);
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O << ")";
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} else if (AndMask == BITMASK_MAX &&
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OrMask == 0 && XorMask > 0 &&
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isPowerOf2_64(XorMask + 1)) {
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|
||||
O << "swizzle(" << IdSymbolic[ID_REVERSE];
|
||||
O << ",";
|
||||
O << formatDec(XorMask + 1);
|
||||
O << ")";
|
||||
|
||||
} else {
|
||||
|
||||
uint16_t GroupSize = BITMASK_MAX - AndMask + 1;
|
||||
if (GroupSize > 1 &&
|
||||
isPowerOf2_64(GroupSize) &&
|
||||
OrMask < GroupSize &&
|
||||
XorMask == 0) {
|
||||
|
||||
O << "swizzle(" << IdSymbolic[ID_BROADCAST];
|
||||
O << ",";
|
||||
O << formatDec(GroupSize);
|
||||
O << ",";
|
||||
O << formatDec(OrMask);
|
||||
O << ")";
|
||||
|
||||
} else {
|
||||
O << "swizzle(" << IdSymbolic[ID_BITMASK_PERM];
|
||||
O << ",";
|
||||
printSwizzleBitmask(AndMask, OrMask, XorMask, O);
|
||||
O << ")";
|
||||
}
|
||||
}
|
||||
} else {
|
||||
printU16ImmDecOperand(MI, OpNo, O);
|
||||
}
|
||||
}
|
||||
|
||||
void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
|
||||
const MCSubtargetInfo &STI,
|
||||
raw_ostream &O) {
|
||||
|
||||
@ -193,6 +193,8 @@ private:
|
||||
raw_ostream &O);
|
||||
void printSendMsg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
|
||||
raw_ostream &O);
|
||||
void printSwizzle(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
|
||||
raw_ostream &O);
|
||||
void printWaitFlag(const MCInst *MI, unsigned OpNo,
|
||||
const MCSubtargetInfo &STI, raw_ostream &O);
|
||||
void printHwreg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
|
||||
|
||||
@ -281,6 +281,46 @@ enum WidthMinusOne { // WidthMinusOne, (5) [15:11]
|
||||
|
||||
} // namespace Hwreg
|
||||
|
||||
namespace Swizzle { // Encoding of swizzle macro used in ds_swizzle_b32.
|
||||
|
||||
enum Id { // id of symbolic names
|
||||
ID_QUAD_PERM = 0,
|
||||
ID_BITMASK_PERM,
|
||||
ID_SWAP,
|
||||
ID_REVERSE,
|
||||
ID_BROADCAST
|
||||
};
|
||||
|
||||
enum EncBits {
|
||||
|
||||
// swizzle mode encodings
|
||||
|
||||
QUAD_PERM_ENC = 0x8000,
|
||||
QUAD_PERM_ENC_MASK = 0xFF00,
|
||||
|
||||
BITMASK_PERM_ENC = 0x0000,
|
||||
BITMASK_PERM_ENC_MASK = 0x8000,
|
||||
|
||||
// QUAD_PERM encodings
|
||||
|
||||
LANE_MASK = 0x3,
|
||||
LANE_MAX = LANE_MASK,
|
||||
LANE_SHIFT = 2,
|
||||
LANE_NUM = 4,
|
||||
|
||||
// BITMASK_PERM encodings
|
||||
|
||||
BITMASK_MASK = 0x1F,
|
||||
BITMASK_MAX = BITMASK_MASK,
|
||||
BITMASK_WIDTH = 5,
|
||||
|
||||
BITMASK_AND_SHIFT = 0,
|
||||
BITMASK_OR_SHIFT = 5,
|
||||
BITMASK_XOR_SHIFT = 10
|
||||
};
|
||||
|
||||
} // namespace Swizzle
|
||||
|
||||
namespace SDWA {
|
||||
|
||||
enum SdwaSel {
|
||||
|
||||
@ -383,6 +383,14 @@ def SendMsgMatchClass : AsmOperandClass {
|
||||
let RenderMethod = "addImmOperands";
|
||||
}
|
||||
|
||||
def SwizzleMatchClass : AsmOperandClass {
|
||||
let Name = "Swizzle";
|
||||
let PredicateMethod = "isSwizzle";
|
||||
let ParserMethod = "parseSwizzleOp";
|
||||
let RenderMethod = "addImmOperands";
|
||||
let IsOptional = 1;
|
||||
}
|
||||
|
||||
def ExpTgtMatchClass : AsmOperandClass {
|
||||
let Name = "ExpTgt";
|
||||
let PredicateMethod = "isExpTgt";
|
||||
@ -395,6 +403,11 @@ def SendMsgImm : Operand<i32> {
|
||||
let ParserMatchClass = SendMsgMatchClass;
|
||||
}
|
||||
|
||||
def SwizzleImm : Operand<i16> {
|
||||
let PrintMethod = "printSwizzle";
|
||||
let ParserMatchClass = SwizzleMatchClass;
|
||||
}
|
||||
|
||||
def SWaitMatchClass : AsmOperandClass {
|
||||
let Name = "SWaitCnt";
|
||||
let RenderMethod = "addImmOperands";
|
||||
|
||||
@ -65,5 +65,18 @@ const char* const IdSymbolic[] = {
|
||||
};
|
||||
|
||||
} // namespace Hwreg
|
||||
|
||||
namespace Swizzle {
|
||||
|
||||
// This must be in sync with llvm::AMDGPU::Swizzle::Id enum members, see SIDefines.h.
|
||||
const char* const IdSymbolic[] = {
|
||||
"QUAD_PERM",
|
||||
"BITMASK_PERM",
|
||||
"SWAP",
|
||||
"REVERSE",
|
||||
"BROADCAST",
|
||||
};
|
||||
|
||||
} // namespace Swizzle
|
||||
} // namespace AMDGPU
|
||||
} // namespace llvm
|
||||
|
||||
@ -25,6 +25,12 @@ namespace Hwreg { // Symbolic names for the hwreg(...) syntax.
|
||||
extern const char* const IdSymbolic[];
|
||||
|
||||
} // namespace Hwreg
|
||||
|
||||
namespace Swizzle { // Symbolic names for the swizzle(...) syntax.
|
||||
|
||||
extern const char* const IdSymbolic[];
|
||||
|
||||
} // namespace Swizzle
|
||||
} // namespace AMDGPU
|
||||
} // namespace llvm
|
||||
|
||||
|
||||
@ -4,7 +4,7 @@
|
||||
declare i32 @llvm.amdgcn.ds.swizzle(i32, i32) #0
|
||||
|
||||
; FUNC-LABEL: {{^}}ds_swizzle:
|
||||
; CHECK: ds_swizzle_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:100
|
||||
; CHECK: ds_swizzle_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:swizzle(BITMASK_PERM,"00p11")
|
||||
; CHECK: s_waitcnt lgkmcnt
|
||||
define amdgpu_kernel void @ds_swizzle(i32 addrspace(1)* %out, i32 %src) nounwind {
|
||||
%swizzle = call i32 @llvm.amdgcn.ds.swizzle(i32 %src, i32 100) #0
|
||||
|
||||
@ -21,3 +21,93 @@ ds_write2_b32 v2, v4, v6 offset0:1000000000
|
||||
// CHECK: invalid operand for instruction
|
||||
ds_write2_b32 v2, v4, v6 offset1:1000000000
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// swizzle
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// CHECK: error: expected a colon
|
||||
ds_swizzle_b32 v8, v2 offset
|
||||
|
||||
// CHECK: error: failed parsing operand
|
||||
ds_swizzle_b32 v8, v2 offset:
|
||||
|
||||
// CHECK: error: expected a colon
|
||||
ds_swizzle_b32 v8, v2 offset-
|
||||
|
||||
// CHECK: error: expected absolute expression
|
||||
ds_swizzle_b32 v8, v2 offset:SWIZZLE(QUAD_PERM, 0, 1, 2, 3)
|
||||
|
||||
// CHECK: error: expected a swizzle mode
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(quad_perm, 0, 1, 2, 3)
|
||||
|
||||
// CHECK: error: expected a swizzle mode
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(XXX,1)
|
||||
|
||||
// CHECK: error: expected a comma
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM
|
||||
|
||||
// CHECK: error: expected a comma
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2)
|
||||
|
||||
// CHECK: error: expected a closing parentheses
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2, 3
|
||||
|
||||
// CHECK: error: expected a closing parentheses
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2, 3, 4)
|
||||
|
||||
// CHECK: error: expected a 2-bit lane id
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, -1, 1, 2, 3)
|
||||
|
||||
// CHECK: error: expected a 2-bit lane id
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 4, 1, 2, 3)
|
||||
|
||||
// CHECK: error: group size must be in the interval [1,16]
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,0)
|
||||
|
||||
// CHECK: error: group size must be a power of two
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,3)
|
||||
|
||||
// CHECK: error: group size must be in the interval [1,16]
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,17)
|
||||
|
||||
// CHECK: error: group size must be in the interval [1,16]
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,32)
|
||||
|
||||
// CHECK: error: group size must be in the interval [2,32]
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(REVERSE,1)
|
||||
|
||||
// CHECK: error: group size must be a power of two
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(REVERSE,3)
|
||||
|
||||
// CHECK: error: group size must be in the interval [2,32]
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(REVERSE,33)
|
||||
|
||||
// CHECK: error: group size must be in the interval [2,32]
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,1,0)
|
||||
|
||||
// CHECK: error: group size must be a power of two
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,3,1)
|
||||
|
||||
// CHECK: error: group size must be in the interval [2,32]
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,33,1)
|
||||
|
||||
// CHECK: error: lane id must be in the interval [0,group size - 1]
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,2,-1)
|
||||
|
||||
// CHECK: error: lane id must be in the interval [0,group size - 1]
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,2,2)
|
||||
|
||||
// CHECK: error: expected a string
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, pppii)
|
||||
|
||||
// CHECK: error: expected a 5-character mask
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, "")
|
||||
|
||||
// CHECK: error: expected a 5-character mask
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, "ppii")
|
||||
|
||||
// CHECK: error: expected a 5-character mask
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, "pppiii")
|
||||
|
||||
// CHECK: invalid mask
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, "pppi2")
|
||||
|
||||
@ -267,10 +267,6 @@ ds_max_rtn_f32 v8, v2, v4
|
||||
// SICI: ds_max_rtn_f32 v8, v2, v4 ; encoding: [0x00,0x00,0xcc,0xd8,0x02,0x04,0x00,0x08]
|
||||
// VI: ds_max_rtn_f32 v8, v2, v4 ; encoding: [0x00,0x00,0x66,0xd8,0x02,0x04,0x00,0x08]
|
||||
|
||||
ds_swizzle_b32 v8, v2
|
||||
// SICI: ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0xd4,0xd8,0x02,0x00,0x00,0x08]
|
||||
// VI: ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0x7a,0xd8,0x02,0x00,0x00,0x08]
|
||||
|
||||
ds_read_b32 v8, v2
|
||||
// SICI: ds_read_b32 v8, v2 ; encoding: [0x00,0x00,0xd8,0xd8,0x02,0x00,0x00,0x08]
|
||||
// VI: ds_read_b32 v8, v2 ; encoding: [0x00,0x00,0x6c,0xd8,0x02,0x00,0x00,0x08]
|
||||
@ -506,3 +502,143 @@ ds_nop
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CI: ds_nop ; encoding: [0x00,0x00,0x50,0xd8,0x00,0x00,0x00,0x00]
|
||||
// VI: ds_nop ; encoding: [0x00,0x00,0x28,0xd8,0x00,0x00,0x00,0x00]
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// swizzle
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
ds_swizzle_b32 v8, v2
|
||||
// SICI: ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0xd4,0xd8,0x02,0x00,0x00,0x08]
|
||||
// VI: ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0x7a,0xd8,0x02,0x00,0x00,0x08]
|
||||
|
||||
ds_swizzle_b32 v8, v2 offset:0xFFFF
|
||||
// SICI: ds_swizzle_b32 v8, v2 offset:65535 ; encoding: [0xff,0xff,0xd4,0xd8,0x02,0x00,0x00,0x08]
|
||||
// VI: ds_swizzle_b32 v8, v2 offset:65535 ; encoding: [0xff,0xff,0x7a,0xd8,0x02,0x00,0x00,0x08]
|
||||
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2, 3)
|
||||
// SICI: ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM,0,1,2,3) ; encoding: [0xe4,0x80,0xd4,0xd8,0x02,0x00,0x00,0x08]
|
||||
// VI: ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM,0,1,2,3) ; encoding: [0xe4,0x80,0x7a,0xd8,0x02,0x00,0x00,0x08]
|
||||
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 2, 1, 3, 3)
|
||||
// SICI: ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM,2,1,3,3) ; encoding: [0xf6,0x80,0xd4,0xd8,0x02,0x00,0x00,0x08]
|
||||
// VI: ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM,2,1,3,3) ; encoding: [0xf6,0x80,0x7a,0xd8,0x02,0x00,0x00,0x08]
|
||||
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,1)
|
||||
// SICI: ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,1) ; encoding: [0x1f,0x04,0xd4,0xd8,0x02,0x00,0x00,0x08]
|
||||
// VI: ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,1) ; encoding: [0x1f,0x04,0x7a,0xd8,0x02,0x00,0x00,0x08]
|
||||
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,2)
|
||||
// SICI: ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,2) ; encoding: [0x1f,0x08,0xd4,0xd8,0x02,0x00,0x00,0x08]
|
||||
// VI: ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,2) ; encoding: [0x1f,0x08,0x7a,0xd8,0x02,0x00,0x00,0x08]
|
||||
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,4)
|
||||
// SICI: ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,4) ; encoding: [0x1f,0x10,0xd4,0xd8,0x02,0x00,0x00,0x08]
|
||||
// VI: ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,4) ; encoding: [0x1f,0x10,0x7a,0xd8,0x02,0x00,0x00,0x08]
|
||||
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,8)
|
||||
// SICI: ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,8) ; encoding: [0x1f,0x20,0xd4,0xd8,0x02,0x00,0x00,0x08]
|
||||
// VI: ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,8) ; encoding: [0x1f,0x20,0x7a,0xd8,0x02,0x00,0x00,0x08]
|
||||
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,16)
|
||||
// SICI: ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,16) ; encoding: [0x1f,0x40,0xd4,0xd8,0x02,0x00,0x00,0x08]
|
||||
// VI: ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,16) ; encoding: [0x1f,0x40,0x7a,0xd8,0x02,0x00,0x00,0x08]
|
||||
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(REVERSE,2)
|
||||
// SICI: ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,1) ; encoding: [0x1f,0x04,0xd4,0xd8,0x02,0x00,0x00,0x08]
|
||||
// VI: ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,1) ; encoding: [0x1f,0x04,0x7a,0xd8,0x02,0x00,0x00,0x08]
|
||||
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(REVERSE,4)
|
||||
// SICI: ds_swizzle_b32 v8, v2 offset:swizzle(REVERSE,4) ; encoding: [0x1f,0x0c,0xd4,0xd8,0x02,0x00,0x00,0x08]
|
||||
// VI: ds_swizzle_b32 v8, v2 offset:swizzle(REVERSE,4) ; encoding: [0x1f,0x0c,0x7a,0xd8,0x02,0x00,0x00,0x08]
|
||||
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(REVERSE,8)
|
||||
// SICI: ds_swizzle_b32 v8, v2 offset:swizzle(REVERSE,8) ; encoding: [0x1f,0x1c,0xd4,0xd8,0x02,0x00,0x00,0x08]
|
||||
// VI: ds_swizzle_b32 v8, v2 offset:swizzle(REVERSE,8) ; encoding: [0x1f,0x1c,0x7a,0xd8,0x02,0x00,0x00,0x08]
|
||||
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(REVERSE,16)
|
||||
// SICI: ds_swizzle_b32 v8, v2 offset:swizzle(REVERSE,16) ; encoding: [0x1f,0x3c,0xd4,0xd8,0x02,0x00,0x00,0x08]
|
||||
// VI: ds_swizzle_b32 v8, v2 offset:swizzle(REVERSE,16) ; encoding: [0x1f,0x3c,0x7a,0xd8,0x02,0x00,0x00,0x08]
|
||||
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(REVERSE,32)
|
||||
// SICI: ds_swizzle_b32 v8, v2 offset:swizzle(REVERSE,32) ; encoding: [0x1f,0x7c,0xd4,0xd8,0x02,0x00,0x00,0x08]
|
||||
// VI: ds_swizzle_b32 v8, v2 offset:swizzle(REVERSE,32) ; encoding: [0x1f,0x7c,0x7a,0xd8,0x02,0x00,0x00,0x08]
|
||||
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,2,1)
|
||||
// SICI: ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,2,1) ; encoding: [0x3e,0x00,0xd4,0xd8,0x02,0x00,0x00,0x08]
|
||||
// VI: ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,2,1) ; encoding: [0x3e,0x00,0x7a,0xd8,0x02,0x00,0x00,0x08]
|
||||
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,4,1)
|
||||
// SICI: ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,4,1) ; encoding: [0x3c,0x00,0xd4,0xd8,0x02,0x00,0x00,0x08]
|
||||
// VI: ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,4,1) ; encoding: [0x3c,0x00,0x7a,0xd8,0x02,0x00,0x00,0x08]
|
||||
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,8,1)
|
||||
// SICI: ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,8,1) ; encoding: [0x38,0x00,0xd4,0xd8,0x02,0x00,0x00,0x08]
|
||||
// VI: ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,8,1) ; encoding: [0x38,0x00,0x7a,0xd8,0x02,0x00,0x00,0x08]
|
||||
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,16,1)
|
||||
// SICI: ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,16,1) ; encoding: [0x30,0x00,0xd4,0xd8,0x02,0x00,0x00,0x08]
|
||||
// VI: ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,16,1) ; encoding: [0x30,0x00,0x7a,0xd8,0x02,0x00,0x00,0x08]
|
||||
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,32,1)
|
||||
// SICI: ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,32,1) ; encoding: [0x20,0x00,0xd4,0xd8,0x02,0x00,0x00,0x08]
|
||||
// VI: ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,32,1) ; encoding: [0x20,0x00,0x7a,0xd8,0x02,0x00,0x00,0x08]
|
||||
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,2,0)
|
||||
// SICI: ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,2,0) ; encoding: [0x1e,0x00,0xd4,0xd8,0x02,0x00,0x00,0x08]
|
||||
// VI: ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,2,0) ; encoding: [0x1e,0x00,0x7a,0xd8,0x02,0x00,0x00,0x08]
|
||||
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,4,3)
|
||||
// SICI: ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,4,3) ; encoding: [0x7c,0x00,0xd4,0xd8,0x02,0x00,0x00,0x08]
|
||||
// VI: ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,4,3) ; encoding: [0x7c,0x00,0x7a,0xd8,0x02,0x00,0x00,0x08]
|
||||
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,8,7)
|
||||
// SICI: ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,8,7) ; encoding: [0xf8,0x00,0xd4,0xd8,0x02,0x00,0x00,0x08]
|
||||
// VI: ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,8,7) ; encoding: [0xf8,0x00,0x7a,0xd8,0x02,0x00,0x00,0x08]
|
||||
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,16,15)
|
||||
// SICI: ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,16,15) ; encoding: [0xf0,0x01,0xd4,0xd8,0x02,0x00,0x00,0x08]
|
||||
// VI: ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,16,15) ; encoding: [0xf0,0x01,0x7a,0xd8,0x02,0x00,0x00,0x08]
|
||||
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,32,31)
|
||||
// SICI: ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,32,31) ; encoding: [0xe0,0x03,0xd4,0xd8,0x02,0x00,0x00,0x08]
|
||||
// VI: ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,32,31) ; encoding: [0xe0,0x03,0x7a,0xd8,0x02,0x00,0x00,0x08]
|
||||
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, "pppii")
|
||||
// SICI: ds_swizzle_b32 v8, v2 offset:swizzle(REVERSE,4) ; encoding: [0x1f,0x0c,0xd4,0xd8,0x02,0x00,0x00,0x08]
|
||||
// VI: ds_swizzle_b32 v8, v2 offset:swizzle(REVERSE,4) ; encoding: [0x1f,0x0c,0x7a,0xd8,0x02,0x00,0x00,0x08]
|
||||
|
||||
ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, "01pip")
|
||||
// SICI: ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM,"01pip") ; encoding: [0x07,0x09,0xd4,0xd8,0x02,0x00,0x00,0x08]
|
||||
// VI: ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM,"01pip") ; encoding: [0x07,0x09,0x7a,0xd8,0x02,0x00,0x00,0x08]
|
||||
|
||||
ds_swizzle_b32 v8, v2 offset:0x000
|
||||
// SICI: ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0xd4,0xd8,0x02,0x00,0x00,0x08]
|
||||
// VI: ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0x7a,0xd8,0x02,0x00,0x00,0x08]
|
||||
|
||||
ds_swizzle_b32 v8, v2 offset:0x001
|
||||
// SICI: ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM,"0000p") ; encoding: [0x01,0x00,0xd4,0xd8,0x02,0x00,0x00,0x08]
|
||||
// VI: ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM,"0000p") ; encoding: [0x01,0x00,0x7a,0xd8,0x02,0x00,0x00,0x08]
|
||||
|
||||
ds_swizzle_b32 v8, v2 offset:0x020
|
||||
// SICI: ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,32,1) ; encoding: [0x20,0x00,0xd4,0xd8,0x02,0x00,0x00,0x08]
|
||||
// VI: ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,32,1) ; encoding: [0x20,0x00,0x7a,0xd8,0x02,0x00,0x00,0x08]
|
||||
|
||||
ds_swizzle_b32 v8, v2 offset:0x021
|
||||
// SICI: ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM,"00001") ; encoding: [0x21,0x00,0xd4,0xd8,0x02,0x00,0x00,0x08]
|
||||
// VI: ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM,"00001") ; encoding: [0x21,0x00,0x7a,0xd8,0x02,0x00,0x00,0x08]
|
||||
|
||||
ds_swizzle_b32 v8, v2 offset:0x400
|
||||
// SICI: ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM,"00001") ; encoding: [0x00,0x04,0xd4,0xd8,0x02,0x00,0x00,0x08]
|
||||
// VI: ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM,"00001") ; encoding: [0x00,0x04,0x7a,0xd8,0x02,0x00,0x00,0x08]
|
||||
|
||||
ds_swizzle_b32 v8, v2 offset:0x401
|
||||
// SICI: ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM,"0000i") ; encoding: [0x01,0x04,0xd4,0xd8,0x02,0x00,0x00,0x08]
|
||||
// VI: ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM,"0000i") ; encoding: [0x01,0x04,0x7a,0xd8,0x02,0x00,0x00,0x08]
|
||||
|
||||
ds_swizzle_b32 v8, v2 offset:0x420
|
||||
// SICI: ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM,"00000") ; encoding: [0x20,0x04,0xd4,0xd8,0x02,0x00,0x00,0x08]
|
||||
// VI: ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM,"00000") ; encoding: [0x20,0x04,0x7a,0xd8,0x02,0x00,0x00,0x08]
|
||||
|
||||
ds_swizzle_b32 v8, v2 offset:0x421
|
||||
// SICI: ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM,"00000") ; encoding: [0x21,0x04,0xd4,0xd8,0x02,0x00,0x00,0x08]
|
||||
// VI: ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM,"00000") ; encoding: [0x21,0x04,0x7a,0xd8,0x02,0x00,0x00,0x08]
|
||||
|
||||
@ -990,23 +990,23 @@
|
||||
# CHECK: ds_read_u16 v5, v1 offset:65535 gds ; encoding: [0xff,0xff,0x79,0xd8,0x01,0x00,0x00,0x05]
|
||||
0xff,0xff,0x79,0xd8,0x01,0x00,0x00,0x05
|
||||
|
||||
# CHECK: ds_swizzle_b32 v5, v1 offset:65535 ; encoding: [0xff,0xff,0x7a,0xd8,0x01,0x00,0x00,0x05]
|
||||
0xff,0xff,0x7a,0xd8,0x01,0x00,0x00,0x05
|
||||
# CHECK: ds_swizzle_b32 v5, v1 ; encoding: [0x00,0x00,0x7a,0xd8,0x01,0x00,0x00,0x05]
|
||||
0x00,0x00,0x7a,0xd8,0x01,0x00,0x00,0x05
|
||||
|
||||
# CHECK: ds_swizzle_b32 v255, v1 offset:65535 ; encoding: [0xff,0xff,0x7a,0xd8,0x01,0x00,0x00,0xff]
|
||||
0xff,0xff,0x7a,0xd8,0x01,0x00,0x00,0xff
|
||||
# CHECK: ds_swizzle_b32 v255, v1 ; encoding: [0x00,0x00,0x7a,0xd8,0x01,0x00,0x00,0xff]
|
||||
0x00,0x00,0x7a,0xd8,0x01,0x00,0x00,0xff
|
||||
|
||||
# CHECK: ds_swizzle_b32 v5, v255 offset:65535 ; encoding: [0xff,0xff,0x7a,0xd8,0xff,0x00,0x00,0x05]
|
||||
0xff,0xff,0x7a,0xd8,0xff,0x00,0x00,0x05
|
||||
# CHECK: ds_swizzle_b32 v5, v255 ; encoding: [0x00,0x00,0x7a,0xd8,0xff,0x00,0x00,0x05]
|
||||
0x00,0x00,0x7a,0xd8,0xff,0x00,0x00,0x05
|
||||
|
||||
# CHECK: ds_swizzle_b32 v5, v1 ; encoding: [0x00,0x00,0x7a,0xd8,0x01,0x00,0x00,0x05]
|
||||
0x00,0x00,0x7a,0xd8,0x01,0x00,0x00,0x05
|
||||
|
||||
# CHECK: ds_swizzle_b32 v5, v1 offset:4 ; encoding: [0x04,0x00,0x7a,0xd8,0x01,0x00,0x00,0x05]
|
||||
0x04,0x00,0x7a,0xd8,0x01,0x00,0x00,0x05
|
||||
# CHECK: ds_swizzle_b32 v5, v1 ; encoding: [0x00,0x00,0x7a,0xd8,0x01,0x00,0x00,0x05]
|
||||
0x00,0x00,0x7a,0xd8,0x01,0x00,0x00,0x05
|
||||
|
||||
# CHECK: ds_swizzle_b32 v5, v1 offset:65535 gds ; encoding: [0xff,0xff,0x7b,0xd8,0x01,0x00,0x00,0x05]
|
||||
0xff,0xff,0x7b,0xd8,0x01,0x00,0x00,0x05
|
||||
# CHECK: ds_swizzle_b32 v5, v1 gds ; encoding: [0x00,0x00,0x7b,0xd8,0x01,0x00,0x00,0x05]
|
||||
0x00,0x00,0x7b,0xd8,0x01,0x00,0x00,0x05
|
||||
|
||||
# CHECK: ds_permute_b32 v5, v1, v2 offset:65535 ; encoding: [0xff,0xff,0x7c,0xd8,0x01,0x02,0x00,0x05]
|
||||
0xff,0xff,0x7c,0xd8,0x01,0x02,0x00,0x05
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user