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[X86] Make the MUL->VPMADDWD work before op legalization on AVX1 targets. Simplify feature checks by using isTypeLegal.
The v8i32 conversion on AVX1 targets was only working after LowerMUL splits 256-bit vectors. While I was there I've also made it so we don't have to check for AVX2 and BWI directly and instead just ask if the type is legal. Differential Revision: https://reviews.llvm.org/D44190 llvm-svn: 326917
This commit is contained in:
Craig Topper
parent
e9bba73c86
commit
4d90ec52a4
@ -32906,6 +32906,46 @@ static SDValue combineMulSpecial(uint64_t MulAmt, SDNode *N, SelectionDAG &DAG,
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return SDValue();
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}
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// If the upper 17 bits of each element are zero then we can use PMADDWD,
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// which is always at least as quick as PMULLD, expect on KNL.
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static SDValue combineMulToPMADDWD(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget &Subtarget) {
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if (!Subtarget.hasSSE2())
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return SDValue();
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if (Subtarget.getProcFamily() == X86Subtarget::IntelKNL)
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return SDValue();
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EVT VT = N->getValueType(0);
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// Only support vXi32 vectors.
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if (!VT.isVector() || VT.getVectorElementType() != MVT::i32)
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return SDValue();
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// Make sure the vXi16 type is legal. This covers the AVX512 without BWI case.
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MVT WVT = MVT::getVectorVT(MVT::i16, 2 * VT.getVectorNumElements());
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if (!DAG.getTargetLoweringInfo().isTypeLegal(WVT))
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return SDValue();
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SDValue N0 = N->getOperand(0);
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SDValue N1 = N->getOperand(1);
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APInt Mask17 = APInt::getHighBitsSet(32, 17);
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if (!DAG.MaskedValueIsZero(N1, Mask17) ||
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!DAG.MaskedValueIsZero(N0, Mask17))
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return SDValue();
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// Use SplitBinaryOpsAndApply to handle AVX splitting.
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auto PMADDWDBuilder = [](SelectionDAG &DAG, const SDLoc &DL, SDValue Op0,
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SDValue Op1) {
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MVT VT = MVT::getVectorVT(MVT::i32, Op0.getValueSizeInBits() / 32);
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return DAG.getNode(X86ISD::VPMADDWD, DL, VT, Op0, Op1);
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};
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return SplitBinaryOpsAndApply(DAG, Subtarget, SDLoc(N), VT,
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DAG.getBitcast(WVT, N0),
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DAG.getBitcast(WVT, N1), PMADDWDBuilder);
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}
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/// Optimize a single multiply with constant into two operations in order to
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/// implement it with two cheaper instructions, e.g. LEA + SHL, LEA + LEA.
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static SDValue combineMul(SDNode *N, SelectionDAG &DAG,
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@ -32913,23 +32953,8 @@ static SDValue combineMul(SDNode *N, SelectionDAG &DAG,
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const X86Subtarget &Subtarget) {
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EVT VT = N->getValueType(0);
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// If the upper 17 bits of each element are zero then we can use PMADDWD,
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// which is always at least as quick as PMULLD, expect on KNL.
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if (Subtarget.getProcFamily() != X86Subtarget::IntelKNL &&
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((VT == MVT::v4i32 && Subtarget.hasSSE2()) ||
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(VT == MVT::v8i32 && Subtarget.hasAVX2()) ||
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(VT == MVT::v16i32 && Subtarget.useBWIRegs()))) {
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SDValue N0 = N->getOperand(0);
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SDValue N1 = N->getOperand(1);
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APInt Mask17 = APInt::getHighBitsSet(32, 17);
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if (DAG.MaskedValueIsZero(N0, Mask17) &&
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DAG.MaskedValueIsZero(N1, Mask17)) {
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unsigned NumElts = VT.getVectorNumElements();
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MVT WVT = MVT::getVectorVT(MVT::i16, 2 * NumElts);
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return DAG.getNode(X86ISD::VPMADDWD, SDLoc(N), VT,
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DAG.getBitcast(WVT, N0), DAG.getBitcast(WVT, N1));
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}
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}
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if (SDValue V = combineMulToPMADDWD(N, DAG, DCI, Subtarget))
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return V;
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if (DCI.isBeforeLegalize() && VT.isVector())
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return reduceVMULWidth(N, DAG, Subtarget);
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@ -2227,89 +2227,67 @@ define void @PR34947() {
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;
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; X86-AVX1-LABEL: PR34947:
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; X86-AVX1: # %bb.0:
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; X86-AVX1-NEXT: pushl %ebp
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; X86-AVX1-NEXT: .cfi_def_cfa_offset 8
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; X86-AVX1-NEXT: pushl %ebx
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; X86-AVX1-NEXT: .cfi_def_cfa_offset 12
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; X86-AVX1-NEXT: pushl %edi
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; X86-AVX1-NEXT: .cfi_def_cfa_offset 16
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; X86-AVX1-NEXT: pushl %esi
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; X86-AVX1-NEXT: .cfi_def_cfa_offset 20
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; X86-AVX1-NEXT: subl $16, %esp
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; X86-AVX1-NEXT: .cfi_def_cfa_offset 36
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; X86-AVX1-NEXT: .cfi_offset %esi, -20
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; X86-AVX1-NEXT: .cfi_offset %edi, -16
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; X86-AVX1-NEXT: .cfi_offset %ebx, -12
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; X86-AVX1-NEXT: .cfi_offset %ebp, -8
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; X86-AVX1-NEXT: .cfi_def_cfa_offset 8
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; X86-AVX1-NEXT: .cfi_offset %esi, -8
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; X86-AVX1-NEXT: vmovdqa (%eax), %ymm0
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; X86-AVX1-NEXT: xorl %eax, %eax
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; X86-AVX1-NEXT: xorl %edx, %edx
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; X86-AVX1-NEXT: divl (%eax)
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; X86-AVX1-NEXT: movl %edx, {{[0-9]+}}(%esp) # 4-byte Spill
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; X86-AVX1-NEXT: vpextrd $3, %xmm0, %ecx
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; X86-AVX1-NEXT: xorl %eax, %eax
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; X86-AVX1-NEXT: xorl %edx, %edx
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; X86-AVX1-NEXT: divl %ecx
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; X86-AVX1-NEXT: movl %edx, {{[0-9]+}}(%esp) # 4-byte Spill
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; X86-AVX1-NEXT: vpextrd $2, %xmm0, %ecx
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; X86-AVX1-NEXT: xorl %eax, %eax
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; X86-AVX1-NEXT: xorl %edx, %edx
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; X86-AVX1-NEXT: divl %ecx
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; X86-AVX1-NEXT: movl %edx, {{[0-9]+}}(%esp) # 4-byte Spill
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; X86-AVX1-NEXT: vpextrd $1, %xmm0, %ecx
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; X86-AVX1-NEXT: xorl %eax, %eax
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; X86-AVX1-NEXT: xorl %edx, %edx
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; X86-AVX1-NEXT: divl %ecx
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; X86-AVX1-NEXT: movl %edx, (%esp) # 4-byte Spill
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; X86-AVX1-NEXT: vmovd %xmm0, %ecx
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; X86-AVX1-NEXT: movl %edx, %ecx
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; X86-AVX1-NEXT: vmovd %xmm0, %esi
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; X86-AVX1-NEXT: xorl %eax, %eax
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; X86-AVX1-NEXT: xorl %edx, %edx
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; X86-AVX1-NEXT: divl %esi
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; X86-AVX1-NEXT: vmovd %edx, %xmm1
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; X86-AVX1-NEXT: vpinsrd $1, %ecx, %xmm1, %xmm1
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; X86-AVX1-NEXT: vpextrd $2, %xmm0, %ecx
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; X86-AVX1-NEXT: xorl %eax, %eax
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; X86-AVX1-NEXT: xorl %edx, %edx
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; X86-AVX1-NEXT: divl %ecx
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; X86-AVX1-NEXT: movl %edx, %ebp
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; X86-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
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; X86-AVX1-NEXT: vpinsrd $2, %edx, %xmm1, %xmm1
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; X86-AVX1-NEXT: vpextrd $3, %xmm0, %ecx
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; X86-AVX1-NEXT: xorl %eax, %eax
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; X86-AVX1-NEXT: xorl %edx, %edx
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; X86-AVX1-NEXT: divl %ecx
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; X86-AVX1-NEXT: vpinsrd $3, %edx, %xmm1, %xmm1
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; X86-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
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; X86-AVX1-NEXT: vpextrd $1, %xmm0, %ecx
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; X86-AVX1-NEXT: xorl %eax, %eax
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; X86-AVX1-NEXT: xorl %edx, %edx
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; X86-AVX1-NEXT: vpextrd $3, %xmm0, %ecx
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; X86-AVX1-NEXT: divl %ecx
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; X86-AVX1-NEXT: movl %edx, %ecx
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; X86-AVX1-NEXT: vmovd %xmm0, %esi
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; X86-AVX1-NEXT: xorl %eax, %eax
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; X86-AVX1-NEXT: xorl %edx, %edx
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; X86-AVX1-NEXT: vpextrd $2, %xmm0, %esi
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; X86-AVX1-NEXT: divl %esi
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; X86-AVX1-NEXT: movl %edx, %esi
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; X86-AVX1-NEXT: vmovd %edx, %xmm2
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; X86-AVX1-NEXT: vpinsrd $1, %ecx, %xmm2, %xmm2
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; X86-AVX1-NEXT: vpextrd $2, %xmm0, %ecx
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; X86-AVX1-NEXT: xorl %eax, %eax
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; X86-AVX1-NEXT: xorl %edx, %edx
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; X86-AVX1-NEXT: vpextrd $1, %xmm0, %edi
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; X86-AVX1-NEXT: divl %edi
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; X86-AVX1-NEXT: movl %edx, %edi
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; X86-AVX1-NEXT: divl %ecx
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; X86-AVX1-NEXT: vpinsrd $2, %edx, %xmm2, %xmm2
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; X86-AVX1-NEXT: vpextrd $3, %xmm0, %ecx
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; X86-AVX1-NEXT: xorl %eax, %eax
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; X86-AVX1-NEXT: xorl %edx, %edx
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; X86-AVX1-NEXT: vmovd %xmm0, %ebx
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; X86-AVX1-NEXT: divl %ebx
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; X86-AVX1-NEXT: vmovd %edx, %xmm0
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; X86-AVX1-NEXT: vpinsrd $1, %edi, %xmm0, %xmm0
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; X86-AVX1-NEXT: vpinsrd $2, %esi, %xmm0, %xmm0
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; X86-AVX1-NEXT: vpinsrd $3, %ecx, %xmm0, %xmm0
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; X86-AVX1-NEXT: vmovd %ebp, %xmm1
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; X86-AVX1-NEXT: vpinsrd $1, (%esp), %xmm1, %xmm1 # 4-byte Folded Reload
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; X86-AVX1-NEXT: vpinsrd $2, {{[0-9]+}}(%esp), %xmm1, %xmm1 # 4-byte Folded Reload
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; X86-AVX1-NEXT: vpinsrd $3, {{[0-9]+}}(%esp), %xmm1, %xmm1 # 4-byte Folded Reload
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; X86-AVX1-NEXT: vmovd {{[0-9]+}}(%esp), %xmm2 # 4-byte Folded Reload
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; X86-AVX1-NEXT: # xmm2 = mem[0],zero,zero,zero
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; X86-AVX1-NEXT: movl $8199, %eax # imm = 0x2007
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; X86-AVX1-NEXT: vmovd %eax, %xmm3
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; X86-AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [8199,8199,8199,8199]
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; X86-AVX1-NEXT: vpmaddwd %xmm4, %xmm0, %xmm0
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; X86-AVX1-NEXT: vpmaddwd %xmm4, %xmm1, %xmm1
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; X86-AVX1-NEXT: divl %ecx
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; X86-AVX1-NEXT: vpinsrd $3, %edx, %xmm2, %xmm0
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; X86-AVX1-NEXT: xorl %eax, %eax
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; X86-AVX1-NEXT: xorl %edx, %edx
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; X86-AVX1-NEXT: divl (%eax)
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; X86-AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [8199,8199,8199,8199]
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; X86-AVX1-NEXT: vpmaddwd %xmm2, %xmm0, %xmm0
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; X86-AVX1-NEXT: vpmaddwd %xmm2, %xmm1, %xmm1
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; X86-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; X86-AVX1-NEXT: vpmulld %xmm3, %xmm2, %xmm1
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; X86-AVX1-NEXT: vmovd %edx, %xmm1
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; X86-AVX1-NEXT: movl $8199, %eax # imm = 0x2007
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; X86-AVX1-NEXT: vmovd %eax, %xmm2
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; X86-AVX1-NEXT: vpmulld %xmm2, %xmm1, %xmm1
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; X86-AVX1-NEXT: vmovd %xmm1, (%eax)
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; X86-AVX1-NEXT: vmovaps %ymm0, (%eax)
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; X86-AVX1-NEXT: addl $16, %esp
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; X86-AVX1-NEXT: popl %esi
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; X86-AVX1-NEXT: popl %edi
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; X86-AVX1-NEXT: popl %ebx
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; X86-AVX1-NEXT: popl %ebp
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; X86-AVX1-NEXT: vzeroupper
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; X86-AVX1-NEXT: retl
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;
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@ -2421,77 +2399,63 @@ define void @PR34947() {
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;
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; X64-AVX1-LABEL: PR34947:
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; X64-AVX1: # %bb.0:
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; X64-AVX1-NEXT: pushq %rbp
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; X64-AVX1-NEXT: .cfi_def_cfa_offset 16
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; X64-AVX1-NEXT: pushq %rbx
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; X64-AVX1-NEXT: .cfi_def_cfa_offset 24
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; X64-AVX1-NEXT: .cfi_offset %rbx, -24
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; X64-AVX1-NEXT: .cfi_offset %rbp, -16
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; X64-AVX1-NEXT: vmovdqa (%rax), %ymm0
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; X64-AVX1-NEXT: xorl %eax, %eax
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; X64-AVX1-NEXT: xorl %edx, %edx
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; X64-AVX1-NEXT: divl (%rax)
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; X64-AVX1-NEXT: movl %edx, %r8d
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; X64-AVX1-NEXT: vpextrd $3, %xmm0, %ecx
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; X64-AVX1-NEXT: xorl %eax, %eax
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; X64-AVX1-NEXT: xorl %edx, %edx
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; X64-AVX1-NEXT: divl %ecx
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; X64-AVX1-NEXT: movl %edx, %r9d
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; X64-AVX1-NEXT: vpextrd $2, %xmm0, %ecx
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; X64-AVX1-NEXT: xorl %eax, %eax
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; X64-AVX1-NEXT: xorl %edx, %edx
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; X64-AVX1-NEXT: divl %ecx
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; X64-AVX1-NEXT: movl %edx, %r10d
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; X64-AVX1-NEXT: vpextrd $1, %xmm0, %ecx
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; X64-AVX1-NEXT: xorl %eax, %eax
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; X64-AVX1-NEXT: xorl %edx, %edx
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; X64-AVX1-NEXT: divl %ecx
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; X64-AVX1-NEXT: movl %edx, %r11d
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; X64-AVX1-NEXT: vmovd %xmm0, %ecx
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; X64-AVX1-NEXT: movl %edx, %ecx
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; X64-AVX1-NEXT: vmovd %xmm0, %esi
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; X64-AVX1-NEXT: xorl %eax, %eax
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; X64-AVX1-NEXT: xorl %edx, %edx
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; X64-AVX1-NEXT: divl %ecx
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; X64-AVX1-NEXT: movl %edx, %esi
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; X64-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
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; X64-AVX1-NEXT: vpextrd $3, %xmm0, %ecx
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; X64-AVX1-NEXT: xorl %eax, %eax
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; X64-AVX1-NEXT: xorl %edx, %edx
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; X64-AVX1-NEXT: divl %ecx
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; X64-AVX1-NEXT: movl %edx, %edi
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; X64-AVX1-NEXT: divl %esi
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; X64-AVX1-NEXT: vmovd %edx, %xmm1
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; X64-AVX1-NEXT: vpinsrd $1, %ecx, %xmm1, %xmm1
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; X64-AVX1-NEXT: vpextrd $2, %xmm0, %ecx
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; X64-AVX1-NEXT: xorl %eax, %eax
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; X64-AVX1-NEXT: xorl %edx, %edx
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; X64-AVX1-NEXT: divl %ecx
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; X64-AVX1-NEXT: vpinsrd $2, %edx, %xmm1, %xmm1
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; X64-AVX1-NEXT: vpextrd $3, %xmm0, %ecx
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; X64-AVX1-NEXT: xorl %eax, %eax
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; X64-AVX1-NEXT: xorl %edx, %edx
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; X64-AVX1-NEXT: divl %ecx
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; X64-AVX1-NEXT: vpinsrd $3, %edx, %xmm1, %xmm1
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; X64-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
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; X64-AVX1-NEXT: vpextrd $1, %xmm0, %ecx
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; X64-AVX1-NEXT: xorl %eax, %eax
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; X64-AVX1-NEXT: xorl %edx, %edx
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; X64-AVX1-NEXT: divl %ecx
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; X64-AVX1-NEXT: movl %edx, %ecx
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; X64-AVX1-NEXT: vpextrd $1, %xmm0, %ebx
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; X64-AVX1-NEXT: vmovd %xmm0, %esi
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; X64-AVX1-NEXT: xorl %eax, %eax
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; X64-AVX1-NEXT: xorl %edx, %edx
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; X64-AVX1-NEXT: divl %ebx
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; X64-AVX1-NEXT: movl %edx, %ebx
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; X64-AVX1-NEXT: vmovd %xmm0, %ebp
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; X64-AVX1-NEXT: divl %esi
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; X64-AVX1-NEXT: vmovd %edx, %xmm2
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; X64-AVX1-NEXT: vpinsrd $1, %ecx, %xmm2, %xmm2
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; X64-AVX1-NEXT: vpextrd $2, %xmm0, %ecx
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; X64-AVX1-NEXT: xorl %eax, %eax
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; X64-AVX1-NEXT: xorl %edx, %edx
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; X64-AVX1-NEXT: divl %ebp
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; X64-AVX1-NEXT: vmovd %edx, %xmm0
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; X64-AVX1-NEXT: vpinsrd $1, %ebx, %xmm0, %xmm0
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; X64-AVX1-NEXT: vpinsrd $2, %ecx, %xmm0, %xmm0
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; X64-AVX1-NEXT: vpinsrd $3, %edi, %xmm0, %xmm0
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; X64-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [8199,8199,8199,8199]
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; X64-AVX1-NEXT: vpmaddwd %xmm1, %xmm0, %xmm0
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; X64-AVX1-NEXT: vmovd %esi, %xmm2
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; X64-AVX1-NEXT: vpinsrd $1, %r11d, %xmm2, %xmm2
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; X64-AVX1-NEXT: vpinsrd $2, %r10d, %xmm2, %xmm2
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; X64-AVX1-NEXT: vpinsrd $3, %r9d, %xmm2, %xmm2
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; X64-AVX1-NEXT: vpmaddwd %xmm1, %xmm2, %xmm1
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; X64-AVX1-NEXT: divl %ecx
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; X64-AVX1-NEXT: vpinsrd $2, %edx, %xmm2, %xmm2
|
||||
; X64-AVX1-NEXT: vpextrd $3, %xmm0, %ecx
|
||||
; X64-AVX1-NEXT: xorl %eax, %eax
|
||||
; X64-AVX1-NEXT: xorl %edx, %edx
|
||||
; X64-AVX1-NEXT: divl %ecx
|
||||
; X64-AVX1-NEXT: vpinsrd $3, %edx, %xmm2, %xmm0
|
||||
; X64-AVX1-NEXT: xorl %eax, %eax
|
||||
; X64-AVX1-NEXT: xorl %edx, %edx
|
||||
; X64-AVX1-NEXT: divl (%rax)
|
||||
; X64-AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [8199,8199,8199,8199]
|
||||
; X64-AVX1-NEXT: vpmaddwd %xmm2, %xmm0, %xmm0
|
||||
; X64-AVX1-NEXT: vpmaddwd %xmm2, %xmm1, %xmm1
|
||||
; X64-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
|
||||
; X64-AVX1-NEXT: vmovd %r8d, %xmm1
|
||||
; X64-AVX1-NEXT: vmovd %edx, %xmm1
|
||||
; X64-AVX1-NEXT: movl $8199, %eax # imm = 0x2007
|
||||
; X64-AVX1-NEXT: vmovd %eax, %xmm2
|
||||
; X64-AVX1-NEXT: vpmulld %xmm2, %xmm1, %xmm1
|
||||
; X64-AVX1-NEXT: vmovd %xmm1, (%rax)
|
||||
; X64-AVX1-NEXT: vmovaps %ymm0, (%rax)
|
||||
; X64-AVX1-NEXT: popq %rbx
|
||||
; X64-AVX1-NEXT: popq %rbp
|
||||
; X64-AVX1-NEXT: vzeroupper
|
||||
; X64-AVX1-NEXT: retq
|
||||
;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user