From 4d92249e812474bc585b0ef8bc26558dfb87d567 Mon Sep 17 00:00:00 2001
From: Evandro Menezes <e.menezes@samsung.com>
Date: Tue, 12 Nov 2019 14:28:25 -0600
Subject: [PATCH] [AArch64] Update for Exynos

Fix the modeling for loads and stores using the register offset addresing mode.
---
 lib/Target/AArch64/AArch64SchedExynosM3.td | 18 ++++++++++++++----
 lib/Target/AArch64/AArch64SchedExynosM4.td | 18 ++++++++++++------
 2 files changed, 26 insertions(+), 10 deletions(-)

diff --git a/lib/Target/AArch64/AArch64SchedExynosM3.td b/lib/Target/AArch64/AArch64SchedExynosM3.td
index 569bdb5bafa..d1734c455b2 100644
--- a/lib/Target/AArch64/AArch64SchedExynosM3.td
+++ b/lib/Target/AArch64/AArch64SchedExynosM3.td
@@ -167,6 +167,8 @@ def M3WriteLH : SchedWriteRes<[]>        { let Latency = 5;
                                            let NumMicroOps = 0; }
 def M3WriteLX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M3WriteL5]>,
                                    SchedVar<NoSchedPred,         [M3WriteL4]>]>;
+def M3WriteLY : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M3WriteLE]>,
+                                   SchedVar<NoSchedPred,         [M3WriteL5]>]>;
 
 def M3WriteS1 : SchedWriteRes<[M3UnitS]>   { let Latency = 1; }
 def M3WriteSA : SchedWriteRes<[M3UnitA,
@@ -176,6 +178,12 @@ def M3WriteSA : SchedWriteRes<[M3UnitA,
 def M3WriteSB : SchedWriteRes<[M3UnitA,
                                M3UnitS]>   { let Latency = 2;
                                              let NumMicroOps = 2; }
+def M3WriteSC : SchedWriteRes<[M3UnitA,
+                               M3UnitS,
+                               M3UnitFST]> { let Latency = 1;
+                                             let NumMicroOps = 2; }
+def M3WriteSY : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M3WriteSA]>,
+                                   SchedVar<NoSchedPred,         [WriteVST]>]>;
 
 def M3ReadAdrBase : SchedReadVariant<[SchedVar<ExynosScaledIdxPred, [ReadDefault]>,
                                       SchedVar<NoSchedPred,         [ReadDefault]>]>;
@@ -559,7 +567,7 @@ def : InstRW<[M3WriteLE,
               ReadAdrBase], (instregex "^LDR[BDHS]roW")>;
 def : InstRW<[WriteVLD,
               ReadAdrBase], (instregex "^LDR[BDHS]roX")>;
-def : InstRW<[M3WriteLE,
+def : InstRW<[M3WriteLY,
               ReadAdrBase], (instregex "^LDRQro[WX]")>;
 def : InstRW<[WriteVLD,
               M3WriteLH],   (instregex "^LDN?P[DS]i")>;
@@ -579,14 +587,16 @@ def : InstRW<[WriteVST,
 def : InstRW<[WriteVST],    (instregex "^STR[BDHSQ]ui")>;
 def : InstRW<[M3WriteSA,
               ReadAdrBase], (instregex "^STR[BDHS]roW")>;
+def : InstRW<[M3WriteSA,
+              ReadAdrBase], (instregex "^STRQroW")>;
 def : InstRW<[WriteVST,
               ReadAdrBase], (instregex "^STR[BDHS]roX")>;
-def : InstRW<[M3WriteSA,
-              ReadAdrBase], (instregex "^STRQro[WX]")>;
+def : InstRW<[M3WriteSY,
+              ReadAdrBase], (instregex "^STRQroX")>;
 def : InstRW<[WriteVST],    (instregex "^STN?P[DSQ]i")>;
 def : InstRW<[WriteVST,
               WriteAdr],    (instregex "^STP[DS](post|pre)")>;
-def : InstRW<[M3WriteSA,
+def : InstRW<[M3WriteSC,
               WriteAdr],    (instregex "^STPQ(post|pre)")>;
 
 // ASIMD instructions.
diff --git a/lib/Target/AArch64/AArch64SchedExynosM4.td b/lib/Target/AArch64/AArch64SchedExynosM4.td
index caac07b7eab..d2284f9fa0b 100644
--- a/lib/Target/AArch64/AArch64SchedExynosM4.td
+++ b/lib/Target/AArch64/AArch64SchedExynosM4.td
@@ -202,8 +202,10 @@ def M4WriteLE : SchedWriteRes<[M4UnitA,
                                            let NumMicroOps = 2; }
 def M4WriteLH : SchedWriteRes<[]>        { let Latency = 5;
                                            let NumMicroOps = 0; }
-def M4WriteLX : SchedWriteVariant<[SchedVar<ScaledIdxPred, [M4WriteL5]>,
-                                   SchedVar<NoSchedPred,   [M4WriteL4]>]>;
+def M4WriteLX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M4WriteL5]>,
+                                   SchedVar<NoSchedPred,         [M4WriteL4]>]>;
+def M4WriteLY : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M4WriteLE]>,
+                                   SchedVar<NoSchedPred,         [M4WriteL5]>]>;
 
 def M4WriteS1 : SchedWriteRes<[M4UnitS]>  { let Latency = 1; }
 def M4WriteSA : SchedWriteRes<[M4UnitS0]> { let Latency = 3; }
@@ -461,6 +463,8 @@ def M4WriteVSTI    : SchedWriteRes<[M4UnitNSHF,
                                                     let NumMicroOps = 5;
                                                     let ResourceCycles = [1, 1, 1, 1, 2, 1, 2, 1, 2, 1, 2, 1]; }
 def M4WriteVSTJ    : SchedWriteRes<[M4UnitA,
+                                    M4UnitS,
+                                    M4UnitFST,
                                     M4UnitS,
                                     M4UnitFST]>   { let Latency = 1;
                                                     let NumMicroOps = 2; }
@@ -476,6 +480,8 @@ def M4WriteVSTL    : SchedWriteRes<[M4UnitNSHF,
                                     M4UnitFST]>   { let Latency = 4;
                                                     let NumMicroOps = 4;
                                                     let ResourceCycles = [1, 1, 2, 1, 2, 1]; }
+def M4WriteVSTY    : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M4WriteVSTK]>,
+                                        SchedVar<NoSchedPred,         [WriteVST]>]>;
 
 // Special cases.
 def M4WriteCOPY    : SchedWriteVariant<[SchedVar<ExynosFPPred, [M4WriteNALU1]>,
@@ -676,7 +682,7 @@ def : InstRW<[M4WriteLE,
               ReadAdrBase], (instregex "^LDR[BHSDQ]roW")>;
 def : InstRW<[WriteVLD,
               ReadAdrBase], (instregex "^LDR[BHSD]roX")>;
-def : InstRW<[M4WriteLE,
+def : InstRW<[M4WriteLY,
               ReadAdrBase], (instrs LDRQroX)>;
 def : InstRW<[WriteVLD,
               M4WriteLH],   (instregex "^LDN?P[SD]i")>;
@@ -700,16 +706,16 @@ def : InstRW<[WriteVST],    (instregex "^STUR[BHSDQ]i")>;
 def : InstRW<[WriteVST,
               WriteAdr],    (instregex "^STR[BHSDQ](post|pre)")>;
 def : InstRW<[WriteVST],    (instregex "^STR[BHSDQ]ui")>;
-def : InstRW<[M4WriteVSTJ,
+def : InstRW<[M4WriteVSTK,
               ReadAdrBase], (instregex "^STR[BHSD]roW")>;
 def : InstRW<[M4WriteVSTK,
               ReadAdrBase], (instrs STRQroW)>;
 def : InstRW<[WriteVST,
               ReadAdrBase], (instregex "^STR[BHSD]roX")>;
-def : InstRW<[M4WriteVSTK,
+def : InstRW<[M4WriteVSTY,
               ReadAdrBase], (instrs STRQroX)>;
 def : InstRW<[WriteVST],    (instregex "^STN?P[SD]i")>;
-def : InstRW<[M4WriteVSTA], (instregex "^STN?PQi")>;
+def : InstRW<[M4WriteVSTJ], (instregex "^STN?PQi")>;
 def : InstRW<[WriteVST,
               WriteAdr],    (instregex "^STP[SD](post|pre)")>;
 def : InstRW<[M4WriteVSTJ,