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ARM: FMA is legal only if VFP4 is available.
rdar://13306723 llvm-svn: 176212
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@ -554,6 +554,12 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
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setOperationAction(ISD::CTPOP, MVT::v4i16, Custom);
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setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
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// NEON only has FMA instructions as of VFP4.
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if (!Subtarget->hasVFP4()) {
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setOperationAction(ISD::FMA, MVT::v2f32, Expand);
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setOperationAction(ISD::FMA, MVT::v4f32, Expand);
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}
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setTargetDAGCombine(ISD::INTRINSIC_VOID);
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setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
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setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
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31
test/CodeGen/ARM/2013-02-27-expand-vfma.ll
Normal file
31
test/CodeGen/ARM/2013-02-27-expand-vfma.ll
Normal file
@ -0,0 +1,31 @@
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; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s
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; RUN: llc < %s -mtriple=armv7s-apple-darwin | FileCheck %s -check-prefix=VFP4
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define <4 x float> @muladd(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind {
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; CHECK: muladd:
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; CHECK: fmaf
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; CHECK: fmaf
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; CHECK: fmaf
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; CHECK: fmaf
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; CHECK-NOT: fmaf
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; CHECK-VFP4: vfma.f32
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%tmp = tail call <4 x float> @llvm.fma.v4f32(<4 x float> %b, <4 x float> %c, <4 x float> %a) #2
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ret <4 x float> %tmp
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}
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declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) #1
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define <2 x float> @muladd2(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind {
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; CHECK: muladd2:
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; CHECK: fmaf
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; CHECK: fmaf
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; CHECK-NOT: fmaf
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; CHECK-VFP4: vfma.f32
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%tmp = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %b, <2 x float> %c, <2 x float> %a) #2
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ret <2 x float> %tmp
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}
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declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>) #1
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