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[ARM] Implement isLoad/StoreFromStackSlot for MVE stack stores accesses

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This implements the isLoadFromStackSlot and isStoreToStackSlot for MVE
MVE_VSTRWU32 and MVE_VLDRWU32 functions. They behave the same as many
other loads/stores, expecting a FI in Op1 and zero offset in Op2. At the
same time this alters VLDR_P0_off and VSTR_P0_off to use the same code
too, as they too should be returning VPR in Op0, take a FI in Op1 and
zero offset in Op2.

Differential Revision: https://reviews.llvm.org/D106797
This commit is contained in:
David Green 2021-07-27 09:11:58 +01:00
parent 565fcd6a48
commit 4d9d8789ad
2 changed files with 6 additions and 20 deletions
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18
lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -1306,19 +1306,14 @@ unsigned ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
case ARM::tSTRspi:
case ARM::VSTRD:
case ARM::VSTRS:
case ARM::VSTR_P0_off:
case ARM::MVE_VSTRWU32:
if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
MI.getOperand(2).getImm() == 0) {
FrameIndex = MI.getOperand(1).getIndex();
return MI.getOperand(0).getReg();
}
break;
case ARM::VSTR_P0_off:
if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
MI.getOperand(1).getImm() == 0) {
FrameIndex = MI.getOperand(0).getIndex();
return ARM::P0;
}
break;
case ARM::VST1q64:
case ARM::VST1d64TPseudo:
case ARM::VST1d64QPseudo:
@ -1543,19 +1538,14 @@ unsigned ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
case ARM::tLDRspi:
case ARM::VLDRD:
case ARM::VLDRS:
case ARM::VLDR_P0_off:
case ARM::MVE_VLDRWU32:
if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
MI.getOperand(2).getImm() == 0) {
FrameIndex = MI.getOperand(1).getIndex();
return MI.getOperand(0).getReg();
}
break;
case ARM::VLDR_P0_off:
if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
MI.getOperand(1).getImm() == 0) {
FrameIndex = MI.getOperand(0).getIndex();
return ARM::P0;
}
break;
case ARM::VLD1q64:
case ARM::VLD1d8TPseudo:
case ARM::VLD1d16TPseudo:

8
test/CodeGen/Thumb2/mve-gather-increment.ll
View File

@ -967,10 +967,11 @@ define arm_aapcs_vfpcc void @gather_inc_v16i8_complex(i8* noalias nocapture read
; CHECK-NEXT: vstrw.32 q0, [sp, #168] @ 16-byte Spill
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: vmov q3, q5
; CHECK-NEXT: vstrw.32 q1, [sp, #296] @ 16-byte Spill
; CHECK-NEXT: vadd.i32 q1, q1, r0
; CHECK-NEXT: vldrw.u32 q0, [sp, #248] @ 16-byte Reload
; CHECK-NEXT: vldrw.u32 q3, [sp, #216] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q5, [sp, #120] @ 16-byte Spill
; CHECK-NEXT: vadd.i32 q0, q0, r0
; CHECK-NEXT: subs.w r11, r11, #16
; CHECK-NEXT: ldrb.w r9, [r1]
; CHECK-NEXT: vmov r1, r3, d14
@ -997,9 +998,6 @@ define arm_aapcs_vfpcc void @gather_inc_v16i8_complex(i8* noalias nocapture read
; CHECK-NEXT: vmov.8 q6[5], r7
; CHECK-NEXT: ldrb r4, [r1]
; CHECK-NEXT: vmov r1, r5, d3
; CHECK-NEXT: vldrw.u32 q1, [sp, #248] @ 16-byte Reload
; CHECK-NEXT: vadd.i32 q0, q1, r0
; CHECK-NEXT: vstrw.32 q1, [sp, #248] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q1, [sp, #232] @ 16-byte Reload
; CHECK-NEXT: ldrb.w r12, [r1]
; CHECK-NEXT: vmov r1, r3, d9
@ -1016,7 +1014,6 @@ define arm_aapcs_vfpcc void @gather_inc_v16i8_complex(i8* noalias nocapture read
; CHECK-NEXT: vmov r1, r3, d1
; CHECK-NEXT: vldrw.u32 q0, [sp, #264] @ 16-byte Reload
; CHECK-NEXT: vmov.8 q7[5], r7
; CHECK-NEXT: vstrw.32 q0, [sp, #264] @ 16-byte Spill
; CHECK-NEXT: vadd.i32 q0, q0, r0
; CHECK-NEXT: ldrb r1, [r1]
; CHECK-NEXT: ldrb r3, [r3]
@ -1027,7 +1024,6 @@ define arm_aapcs_vfpcc void @gather_inc_v16i8_complex(i8* noalias nocapture read
; CHECK-NEXT: vmov r3, lr, d1
; CHECK-NEXT: vldrw.u32 q0, [sp, #280] @ 16-byte Reload
; CHECK-NEXT: vmov.8 q7[8], r1
; CHECK-NEXT: vstrw.32 q0, [sp, #280] @ 16-byte Spill
; CHECK-NEXT: vadd.i32 q0, q0, r0
; CHECK-NEXT: vmov.8 q7[9], r4
; CHECK-NEXT: vmov r4, r1, d0