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Revert "[AVR] Add the branch selection pass from the GitHub repository"
This reverts commit 602ef067c1d58ecb425d061f35f2bc4c7e92f4f3. llvm-svn: 307111
This commit is contained in:
Dylan McKay
parent
590d049bd1
commit
4df9fae587
@ -1,262 +0,0 @@
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//===-- AVRBranchSelector.cpp - Emit long conditional branches ------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a pass that scans a machine function to determine which
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// conditional branches need more than 8 bits of displacement to reach their
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// target basic block. It does this in two passes; a calculation of basic block
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// positions pass, and a branch pseudo op to machine branch opcode pass. This
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// pass should be run last, just before the assembly printer.
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//
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//===----------------------------------------------------------------------===//
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#include "AVR.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "AVRInstrInfo.h"
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#include "AVRTargetMachine.h"
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#include "MCTargetDesc/AVRMCTargetDesc.h"
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#define DEBUG_TYPE "avr-branch-select"
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STATISTIC(NumExpanded, "Number of branches expanded to long format");
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namespace llvm {
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/// Ensures branch targets can fit inside the instruction
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/// they reside in.
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///
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/// If a branch target is too large for the instruction it
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/// is being used with, this pass replaces it with a larger,
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/// equivalent instruction which can fit the target.
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class AVRBSel : public MachineFunctionPass {
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public:
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static char ID;
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explicit AVRBSel() : MachineFunctionPass(ID) {}
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override { return "AVR Branch Selector"; }
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protected:
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/// Measure and sum the size of all basic blocks in a function.
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unsigned calculateFunctionSize(const MachineFunction &MF);
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private:
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/// The sizes of the basic blocks in the function.
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std::vector<unsigned> BlockSizes;
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};
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char AVRBSel::ID = 0;
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/// Checks whether the passed opcode is a conditional branch.
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static bool isConditionalBranch(int Opcode) {
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switch (Opcode) {
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default:
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return false;
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case AVR::BREQk:
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case AVR::BRNEk:
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case AVR::BRSHk:
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case AVR::BRLOk:
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case AVR::BRMIk:
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case AVR::BRPLk:
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case AVR::BRGEk:
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case AVR::BRLTk:
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return true;
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}
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}
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unsigned AVRBSel::calculateFunctionSize(const MachineFunction &MF) {
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const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
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const AVRInstrInfo &TII = *STI.getInstrInfo();
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unsigned FuncSize = 0;
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for (const MachineBasicBlock &MBB : MF) {
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unsigned BlockSize = 0;
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for (const MachineInstr &MI : MBB) {
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BlockSize += TII.getInstSizeInBytes(MI);
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}
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BlockSizes[MBB.getNumber()] = BlockSize;
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FuncSize += BlockSize;
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}
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assert(FuncSize % 2 == 0 && "function should have an even number of bytes");
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return FuncSize;
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}
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bool AVRBSel::runOnMachineFunction(MachineFunction &MF) {
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const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
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const AVRInstrInfo &TII = *STI.getInstrInfo();
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// Give the blocks of the function a dense, in-order, numbering.
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MF.RenumberBlocks();
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BlockSizes.resize(MF.getNumBlockIDs());
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unsigned FuncSize = calculateFunctionSize(MF);
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// If the entire function is smaller than the displacement of a branch field,
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// we know we don't need to shrink any branches in this function. This is a
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// common case.
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if (isUInt<7>(FuncSize)) {
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BlockSizes.clear();
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return false;
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}
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// For each conditional branch, if the offset to its destination is larger
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// than the offset field allows, transform it into a long or a huge branch
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// sequence like this:
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// -short branch:
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// brCC MBB
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// -long branch:
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// br!CC $PC+2
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// rjmp MBB
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// -huge branch:
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// br!CC $PC+4
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// jmp MBB
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bool MadeChange = true;
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while (MadeChange) {
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// Iteratively expand branches until we reach a fixed point.
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MadeChange = false;
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for (MachineBasicBlock &MBB : MF) {
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unsigned MBBStartOffset = 0;
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for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E;
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++I) {
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int Opc = I->getOpcode();
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if ((!isConditionalBranch(Opc) || I->getOperand(0).isImm()) &&
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(Opc != AVR::RJMPk)) {
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MBBStartOffset += TII.getInstSizeInBytes(*I);
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continue;
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}
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// Determine the offset from the current branch to the destination
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// block.
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MachineBasicBlock &Dest = *I->getOperand(0).getMBB();
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assert(Dest.getNumber() >= 0 &&
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"Destination basic block isn't in a function");
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int BranchSize;
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if (Dest.getNumber() <= MBB.getNumber()) {
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// If this is a backwards branch, the delta is the offset from the
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// start of this block to this branch, plus the sizes of all blocks
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// from this block to the dest.
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BranchSize = MBBStartOffset;
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for (unsigned i = Dest.getNumber(), e = MBB.getNumber(); i != e;
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++i) {
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BranchSize += BlockSizes[i];
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}
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// Set the size of backwards branches to a negative value.
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BranchSize = -BranchSize;
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} else {
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// Otherwise, add the size of the blocks between this block and the
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// dest to the number of bytes left in this block.
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BranchSize = -MBBStartOffset;
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for (unsigned i = MBB.getNumber(), e = Dest.getNumber(); i != e;
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++i) {
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BranchSize += BlockSizes[i];
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}
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}
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if (isConditionalBranch(Opc))
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BranchSize -= 2; // take the size of the current instruction.
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assert(BranchSize % 2 == 0 &&
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"BranchSize should have an even number of bytes");
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// If this branch is in range, ignore it.
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if ((isConditionalBranch(Opc) && isInt<8>(BranchSize)) ||
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(Opc == AVR::RJMPk && isInt<13>(BranchSize))) {
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MBBStartOffset += 2;
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continue;
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}
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// Otherwise, we have to expand it to a long branch.
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unsigned NewSize;
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int UncondOpc;
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MachineInstr &OldBranch = *I;
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DebugLoc DL = OldBranch.getDebugLoc();
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if (Opc == AVR::RJMPk) {
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// Replace this instruction with a jmp which has a size of 4 bytes.
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NewSize = 4;
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UncondOpc = AVR::JMPk;
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// We may be converting a conditional long jump to a huge one, if this
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// is the case, update the $PC+2 operand in brCC to $PC+4.
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// Skip the check when this instruction is the first inside the BB.
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if (I != MBB.begin()) {
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MachineInstr &PI = *std::prev(I);
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if (isConditionalBranch(PI.getOpcode()) &&
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PI.getOperand(0).isImm() &&
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PI.getOperand(0).getImm() == 2) {
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PI.getOperand(0).setImm(4);
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}
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}
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} else {
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assert(isConditionalBranch(Opc) &&
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"opcode should be a conditional branch");
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unsigned BrCCOffs;
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// Determine if we can reach the destination block with a rjmp,
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// otherwise a jmp instruction is needed.
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if (isInt<13>(BranchSize)) {
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NewSize = 4;
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BrCCOffs = 2;
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UncondOpc = AVR::RJMPk;
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} else {
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NewSize = 6;
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BrCCOffs = 4;
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UncondOpc = AVR::JMPk;
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}
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AVRCC::CondCodes OCC =
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TII.getOppositeCondition(TII.getCondFromBranchOpc(Opc));
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// Jump over the uncond branch inst (i.e. $+2) on opposite condition.
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BuildMI(MBB, I, DL, TII.getBrCond(OCC)).addImm(BrCCOffs);
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}
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// Uncond branch to the real destination.
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I = BuildMI(MBB, I, DL, TII.get(UncondOpc)).addMBB(&Dest);
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// Remove the old branch from the function.
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OldBranch.eraseFromParent();
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// Remember that this instruction is NewSize bytes, increase the size of
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// the block by NewSize-2, remember to iterate.
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BlockSizes[MBB.getNumber()] += NewSize - 2;
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MBBStartOffset += NewSize;
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++NumExpanded;
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MadeChange = true;
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}
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}
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}
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BlockSizes.clear();
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return true;
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}
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FunctionPass *createAVRBranchSelectionPass() { return new AVRBSel(); }
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} // end of namespace llvm
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@ -67,7 +67,6 @@ public:
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bool addInstSelector() override;
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bool addInstSelector() override;
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void addPreSched2() override;
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void addPreSched2() override;
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void addPreRegAlloc() override;
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void addPreRegAlloc() override;
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void addPreEmitPass() override;
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};
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};
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} // namespace
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} // namespace
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@ -116,9 +115,4 @@ void AVRPassConfig::addPreSched2() {
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addPass(createAVRExpandPseudoPass());
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addPass(createAVRExpandPseudoPass());
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}
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}
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void AVRPassConfig::addPreEmitPass() {
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// Must run branch selection immediately preceding the asm printer.
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addPass(createAVRBranchSelectionPass());
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}
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} // end of namespace llvm
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} // end of namespace llvm
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@ -18,7 +18,6 @@ add_public_tablegen_target(AVRCommonTableGen)
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add_llvm_target(AVRCodeGen
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add_llvm_target(AVRCodeGen
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AVRAsmPrinter.cpp
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AVRAsmPrinter.cpp
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AVRBranchSelector.cpp
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AVRExpandPseudoInsts.cpp
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AVRExpandPseudoInsts.cpp
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AVRFrameLowering.cpp
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AVRFrameLowering.cpp
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AVRInstrInfo.cpp
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AVRInstrInfo.cpp
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@ -10,7 +10,7 @@ declare i8 @llvm.ctlz.i8(i8)
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; CHECK-LABEL: count_leading_zeros:
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; CHECK-LABEL: count_leading_zeros:
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; CHECK: cpi [[RESULT:r[0-9]+]], 0
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; CHECK: cpi [[RESULT:r[0-9]+]], 0
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; CHECK: breq LBB0_2
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; CHECK: breq LBB0_1
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; CHECK: mov [[SCRATCH:r[0-9]+]], {{.*}}[[RESULT]]
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; CHECK: mov [[SCRATCH:r[0-9]+]], {{.*}}[[RESULT]]
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; CHECK: lsr {{.*}}[[SCRATCH]]
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; CHECK: lsr {{.*}}[[SCRATCH]]
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; CHECK: or {{.*}}[[SCRATCH]], {{.*}}[[RESULT]]
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; CHECK: or {{.*}}[[SCRATCH]], {{.*}}[[RESULT]]
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@ -43,6 +43,6 @@ declare i8 @llvm.ctlz.i8(i8)
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; CHECK: add {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
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; CHECK: add {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
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; CHECK: andi {{.*}}[[RESULT]], 15
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; CHECK: andi {{.*}}[[RESULT]], 15
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; CHECK: ret
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; CHECK: ret
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; CHECK: LBB0_2:
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; CHECK: LBB0_1:
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; CHECK: ldi {{.*}}[[RESULT]], 8
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; CHECK: ldi {{.*}}[[RESULT]], 8
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; CHECK: ret
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; CHECK: ret
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@ -10,7 +10,7 @@ declare i8 @llvm.cttz.i8(i8)
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; CHECK-LABEL: count_trailing_zeros:
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; CHECK-LABEL: count_trailing_zeros:
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; CHECK: cpi [[RESULT:r[0-9]+]], 0
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; CHECK: cpi [[RESULT:r[0-9]+]], 0
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; CHECK: breq LBB0_2
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; CHECK: breq LBB0_1
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; CHECK: mov [[SCRATCH:r[0-9]+]], {{.*}}[[RESULT]]
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; CHECK: mov [[SCRATCH:r[0-9]+]], {{.*}}[[RESULT]]
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; CHECK: dec {{.*}}[[SCRATCH]]
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; CHECK: dec {{.*}}[[SCRATCH]]
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; CHECK: com {{.*}}[[RESULT]]
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; CHECK: com {{.*}}[[RESULT]]
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@ -34,7 +34,7 @@ declare i8 @llvm.cttz.i8(i8)
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; CHECK: andi {{.*}}[[SCRATCH]], 15
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; CHECK: andi {{.*}}[[SCRATCH]], 15
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; CHECK: mov {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
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; CHECK: mov {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
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; CHECK: ret
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; CHECK: ret
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; CHECK: LBB0_2:
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; CHECK: LBB0_1:
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; CHECK: ldi {{.*}}[[SCRATCH]], 8
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; CHECK: ldi {{.*}}[[SCRATCH]], 8
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; CHECK: mov {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
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; CHECK: mov {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
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; CHECK: ret
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; CHECK: ret
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@ -8,9 +8,9 @@ define internal fastcc void @loopy() {
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;
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;
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; https://github.com/avr-rust/rust/issues/49
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; https://github.com/avr-rust/rust/issues/49
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; CHECK: LBB0_{{[0-9]+}}:
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; CHECK: LBB0_1:
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; CHECK: LBB0_{{[0-9]+}}:
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; CHECK: LBB0_2:
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; CHECK-NOT: LBB0_{{[0-9]+}}:
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; CHECK-NOT: LBB0_3:
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start:
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start:
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br label %bb7.preheader
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br label %bb7.preheader
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