From 4eae2fc3adae98160ff8cce2b5216527515f86b2 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Fri, 25 Oct 2002 23:00:40 +0000 Subject: [PATCH] Initial checkin of target support for X86 backend. llvm-svn: 4287 --- include/llvm/Target/MInstructionInfo.h | 85 +++++++++++++++++++++++++ include/llvm/Target/MRegisterInfo.h | 86 ++++++++++++++++++++++++++ 2 files changed, 171 insertions(+) create mode 100644 include/llvm/Target/MInstructionInfo.h create mode 100644 include/llvm/Target/MRegisterInfo.h diff --git a/include/llvm/Target/MInstructionInfo.h b/include/llvm/Target/MInstructionInfo.h new file mode 100644 index 00000000000..e8eb750f1c7 --- /dev/null +++ b/include/llvm/Target/MInstructionInfo.h @@ -0,0 +1,85 @@ +//===- Target/MInstructionInfo.h - Target Instruction Information -*-C++-*-===// +// +// MInstruction's are completely generic instructions that provide very little +// interpretation upon their arguments and sementics. This file defines an +// interface that should be used to get information about the semantics of the +// actual instructions. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CODEGEN_MINSTRUCTIONINFO_H +#define LLVM_CODEGEN_MINSTRUCTIONINFO_H + +#include +#include +class MInstruction; +class MRegisterInfo; + +/// MInstructionDesc - This record contains all of the information known about a +/// particular instruction. Note that several instructions with the same +/// mnemonic may be represented in the target machine as different instructions. +/// +struct MInstructionDesc { + const char *Name; // Assembly language mnemonic for the instruction. + unsigned Flags; // Flags identifying inst properties (defined below) + unsigned TSFlags; // Target Specific Flags +}; + +/// MIF namespace - This namespace contains flags that pertain to machine +/// instructions +/// +namespace MIF { + enum { + // Memory flags... + LOAD = 1 << 0, // This instruction loads from memory + STORE = 1 << 1, // This instruction stores to memory + + // Control flow flags... + CALL = 1 << 2, // This instruction calls another function + RET = 1 << 3, // This instruction returns from function + BRANCH = 1 << 4, // This instruction is a branch + }; +}; + +/// MInstructionInfo base class - We assume that the target defines a static +/// array of MInstructionDesc objects that represent all of the machine +/// instructions that the target has. As such, we simply have to track a +/// pointer to this array so that we can turn an instruction opcode into an +/// instruction descriptor. +/// +class MInstructionInfo { + const MInstructionDesc *Desc; // Pointer to the descriptor array + unsigned NumInstructions; // Number of entries in the array +protected: + MInstructionInfo(const MInstructionDesc *D, unsigned NI) + : Desc(D), NumInstructions(NI) {} +public: + + enum { // Target independant constants + PHIOpcode = 0, /// Opcode for PHI instruction + NoOpOpcode = 1, /// Opcode for noop instruction + }; + + /// getRegisterInfo - MInstructionInfo is a superset of MRegister info. As + /// such, whenever a client has an instance of instruction info, it should + /// always be able to get register info as well (through this method). + /// + virtual const MRegisterInfo &getRegisterInfo() const = 0; + + const MInstructionDesc &operator[](unsigned Opcode) const { + assert(Opcode < NumInstructions && + "Attempting to access record for invalid opcode!"); + return Desc[Opcode]; + } + + /// Provide a get method, equivalent to [], but more useful if we have a + /// pointer to this object. + const MInstructionDesc &get(unsigned Opcode) const { + return operator[](Opcode); + } + + virtual void print(const MInstruction *MI, std::ostream &O) const = 0; + +}; + +#endif diff --git a/include/llvm/Target/MRegisterInfo.h b/include/llvm/Target/MRegisterInfo.h new file mode 100644 index 00000000000..99247cf1966 --- /dev/null +++ b/include/llvm/Target/MRegisterInfo.h @@ -0,0 +1,86 @@ +//===- Target/MRegisterInfo.h - Target Register Information -------*-C++-*-===// +// +// This file describes an abstract interface used to get information about a +// target machines register file. This information is used for a variety of +// purposed, especially register allocation. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CODEGEN_MREGISTERINFO_H +#define LLVM_CODEGEN_MREGISTERINFO_H + +#include + +/// MRegisterDesc - This record contains all of the information known about a +/// particular register. +/// +struct MRegisterDesc { + const char *Name; // Assembly language name for the register + unsigned Flags; // Flags identifying register properties (defined below) + unsigned TSFlags; // Target Specific Flags +}; + +/// MRF namespace - This namespace contains flags that pertain to machine +/// registers +/// +namespace MRF { // MRF = Machine Register Flags + enum { + INT8 = 1 << 0, // This is an 8 bit integer register + INT16 = 1 << 1, // This is a 16 bit integer register + INT32 = 1 << 2, // This is a 32 bit integer register + INT64 = 1 << 3, // This is a 64 bit integer register + INT128 = 1 << 4, // This is a 128 bit integer register + + FP32 = 1 << 5, // This is a 32 bit floating point register + FP64 = 1 << 6, // This is a 64 bit floating point register + FP80 = 1 << 7, // This is a 80 bit floating point register + FP128 = 1 << 8, // This is a 128 bit floating point register + }; +}; + +/// MRegisterInfo base class - We assume that the target defines a static array +/// of MRegisterDesc objects that represent all of the machine registers that +/// the target has. As such, we simply have to track a pointer to this array so +/// that we can turn register number into a register descriptor. +/// +class MRegisterInfo { + const MRegisterDesc *Desc; // Pointer to the descriptor array + unsigned NumRegs; // Number of entries in the array +protected: + MRegisterInfo(const MRegisterDesc *D, unsigned NR) : Desc(D), NumRegs(NR) {} +public: + + enum { // Define some target independant constants + /// NoRegister - This 'hard' register is a 'noop' register for all backends. + /// This is used as the destination register for instructions that do not + /// produce a value. Some frontends may use this as an operand register to + /// mean special things, for example, the Sparc backend uses R0 to mean %g0 + /// which always PRODUCES the value 0. The X86 backend does not use this + /// value as an operand register. + /// + NoRegister = 0, + + /// FirstVirtualRegister - This is the first register number that is + /// considered to be a 'virtual' register, which is part of the SSA + /// namespace. This must be the same for all targets, which means that each + /// target is limited to 1024 registers. + /// + FirstVirtualRegister = 1024, + }; + + const MRegisterDesc &operator[](unsigned RegNo) const { + assert(RegNo < NumRegs && + "Attempting to access record for invalid register number!"); + return Desc[RegNo]; + } + + /// Provide a get method, equivalent to [], but more useful if we have a + /// pointer to this object. + /// + const MRegisterDesc &get(unsigned RegNo) const { return operator[](RegNo); } + + // This will eventually get some virtual methods... + +}; + +#endif