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[SystemZ] Bugfix in SystemZTargetLowering::combineIntDIVREM()

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Make sure to not unroll a vector division/remainder (with a constant splat
divisor) after type legalization, since the scalar type may then be illegal.

Review: Ulrich Weigand
https://reviews.llvm.org/D62036

llvm-svn: 360965
This commit is contained in:
Jonas Paulsson 2019-05-17 00:50:35 +00:00
parent 1c61494df7
commit 4eafdd14d1
2 changed files with 14 additions and 1 deletions
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2
lib/Target/SystemZ/SystemZISelLowering.cpp
View File

@ -5841,7 +5841,7 @@ SDValue SystemZTargetLowering::combineIntDIVREM(
// since it is not Legal but Custom it can only happen before
// legalization. Therefore we must scalarize this early before Combine
// 1. For widened vectors, this is already the result of type legalization.
if (VT.isVector() && isTypeLegal(VT) &&
if (DCI.Level == BeforeLegalizeTypes && VT.isVector() && isTypeLegal(VT) &&
DAG.isConstantIntBuildVectorOrConstantInt(N->getOperand(1)))
return DAG.UnrollVectorOp(N);
return SDValue();

13
test/CodeGen/SystemZ/vec-rem.ll Normal file
View File

@ -0,0 +1,13 @@
; Verify that we do not create illegal scalar urems after type legalization.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13
define <16 x i8> @main(i16 %arg) {
bb:
%tmp6 = insertelement <16 x i16> undef, i16 %arg, i32 0
%tmp7 = shufflevector <16 x i16> %tmp6, <16 x i16> undef, <16 x i32> zeroinitializer
%tmp8 = insertelement <16 x i8> <i8 undef, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, i8 undef, i32 0
%tmp11 = urem <16 x i16> %tmp7, <i16 29265, i16 29265, i16 29265, i16 29265, i16 29265, i16 29265, i16 29265, i16 29265, i16 29265, i16 29265, i16 29265, i16 29265, i16 29265, i16 29265, i16 29265, i16 29265>
%tmp12 = trunc <16 x i16> %tmp11 to <16 x i8>
ret <16 x i8> %tmp12
}