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Recognise 32-bit ror-based bswap implementation used by uclibc
llvm-svn: 119007
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@ -11451,6 +11451,35 @@ bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
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}
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}
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break;
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break;
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case 3:
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case 3:
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if (CI->getType()->isIntegerTy(32) &&
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IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
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SmallVector<StringRef, 4> Words;
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SplitString(AsmPieces[0], Words, " \t,");
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if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
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Words[2] == "${0:w}") {
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Words.clear();
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SplitString(AsmPieces[1], Words, " \t,");
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if (Words.size() == 3 && Words[0] == "rorl" && Words[1] == "$$16" &&
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Words[2] == "$0") {
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Words.clear();
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SplitString(AsmPieces[2], Words, " \t,");
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if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
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Words[2] == "${0:w}") {
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AsmPieces.clear();
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const std::string &Constraints = IA->getConstraintString();
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SplitString(StringRef(Constraints).substr(5), AsmPieces, ",");
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std::sort(AsmPieces.begin(), AsmPieces.end());
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if (AsmPieces.size() == 4 &&
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AsmPieces[0] == "~{cc}" &&
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AsmPieces[1] == "~{dirflag}" &&
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AsmPieces[2] == "~{flags}" &&
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AsmPieces[3] == "~{fpsr}") {
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return LowerToBSwap(CI);
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}
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}
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}
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}
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}
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if (CI->getType()->isIntegerTy(64) &&
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if (CI->getType()->isIntegerTy(64) &&
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Constraints.size() >= 2 &&
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Constraints.size() >= 2 &&
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Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
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Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
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@ -65,6 +65,13 @@ define i32 @t32(i32 %x) nounwind {
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ret i32 %asmtmp
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ret i32 %asmtmp
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}
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}
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; CHECK: u32:
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; CHECK: bswapl
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define i32 @u32(i32 %x) nounwind {
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%asmtmp = tail call i32 asm "rorw $$8, ${0:w};rorl $$16, $0;rorw $$8, ${0:w}", "=r,0,~{cc},~{dirflag},~{flags},~{fpsr}"(i32 %x) nounwind
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ret i32 %asmtmp
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}
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; CHECK: s64:
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; CHECK: s64:
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; CHECK: bswapq
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; CHECK: bswapq
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define i64 @s64(i64 %x) nounwind {
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define i64 @s64(i64 %x) nounwind {
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