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[AArch64] Fix DAG selection for cmps for fp16 type

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Summary: When emitting comparison for fp16, in addition to promote the LHS and RHS to fp32, we need to change the VT as well.

Reviewers: t.p.northover

Subscribers: t.p.northover, aemerson, rengolin, llvm-commits

Differential Revision: http://reviews.llvm.org/D19922

llvm-svn: 269151
This commit is contained in:
Weiming Zhao 2016-05-11 01:26:32 +00:00
parent 0e8dbafdec
commit 4edbc2b61e
2 changed files with 13 additions and 0 deletions
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1
lib/Target/AArch64/AArch64ISelLowering.cpp
View File

@ -1229,6 +1229,7 @@ static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
if (VT == MVT::f16) {
LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, LHS);
RHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, RHS);
VT = MVT::f32;
}
return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS);
}

12
test/CodeGen/AArch64/half.ll
View File

@ -81,3 +81,15 @@ define void @test_trunc64(double %in, half* %addr) {
store half %val16, half* %addr
ret void
}
define i16 @test_fccmp(i1 %a) {
;CHECK-LABEL: test_fccmp:
;CHECK: fcmp
%cmp0 = fcmp ogt half 0xH3333, undef
%cmp1 = fcmp ogt half 0xH2222, undef
%x = select i1 %cmp0, i16 0, i16 undef
%or = or i1 %cmp1, %cmp0
%y = select i1 %or, i16 4, i16 undef
%r = add i16 %x, %y
ret i16 %r
}