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[SystemZ] Remove most hard-coded R1D instances for sibcalls
Indirect sibling calls need to use %r1 to hold the target address. This is currently hard-coded in many places. This is not only unnecessary, but makes future changes in this area difficult. This patch now encodes the target address as operand without hard coding a register in most places throughout the MI back-end. Code generation still always uses %r1, but this is now decided solely in one place in SystemZTargetLowering::LowerCall. NFC intended.
This commit is contained in:
Ulrich Weigand
parent
03a62f3073
commit
4f172e6801
@ -236,14 +236,15 @@ void SystemZAsmPrinter::emitInstruction(const MachineInstr *MI) {
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break;
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case SystemZ::CallBR:
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LoweredMI = MCInstBuilder(SystemZ::BR).addReg(SystemZ::R1D);
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LoweredMI = MCInstBuilder(SystemZ::BR)
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.addReg(MI->getOperand(0).getReg());
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break;
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case SystemZ::CallBCR:
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LoweredMI = MCInstBuilder(SystemZ::BCR)
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.addImm(MI->getOperand(0).getImm())
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.addImm(MI->getOperand(1).getImm())
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.addReg(SystemZ::R1D);
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.addReg(MI->getOperand(2).getReg());
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break;
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case SystemZ::CRBCall:
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@ -251,7 +252,7 @@ void SystemZAsmPrinter::emitInstruction(const MachineInstr *MI) {
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.addReg(MI->getOperand(0).getReg())
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.addReg(MI->getOperand(1).getReg())
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.addImm(MI->getOperand(2).getImm())
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.addReg(SystemZ::R1D)
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.addReg(MI->getOperand(3).getReg())
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.addImm(0);
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break;
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@ -260,7 +261,7 @@ void SystemZAsmPrinter::emitInstruction(const MachineInstr *MI) {
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.addReg(MI->getOperand(0).getReg())
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.addReg(MI->getOperand(1).getReg())
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.addImm(MI->getOperand(2).getImm())
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.addReg(SystemZ::R1D)
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.addReg(MI->getOperand(3).getReg())
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.addImm(0);
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break;
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@ -269,7 +270,7 @@ void SystemZAsmPrinter::emitInstruction(const MachineInstr *MI) {
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.addReg(MI->getOperand(0).getReg())
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.addImm(MI->getOperand(1).getImm())
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.addImm(MI->getOperand(2).getImm())
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.addReg(SystemZ::R1D)
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.addReg(MI->getOperand(3).getReg())
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.addImm(0);
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break;
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@ -278,7 +279,7 @@ void SystemZAsmPrinter::emitInstruction(const MachineInstr *MI) {
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.addReg(MI->getOperand(0).getReg())
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.addImm(MI->getOperand(1).getImm())
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.addImm(MI->getOperand(2).getImm())
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.addReg(SystemZ::R1D)
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.addReg(MI->getOperand(3).getReg())
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.addImm(0);
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break;
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@ -287,7 +288,7 @@ void SystemZAsmPrinter::emitInstruction(const MachineInstr *MI) {
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.addReg(MI->getOperand(0).getReg())
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.addReg(MI->getOperand(1).getReg())
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.addImm(MI->getOperand(2).getImm())
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.addReg(SystemZ::R1D)
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.addReg(MI->getOperand(3).getReg())
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.addImm(0);
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break;
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@ -296,7 +297,7 @@ void SystemZAsmPrinter::emitInstruction(const MachineInstr *MI) {
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.addReg(MI->getOperand(0).getReg())
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.addReg(MI->getOperand(1).getReg())
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.addImm(MI->getOperand(2).getImm())
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.addReg(SystemZ::R1D)
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.addReg(MI->getOperand(3).getReg())
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.addImm(0);
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break;
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@ -305,7 +306,7 @@ void SystemZAsmPrinter::emitInstruction(const MachineInstr *MI) {
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.addReg(MI->getOperand(0).getReg())
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.addImm(MI->getOperand(1).getImm())
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.addImm(MI->getOperand(2).getImm())
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.addReg(SystemZ::R1D)
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.addReg(MI->getOperand(3).getReg())
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.addImm(0);
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break;
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@ -314,7 +315,7 @@ void SystemZAsmPrinter::emitInstruction(const MachineInstr *MI) {
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.addReg(MI->getOperand(0).getReg())
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.addImm(MI->getOperand(1).getImm())
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.addImm(MI->getOperand(2).getImm())
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.addReg(SystemZ::R1D)
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.addReg(MI->getOperand(3).getReg())
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.addImm(0);
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break;
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@ -640,18 +640,22 @@ bool SystemZElimCompare::fuseCompareOperations(
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MachineOperand CCMask(MBBI->getOperand(1));
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assert((CCMask.getImm() & ~SystemZ::CCMASK_ICMP) == 0 &&
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"Invalid condition-code mask for integer comparison");
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// This is only valid for CompareAndBranch.
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// This is only valid for CompareAndBranch and CompareAndSibcall.
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MachineOperand Target(MBBI->getOperand(
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Type == SystemZII::CompareAndBranch ? 2 : 0));
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(Type == SystemZII::CompareAndBranch ||
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Type == SystemZII::CompareAndSibcall) ? 2 : 0));
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const uint32_t *RegMask;
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if (Type == SystemZII::CompareAndSibcall)
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RegMask = MBBI->getOperand(2).getRegMask();
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RegMask = MBBI->getOperand(3).getRegMask();
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// Clear out all current operands.
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int CCUse = MBBI->findRegisterUseOperandIdx(SystemZ::CC, false, TRI);
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assert(CCUse >= 0 && "BRC/BCR must use CC");
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Branch->RemoveOperand(CCUse);
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// Remove target (branch) or regmask (sibcall).
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// Remove regmask (sibcall).
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if (Type == SystemZII::CompareAndSibcall)
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Branch->RemoveOperand(3);
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// Remove target (branch or sibcall).
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if (Type == SystemZII::CompareAndBranch ||
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Type == SystemZII::CompareAndSibcall)
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Branch->RemoveOperand(2);
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@ -678,8 +682,10 @@ bool SystemZElimCompare::fuseCompareOperations(
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RegState::ImplicitDefine | RegState::Dead);
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}
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if (Type == SystemZII::CompareAndSibcall)
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if (Type == SystemZII::CompareAndSibcall) {
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MIB.add(Target);
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MIB.addRegMask(RegMask);
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}
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// Clear any intervening kills of SrcReg and SrcReg2.
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MBBI = Compare;
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@ -752,11 +752,14 @@ bool SystemZInstrInfo::PredicateInstruction(
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return true;
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}
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if (Opcode == SystemZ::CallBR) {
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const uint32_t *RegMask = MI.getOperand(0).getRegMask();
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MachineOperand Target = MI.getOperand(0);
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const uint32_t *RegMask = MI.getOperand(1).getRegMask();
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MI.RemoveOperand(1);
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MI.RemoveOperand(0);
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MI.setDesc(get(SystemZ::CallBCR));
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MachineInstrBuilder(*MI.getParent()->getParent(), MI)
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.addImm(CCValid).addImm(CCMask)
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.add(Target)
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.addRegMask(RegMask)
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.addReg(SystemZ::CC, RegState::Implicit);
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return true;
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@ -290,33 +290,32 @@ let isCall = 1, Defs = [R14D, CC] in {
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[(z_tls_ldcall tglobaltlsaddr:$I2)]>;
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}
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// Sibling calls. Indirect sibling calls must be via R1, since R2 upwards
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// are argument registers and since branching to R0 is a no-op.
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// Sibling calls.
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let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
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def CallJG : Alias<6, (outs), (ins pcrel32:$I2),
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[(z_sibcall pcrel32:$I2)]>;
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let Uses = [R1D] in
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def CallBR : Alias<2, (outs), (ins), [(z_sibcall R1D)]>;
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def CallBR : Alias<2, (outs), (ins ADDR64:$R2),
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[(z_sibcall ADDR64:$R2)]>;
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}
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// Conditional sibling calls.
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let CCMaskFirst = 1, isCall = 1, isTerminator = 1, isReturn = 1 in {
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def CallBRCL : Alias<6, (outs), (ins cond4:$valid, cond4:$R1,
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pcrel32:$I2), []>;
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let Uses = [R1D] in
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def CallBCR : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>;
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def CallBCR : Alias<2, (outs), (ins cond4:$valid, cond4:$R1,
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ADDR64:$R2), []>;
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}
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// Fused compare and conditional sibling calls.
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let isCall = 1, isTerminator = 1, isReturn = 1, Uses = [R1D] in {
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def CRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>;
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def CGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>;
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def CIBCall : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>;
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def CGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>;
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def CLRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>;
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def CLGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>;
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def CLIBCall : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>;
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def CLGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>;
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let isCall = 1, isTerminator = 1, isReturn = 1 in {
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def CRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3, ADDR64:$R4), []>;
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def CGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3, ADDR64:$R4), []>;
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def CIBCall : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3, ADDR64:$R4), []>;
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def CGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3, ADDR64:$R4), []>;
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def CLRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3, ADDR64:$R4), []>;
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def CLGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3, ADDR64:$R4), []>;
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def CLIBCall : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3, ADDR64:$R4), []>;
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def CLGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3, ADDR64:$R4), []>;
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}
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// A return instruction (br %r14).
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