1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-20 11:33:24 +02:00

[X86] Tag LOCK/REX64/DATA16/DATA32 instruction prefix scheduler classes

llvm-svn: 320266
This commit is contained in:
Simon Pilgrim 2017-12-09 21:27:03 +00:00
parent bd568f94fd
commit 4f4608b667

View File

@ -2036,19 +2036,23 @@ def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
// Lock instruction prefix
let SchedRW = [WriteMicrocoded] in
def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
let SchedRW = [WriteNop] in {
// Rex64 instruction prefix
def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>,
def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", [], IIC_NOP>,
Requires<[In64BitMode]>;
// Data16 instruction prefix
def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>,
def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", [], IIC_NOP>,
Requires<[Not16BitMode]>;
// Data instruction prefix
def DATA32_PREFIX : I<0x66, RawFrm, (outs), (ins), "data32", []>,
def DATA32_PREFIX : I<0x66, RawFrm, (outs), (ins), "data32", [], IIC_NOP>,
Requires<[In16BitMode]>;
} // SchedRW
// Repeat string operation instruction prefixes
// These use the DF flag in the EFLAGS register to inc or dec ECX